Real-time transmission and processing method and system of uplink burst mode passive optical network signal

Abstract

The application provides a real-time transmission and processing method and system for an uplink burst mode passive optical network signal, and the method comprises the following steps: receiving each group of signals in the continuously and parallelly transmitted uplink burst mode passive optical network signal and directly detecting and analog-to-digital converting the signals in real time to obtain each group of digital signals, wherein the passive optical network signal comprises a preamble sequence comprising a first sequence, a second sequence and a third sequence and a sequence carrying transmission information; overlapping each group of digital signals in real time at an overlap ratio to obtain each group of overlapped digital signals; performing real-time frequency domain clock recovery on each group of overlapped digital signals based on the first sequence, performing real-time frequency domain equalization on each group of digital signals after clock recovery based on the third sequence; performing real-time de-overlapping on each group of equalized digital signals in the time domain at the overlap ratio; and determining the frame header position of each group of de-overlapped digital signals based on the second sequence to realize real-time frame synchronization and obtain the recovered passive optical network signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of optical communication technology, and in particular to a real-time transmission and processing method and system for upstream burst mode passive optical network signals. BACKGROUND

[0002] With the advent of the digital age, data traffic is growing exponentially, and the demand for network bandwidth is increasingly urgent. In this context, 50G passive optical network (PON) technology has the characteristics of high bandwidth, low cost and high efficiency. With the increase of transmission rate and more complex network structure, the suddenness and instability of upstream signals increase, and digital signal processing needs to have higher processing speed and more complex algorithms to ensure the effective reception, processing and transmission of upstream signals.

[0003] The 50G passive optical network standard supports a 50Gbit / s downstream rate and 12.5Gbit / s, 25Gbit / s and 50Gbit / s upstream rates. The upstream non-return-to-zero (NRZ) signal is a transmission method of binary digital signals, in which 1 and 0 are represented by different electronic states, and there is no neutral state or other state. The characteristic of this coding method is that the energy of the pulse is more concentrated than the return-to-zero code, and the signal does not stop during transmission. For the upstream non-return-to-zero signal, it is a major challenge to realize the reception and transmission of real-time upstream burst mode signals of 50G passive optical networks.

[0004] The currently commonly used real-time upstream burst mode passive optical network digital signal processing system has the difficulties of slow convergence speed and error code concentration during convergence. The main reasons are: 1) the real-time upstream burst mode passive optical network signal has burstiness and uncertainty, and this burstiness makes it difficult for the receiving end to quickly and accurately establish and maintain synchronization, resulting in slower convergence speed; 2) the existing optical devices may have problems such as insufficient modulation bandwidth, slow rise time and long recovery time, which cannot meet the requirements of high-speed burst transmission, thereby limiting the convergence speed, and may cause signal distortion and error code concentration problems during convergence; 3) the distances of different optical network units and optical line terminals in the passive optical network are different, and the loss changes in the optical fiber link, etc., cause the optical power of the upstream burst signal to have a large fluctuation at the receiving end. In addition, various noise sources in the system, such as thermal noise and shot noise, also interfere with the signal. When the optical power changes greatly or the noise is strong, the detection performance of the receiving end decreases, and errors are easily generated, and during the convergence process, these factors will superimpose on each other, causing error code concentration and prolonging the convergence time.

[0005] Therefore, it is of great practicality and practical significance to study a real-time processing method and system for upstream burst mode passive optical network signals. SUMMARY

[0006] In view of this, the embodiments of the present application provide an uplink burst mode passive optical network signal real-time transmission and processing method and system to eliminate or improve one or more defects in the prior art.

[0007] The first aspect of the present application provides an uplink burst mode passive optical network signal real-time transmission and processing method, which comprises the following steps:

[0008] Receiving a plurality of groups of signals in the uplink burst mode passive optical network signal continuously transmitted by a sending end, wherein each group of signals is multiplexed and transmitted in parallel, the passive optical network signal comprises a preamble sequence and a sequence carrying sending information, and the preamble sequence comprises a first sequence for frame detection and phase estimation, a second sequence for frame synchronization, and a third sequence for channel estimation;

[0009] Directly detecting and analog-to-digital converting each group of signals in real time to obtain each group of digital signals;

[0010] Performing real-time overlap operation on each group of digital signals at a first overlap ratio to obtain each group of overlapped digital signals;

[0011] Performing real-time frequency domain clock recovery on each group of overlapped digital signals based on the first sequence in each group of overlapped digital signals, and performing real-time frequency domain equalization on the clock-recovered each group of digital signals based on the third sequence in the clock-recovered each group of digital signals;

[0012] Performing real-time de-overlap operation on each group of equalized digital signals in the time domain at the first overlap ratio;

[0013] Determining the frame header position of each group of de-overlapped digital signals based on the second sequence in each group of de-overlapped digital signals to perform real-time frame synchronization on each group of de-overlapped digital signals, thereby obtaining the recovered passive optical network signal.

[0014] In some embodiments of the present application, the real-time frequency domain clock recovery on each group of overlapped digital signals based on the first sequence in each group of overlapped digital signals comprises:

[0015] Through a feedforward initial phase estimation module, a comparison algorithm of tree structure search is adopted to determine the frequency point with power peak value in the first sequence in the frequency domain based on the first sequence in each group of overlapped digital signals, so as to realize frame detection;

[0016] Through a feedforward initial phase estimation module, parallel feedforward initial sampling phase offset estimation is performed on the first sequence in the frequency domain to feedback and compensate the phase of the overlapped corresponding group of digital signals containing the first sequence in the feedback loop module, wherein the output time of the frame detection and the initial sampling phase offset estimation is aligned.

[0017] The feedback loop module performs Godard-based sampling phase estimation, loop filtering, digital numerically controlled oscillation and phase compensation on the corresponding group of digital signals after overlap without the first sequence in the frequency domain to perform real-time frequency domain clock recovery on the group of digital signals after overlap.

[0018] In some embodiments of the present application, the third sequence in the group of digital signals after clock recovery performs real-time frequency domain equalization on the group of digital signals after clock recovery, including:

[0019] The feedforward least mean square error algorithm is used to estimate the channel coefficients of the corresponding group of digital signals based on the third sequence in the group of digital signals after clock recovery and the corresponding group of digital signals after clock recovery containing the third sequence in the frequency domain.

[0020] The feedback decision-directed least mean square algorithm based on interpolation fast Fourier transform is used to estimate the updated channel coefficients of the corresponding group of digital signals after clock recovery based on the corresponding group of digital signals after clock recovery without the third sequence in the frequency domain, so as to perform real-time frequency domain equalization on the group of digital signals after clock recovery based on the channel coefficients and the updated channel coefficients.

[0021] In some embodiments of the present application, the second sequence in the group of digital signals after overlap removal is used to determine the frame header position of the group of digital signals after overlap removal to perform real-time frame synchronization on the group of digital signals after overlap removal, including:

[0022] Each of the two consecutive groups of digital signals after overlap removal is reconstructed to obtain a plurality of groups of reconstructed digital signals.

[0023] The sliding cross-correlation is performed based on the second sequence in the group of digital signals after overlap removal and the group of reconstructed signals to obtain a plurality of cross-correlation values, and the binary tree search algorithm is used to determine the position of the maximum peak based on the plurality of cross-correlation values to determine the frame header position of the group of digital signals after overlap removal.

[0024] The group of digital signals after overlap removal is synchronized in real time based on the frame header position.

[0025] In some embodiments of the present application, the group of signals in the upstream burst mode passive optical network signal is generated by the sending end by performing the following steps in advance:

[0026] The bit sequence to be sent is sequentially divided into a plurality of groups with a preset parallel degree to obtain a plurality of sequence groups, wherein the bit sequence to be sent includes a preamble sequence and a sequence carrying sending information, and the preamble sequence includes a sequence for frame detection and phase estimation, a sequence for frame synchronization and a sequence for channel estimation.

[0027] overlapping each group of sequences with a second overlap ratio to obtain each group of overlapped sequences, wherein the second overlap ratio is same as the first overlap ratio;

[0028] performing fast Fourier transform, resampling, filtering and inverse Fourier transform on each group of overlapped sequences to obtain each group of time domain digital signals;

[0029] performing overlap removal on each group of time domain digital signals with the second overlap ratio to obtain each group of overlap removed time domain digital signals;

[0030] performing digital-to-analog conversion and intensity modulation on each group of overlap removed time domain digital signals to obtain each group of signals to generate an upstream burst mode passive optical network signal.

[0031] In some embodiments of the present application, the overlapping operation comprises overlapping the end of the previous group of data according to the overlap ratio for each group of data, wherein the data of the overlapping part is 0 for the first group of data.

[0032] In some embodiments of the present application, the length of the first sequence is 192, which is composed of a plurality of sequences of 0 and 1 in the time domain and exhibits two frequency points at half baud rate in the frequency domain; the length of the second sequence is 96, which comprises three groups of 32-symbol random sequences multiplied by coefficients 1, 1 and -1 respectively; and the third sequence comprises random symbols with a length of 768.

[0033] In some embodiments of the present application, after performing real-time overlapping operation on each group of digital signals with the first overlap ratio to obtain each group of overlapped digital signals, the method further comprises:

[0034] performing fast Fourier transform and matched filtering on each group of overlapped digital signals to obtain each group of matched frequency domain digital signals.

[0035] In some embodiments of the present application, after performing real-time frequency domain clock recovery on each group of overlapped digital signals based on the first sequence in each group of overlapped digital signals, the method further comprises:

[0036] performing downsampling operation on each group of clock recovered digital signals in the frequency domain to obtain each group of digital signals with 1-fold parallelism.

[0037] The second aspect of the present application provides an uplink burst mode passive optical network signal real-time transmission and processing system, comprising: a field programmable gate array, a photodetector and a high-speed digital-to-analog converter, the photodetector is used for receiving each group of signals in the uplink burst mode passive optical network signal transmitted by a sending end in continuous parallel transmission, directly detecting each group of signals in real time to obtain each group of analog electrical signals; the high-speed digital-to-analog converter is used for performing real-time analog-to-digital conversion on each group of analog electrical signals to obtain each group of digital signals; the field programmable gate array comprises a computer device, the computer device comprises a processor and a memory, the memory stores computer instructions, and the processor is used for executing the computer instructions stored in the memory; when the computer instructions are executed by the processor, the system implements the following steps of the uplink burst mode passive optical network signal real-time transmission and processing method of the first aspect:

[0038] Each group of digital signals is subjected to real-time overlap operation at a first overlap ratio to obtain each group of digital signals after overlap;

[0039] Each group of digital signals after overlap is subjected to real-time frequency domain clock recovery based on a first sequence in each group of digital signals after overlap, and each group of digital signals after clock recovery is subjected to real-time frequency domain equalization based on a third sequence in each group of digital signals after clock recovery;

[0040] Each group of digital signals after equalization is subjected to real-time de-overlap operation in the time domain at the first overlap ratio;

[0041] The frame header position of each group of digital signals after de-overlap is determined based on a second sequence in each group of digital signals after de-overlap, so as to perform real-time frame synchronization on each group of digital signals after de-overlap, thereby obtaining the recovered passive optical network signal.

[0042] The third aspect of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the following steps of the uplink burst mode passive optical network signal real-time transmission and processing method of the first aspect:

[0043] Each group of digital signals is subjected to real-time overlap operation at a first overlap ratio to obtain each group of digital signals after overlap; wherein each group of digital signals as input is obtained by directly detecting and analog-to-digital converting each group of signals in the uplink burst mode passive optical network signal transmitted by a sending end in continuous parallel transmission in real time, the passive optical network signal comprises a preamble sequence and a sequence carrying sending information, and the preamble sequence comprises a first sequence for frame detection and phase estimation, a second sequence for frame synchronization and a third sequence for channel estimation;

[0044] recovering the overlapped digital signals in real time based on the first sequence in the overlapped digital signals, and equalizing the clock-recovered digital signals in real time based on the third sequence in the clock-recovered digital signals;

[0045] performing real-time overlap removal on the equalized digital signals in the time domain at the first overlap ratio;

[0046] determining the frame header position of the overlap-removed digital signals based on the second sequence in the overlap-removed digital signals, and performing real-time frame synchronization on the overlap-removed digital signals, thereby obtaining the recovered passive optical network signal.

[0047] The fourth aspect of the present application provides a computer program product comprising computer instructions which, when executed by a processor, implement the following steps of the uplink burst mode passive optical network signal real-time transmission and processing method of the first aspect:

[0048] performing real-time overlap operation on the digital signals at a first overlap ratio, thereby obtaining overlapped digital signals; wherein the input digital signals are obtained by directly detecting and analog-to-digital converting the received uplink burst mode passive optical network signal transmitted in continuous parallel mode by the sending end in real time, the passive optical network signal comprising a preamble sequence and a sequence carrying sending information, the preamble sequence comprising a first sequence for frame detection and phase estimation, a second sequence for frame synchronization, and a third sequence for channel estimation;

[0049] recovering the overlapped digital signals in real time based on the first sequence in the overlapped digital signals, and equalizing the clock-recovered digital signals in real time based on the third sequence in the clock-recovered digital signals;

[0050] performing real-time overlap removal on the equalized digital signals in the time domain at the first overlap ratio;

[0051] determining the frame header position of the overlap-removed digital signals based on the second sequence in the overlap-removed digital signals, and performing real-time frame synchronization on the overlap-removed digital signals, thereby obtaining the recovered passive optical network signal.

[0052] The uplink burst mode passive optical network signal real-time transmission and processing method and system can realize fast convergence based on the preamble sequence and effective recovery of the passive optical network signal.

[0053] Additional advantages, objects, and features of the application will be set forth in part by the description that follows, and will become apparent to those skilled in the art upon examination of the following detailed description and drawings in which

[0054] Those skilled in the art will appreciate that the objects and advantages of the application can be practiced without resorting to the details of the following description. The following detailed description and drawings are provided to describe the preferred embodiments of the application and are not intended to limit the scope of the application. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description, serve to explain the principles of the application. The components in the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. For purposes of clarity and understanding, it is to be understood that certain portions of the drawings can be exaggerated and others omitted in order to depict certain aspects of the application.

[0056] Figure 1 Flow chart of the real-time transmission and processing method of the upstream burst mode PON signal in an embodiment of the application;

[0057] Figure 2 Structure example of the preamble sequence in an embodiment of the application;

[0058] Figure 3 Implementation example of the real-time frequency domain clock recovery in an embodiment of the application;

[0059] Figure 4 Implementation example of the real-time frequency domain equalization in an embodiment of the application;

[0060] Figure 5 Implementation example of the real-time frame synchronization in an embodiment of the application;

[0061] Figure 6 Flow chart of the real-time transmission and processing method of the upstream burst mode PON signal in an embodiment of the application;

[0062] Figure 7 Structure example of the real-time transmission and processing system of the upstream burst mode PON signal in an embodiment of the application;

[0063] Figure 8 Clock error result using initial phase estimation in an embodiment of the application;

[0064] Figure 9A diagram of mean square error results obtained by using frequency domain equalization in an embodiment of the present application;

[0065] Figure 10 A diagram of bit error distribution of transceiver bit XOR at a received optical power of -23dBm in an embodiment of the present application;

[0066] Figure 11 A diagram of received optical power-bit error rate performance of signals transmitted by a transmitting end after back-to-back and fiber channel transmission and recovery in an embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be described in further detail below with reference to embodiments and drawings. Here, the illustrative embodiments of the present application and their descriptions are used to explain the present application, but are not intended to limit the present application.

[0068] It should also be noted that, in order to avoid obscuring the present application due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present application are shown in the drawings, and other details not closely related to the present application are omitted.

[0069] It should be emphasized that the term “comprises / comprising” as used herein indicates the presence of the stated features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0070] It should also be noted that, unless otherwise specified, the term “connected” as used herein can not only mean direct connection, but also indirect connection in the presence of an intermediate.

[0071] In the following, embodiments of the present application will be described with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0072] In order to solve the problems of slow convergence speed and error code concentration during digital processing of real-time uplink burst mode passive optical network signals in the prior art, an embodiment of the present application proposes a real-time transmission and processing method and system for uplink burst mode passive optical network signals. The method can achieve fast convergence, implement a real-time transmission and processing system for uplink burst mode passive optical network signals in a resource-limited field programmable gate array (FPGA), and has good signal recovery performance.

[0073] Figure 1 A flowchart of the real-time transmission and processing method for uplink burst mode passive optical network signals in an embodiment of the present application is shown in FIG. Figure 1 The method is executed by a receiving end and includes the following steps:

[0074] In step S110, each group of signals in the upstream burst mode passive optical network signal transmitted by the transmitting end in a continuous and parallel manner is received, wherein the upstream burst mode passive optical network signal includes a preamble sequence and a sequence carrying transmission information, and the preamble sequence includes a first sequence for frame detection and phase estimation, a second sequence for frame synchronization, and a third sequence for channel estimation.

[0075] In the transmission process of the upstream burst mode signal, a plurality of groups of signals in the continuous transmission passive optical network signal are transmitted in a multiplexed and parallel manner. The convergence process of all digital signal processing algorithms must be completed within the transmission time of the preamble sequence of each frame, and therefore clock recovery with fast convergence is required to improve transmission efficiency. However, the traditional clock recovery algorithm needs a long time to complete convergence, and is not suitable for direct application to the detection of burst mode signals. Therefore, a DSP (digital signal processing) algorithm with fast convergence is designed.

[0076] In an embodiment, the structure of the preamble sequence designed by the present application is as shown in Figure 2 The preamble sequence mainly includes three parts: a first sequence (or preamble sequence A), a second sequence (or preamble sequence B), and a third sequence (or preamble sequence C). The preamble sequence A includes 192 symbols, is composed of a repeated sequence [0, 1] in the time domain, and exhibits two frequency points located at half the baud rate (i.e. Rs / 2, Rs represents the baud rate) in the frequency domain, and is used for burst frame detection and sampling phase offset estimation. The preamble sequence A occupies two complete clock periods, wherein the first period is used for frame detection, and the second period is used for sampling phase offset estimation. The preamble sequence B includes 96 symbols, and is used for frame synchronization. Specifically, the preamble sequence B includes three groups of 32-symbol random sequences Pn multiplied by the coefficients of [1, 1, -1] to obtain sequences, thereby ensuring that the synchronization peak value has sufficient power to achieve accurate frame synchronization. The preamble sequence C includes 768 random symbols, and is used for estimating the initial tap coefficients (or initial channel coefficients) of the burst mode frequency domain equalizer. Therefore, the total length of the preamble sequence is 1056, and the transmission time under a 25Gbit / s OOK (on-off keying) signal is about 42ns. The payload length of the sequence carrying transmission information can be set to The above preamble sequence structure is only an example and does not constitute a limitation, and the above parameters can be adjusted for other communication requirements. Using the preamble sequence, fast convergence of the real-time upstream burst mode passive optical network signal can be achieved, thereby facilitating signal recovery and effective reception by the receiving end.

[0077] In an embodiment of the present application, each group of signals in the upstream burst mode PON signal is generated by the following steps performed by the transmitting end in advance:

[0078] sequentially divide the bit sequence to be transmitted into a plurality of groups at a preset parallelism, to obtain a plurality of groups of sequences, wherein the bit sequence to be transmitted includes a preamble sequence and a sequence carrying transmission information, and the preamble sequence includes a sequence for frame detection and phase estimation, a sequence for frame synchronization, and a sequence for channel estimation;

[0079] perform an overlap operation on each group of sequences at a second overlap ratio, to obtain each group of overlapped sequences, wherein the second overlap ratio is the same as the first overlap ratio;

[0080] perform a fast Fourier transform, resampling, filtering, and inverse Fourier transform on each group of overlapped sequences, to obtain each group of time-domain digital signals;

[0081] perform a de-overlap operation on each group of time-domain digital signals at the second overlap ratio, to obtain each group of time-domain digital signals after de-overlap;

[0082] perform digital-to-analog conversion and intensity modulation on each group of time-domain digital signals after de-overlap, to obtain each group of signals, to generate an upstream burst mode PON signal.

[0083] In the above steps, in the FPGA, the parallelism refers to the number of parallel transmission and processing of data per clock cycle. The 1x parallelism represents the number of parallel computing based on the number of parallel transmission of data; the 1.125x parallelism represents that the number of parallel computing is increased to 1.125 times of the original number by oversampling in the data processing process. Due to the bandwidth limitation of existing transmission devices, the overlap operation helps to reduce the impairment such as inter-symbol interference, and in the digital signal processing, especially in the filtering (such as shaping filtering) of long signals, directly filtering the entire signal may cause huge computation. Therefore, the long signal is grouped and divided into a plurality of shorter blocks. In an example, the transmitting end divides the bit sequence to be transmitted into a plurality of groups according to the 1x parallelism, for example, assuming that the length of the bit sequence to be transmitted is 8000 and the 1x parallelism is 80, the above grouping process is the process of converting the one-dimensional sequence with a length of 8000 into a two-dimensional matrix with a size of 80 100, i.e., into 100 groups, and each group of sequences contains 80 symbols. When transmitting the sequence, 80 data are transmitted in parallel at each time, and 100 groups of sequences are transmitted in sequence, i.e., the frame of bit sequence with a length of 8000 is completely transmitted to the receiving end by 100 times of parallel and continuous transmission.

[0084] In an embodiment, the specific way of the overlap operation is to overlap the end of the previous group of data with the current group of data according to a second overlap ratio, wherein for the first group of data, the data in the overlap part is all 0. For example, assuming the overlap length is 20, after the overlap operation, the two-dimensional matrix will become 100 100 100 dimensions, the first 20 data of the first group of data is 0, the last 80 data is the original 80 data of the group, the first 20 data of the second group of data is the last 20 data of the first group of data, and the last 80 data is the original 80 data of the group, and so on to get the overlapped data of the third group to the last group (the overlap way is similar to the second group).

[0085] In a specific embodiment, for the generation and transmission of the real-time upstream burst mode passive optical network signal, as shown in Figure 6 , first, the bit sequence to be transmitted is grouped and overlapped by step S1-1 to protect the signal and eliminate the inter-symbol interference; then, the fast Fourier transform is used to convert each group of time domain signals to the frequency domain, and the frequency domain signals are resampled to 1.125 samples per symbol by step S1-2 to obtain a resampled signal with a sampling rate of 1.125 times (the parameter matching of the circuit structure shown in Figures 3-5 , if other multiples of resampling are used, the parameters in the circuit structure need to be adjusted); then, the root raised cosine filter is used to perform shaping filtering on each group of resampled signals by step S1-3, and the shaping filter will perform filtering operation on each frame (including the overlap part). The filter adjusts the spectrum of the signal according to its frequency response characteristics. The filtered frequency domain signals are converted into time domain signals by inverse Fourier transform by step S1-4, and the output time domain signals are removed according to the same overlap ratio S as the overlap operation. Due to the limitation of transmission hardware, in order to meet the transmission rate of 25G, the overlap removal operation needs to be performed to remove the overlap part. Finally, the digital-to-analog conversion and intensity modulation are used to generate the upstream burst mode passive optical network signal to be transmitted, and the signal is transmitted to the receiving end through the optical fiber.

[0086] It should be noted that the signal without processing by the sending end cannot be sampled at 1.125 times the rate without introducing additional phase damage, and there will be an impact of inter-symbol interference, so the integrity of the signal cannot be protected. After the signal is transmitted through the optical fiber, it will be severely affected. Even if the received optical power is increased, the bit error rate usually does not reach the threshold, and the signal cannot be normally recovered.

[0087] Step S120, directly detecting and analog-to-digital converting the signals in real time to obtain digital signals.

[0088] After the receiving end receives each group of signals transmitted by the sending end in continuous parallel transmission, the receiving end performs real-time recovery processing on each group of signals by means of receiving and processing at the same time.

[0089] In step S130, real-time overlap operation is performed on each group of digital signals at a first overlap ratio, to obtain each group of overlapped digital signals.

[0090] In the receiving end, the manner of overlap operation is the same as that of the sending end. Through the overlap operation in this step, the overlapped time-domain signals are obtained. In fact, the overlapped time-domain signals can also be regarded as 1.125 times sampling overlap signals. Since the frequency-domain clock recovery in the embodiment of the present application is applicable to a scenario greater than 1 times sampling rate, this step is necessary in order to compensate for the phase noise of the received signals.

[0091] In step S140, real-time frequency-domain clock recovery is performed on each group of overlapped digital signals based on the first sequence in each group of overlapped digital signals, and real-time frequency-domain equalization is performed on each group of clock-recovered digital signals based on the third sequence in each group of clock-recovered digital signals.

[0092] In order to perform frequency-domain clock recovery and frequency-domain equalization, step S140 needs to perform clock recovery and equalization on the time-domain overlap signals obtained in step S130 in the frequency domain, that is, after the overlap step, the method further comprises: performing fast Fourier transform and matched filtering on each group of overlapped digital signals to obtain each group of matched frequency-domain digital signals, so as to perform real-time frequency-domain clock recovery on each group of matched frequency-domain digital signals, as shown in steps S4-1 and S4-2. Figure 6

[0093] In addition, after the clock recovery step, the method further comprises: performing downsampling operation on each group of clock-recovered digital signals in the frequency domain to obtain each group of digital signals at 1 times parallelism, so as to perform real-time frequency-domain equalization on each group of digital signals at 1 times parallelism, as shown in step S4-4. Figure 6

[0094] In an embodiment of the present application, the real-time frequency-domain clock recovery performed on each group of overlapped digital signals based on the first sequence in each group of overlapped digital signals comprises the following steps:

[0095] Through the feedforward initial phase estimation module, a comparison algorithm based on tree structure search is adopted to determine the frequency point with a power peak in the first sequence in the frequency domain based on the first sequence in each group of overlapped digital signals, so as to realize frame detection.

[0096] ​​The feedforward initial phase estimation module performs feedforward initial sampling phase offset estimation in the frequency domain based on the first sequence in parallel, so as to feed back and compensate the phase of the corresponding group of digital signals after overlapping of the first sequence in the feedback loop module, wherein the frame detection and the output time of the initial sampling phase offset estimation are aligned.

[0097] Through the feedback loop module, the overlapping digital signals that do not contain the first sequence are sampled and phase estimated, loop filtered, digitally controlled oscillation and phase compensation based on Godard in the frequency domain, so as to perform real-time frequency domain clock recovery for each overlapping digital signal.

[0098] Specifically, for the feedforward initial phase estimation module, the feedforward initial phase of the first sequence is estimated using non-integer multiple sampling, and its phase information can be expressed as:

[0099]

[0100] in, This is the sampling multiple. For operations involving complex angle values, The received frequency tone is the initial sampling phase offset. For the conjugate of the corresponding frequency points, For frequency point location, The number of points and the size of the Fourier transform (FFT) should be chosen, allowing the upper and lower bounds to be integers. The first sequence has a distinct peak in the frequency domain, with power concentrated at a single point, which corresponds to the pitch.

[0101] For frequency domain clock recovery of the Godard-based feedback loop module, non-integer multiple oversampling is used for sampling phase estimation, and the estimated timing error can be expressed as:

[0102]

[0103] in, The roll-off factor, The imaginary part of a complex number. This is a conjugate operation.

[0104] Figure 3 Here is an example diagram illustrating the implementation of real-time frequency domain clock recovery for burst modes based on sampled phase offset estimation, as shown below. Figure 3 The diagram illustrates the implementation of frame detection and real-time frequency domain clock recovery for burst mode based on preamble sequence A, including sampling phase offset estimation. In the feedforward initial phase estimation module, the frame detection module detects the power peak of preamble sequence A to confirm the arrival of the burst signal. If the preset frequency point has the maximum power, it can be considered that preamble sequence A has been detected, indicating that the burst frame has arrived. The frequency range used in this system is [frequency range missing]. and where N is the FFT size. The frequency bin with the largest power is found using a comparison algorithm based on tree structure search. The tree structure search contains 7 layers, with the parallelism of each layer gradually decreasing. And to ensure stability and correctness, the clock cycles required by the tree structure search of each layer are gradually reduced. The total clock cycles of the tree structure search are set to 29, leaving a certain margin, which can be appropriately reduced when resources are relatively abundant and timing problems are not serious.

[0105] The initial phase estimation is also performed at the same time of frame detection, using and the frequency bins around the peak frequency bin for estimating the initial sampling phase offset. It should be noted that since the frame detection and the initial sampling phase offset estimation are performed at the same time, the output time of the frame detection and the initial sampling phase offset estimation should be aligned by the judge. Therefore, a delay of 13 clock cycles is added after the frame detection module. When the frame detection module outputs the signal that the burst frame arrives, the judge allows the estimated initial sampling phase offset to be sent into the feedback loop module of the burst mode frequency domain clock recovery, and compensates the clock error according to the initial phase offset value, so as to realize the fast convergence of the clock recovery. The compensated result can be directly found by looking up the table for compensation, which can avoid the calculation of the frequency domain interpolator and reduce the processing time.

[0106] The feedback loop module of the burst mode frequency domain clock recovery mainly consists of a frequency domain interpolator , a sampling phase estimation module based on Godard (selecting the frequency bin to sum), a loop filter, and a numerically controlled oscillator. The sum operation is realized by summing two by two through a binary tree structure, which requires 7 clock cycles or delays. The phase information or timing error obtained by the sampling phase estimation module based on Godard is sent into the loop filter to improve the stability and response ability of the feedback link. Then, the control signal from the loop filter is sent into the numerically controlled oscillator (NCO) module, which generates the fractional and integer intervals required by the interpolator. The output value is controlled within the preset range by using combinational logic rather than sequential logic, so as to be completed within one clock cycle, reducing the operation time while meeting the requirement that the NCO is updated once per cycle. Considering the complexity, timing violation, and resource usage of the division operation module, the clock cycle is set to the default pipeline calculation time of the Vivado IP core: 39 clock cycles or delays. Finally, the calculated fractional and integer intervals are sent into the lookup table to find the value corresponding to the frequency domain interpolator, where .

[0107] For the initial sampling phase estimated value and the phase value calculated by the Godard-based clock recovery feedback loop, a judgment and selection need to be made. When the burst frame detection detects the peak power, that is, when the first frame data arrives, the burst frame flag bit is set to 1, and the phase value of the initial phase estimation is output at this time. Since there is a loop delay in the feedback loop, the phase value of the initial phase estimation is used to enter the frequency domain interpolator for phase compensation when the phase value calculated by the Godard-based clock recovery feedback loop has not been calculated. The feedback loop delay of the Godard clock recovery is accurately calculated by the counter, and when the phase value calculated by the Godard clock recovery feedback loop is calculated, the phase value input into the frequency domain interpolator is switched to the value.

[0108] The core of this part is to realize fast frequency domain clock recovery through burst frame detection and sampling phase estimation, and according to the design idea of Figure 3 , the burst mode fast convergence clock recovery algorithm can be realized on the FPGA, and accurate timing information is provided for subsequent signal processing. The delay time of the module design has a certain margin, and if it is necessary to reduce the loop calculation delay later, it can be reduced and adjusted according to the resource situation. According to the above process, a burst mode frequency domain clock recovery unit based on a field programmable gate array can be built.

[0109] In an embodiment of the present application, the third sequence in each group of digital signals after clock recovery is used for real-time frequency domain equalization of each group of digital signals after clock recovery, including the following steps:

[0110] The feedforward minimum mean square error algorithm is used to estimate the channel coefficients of the group of digital signals in the frequency domain based on the third sequence in each group of digital signals after clock recovery and the corresponding group of digital signals after clock recovery containing the third sequence;

[0111] The feedback decision-directed least mean square algorithm based on interpolation fast Fourier transform is used to estimate the updated channel coefficients of the group of digital signals in the frequency domain based on the corresponding group of digital signals after clock recovery not containing the third sequence, and the real-time frequency domain equalization of each group of digital signals after clock recovery is performed based on the channel coefficients and the updated channel coefficients.

[0112] Specifically, the channel estimation is performed by the feedforward minimum mean square error (MMSE) algorithm, and the definition of the channel coefficient can be represented as:

[0113]

[0114] Wherein, is the expectation operation, is the preamble sequence C used for channel estimation, is the signal of the received preamble sequence C;

[0115] Since the channel is variable, the impairment of each set of signal data received from the transmitter multiple times is different. Therefore, the channel coefficients are updated using a feedback-decision-guided least mean square algorithm. The updated channel coefficients can be defined as follows:

[0116]

[0117] in, Step size, For channel coefficients, The gradient value of MSE can be expressed as:

[0118]

[0119] in, The equalized signal The judgment value, This is the received signal.

[0120] Figure 4 An example diagram of a real-time implementation of a burst-mode frequency domain equalizer based on feedforward channel estimation of the preamble sequence C is shown below. Figure 4 The diagram illustrates the implementation structure of burst-mode frequency equalization based on a preamble sequence C. It employs a feedforward minimum mean square error (MMS) algorithm for channel estimation and a feedback-guided MMS algorithm for updating channel coefficients. Burst-mode frequency equalization uses the calculated channel coefficients to compensate for the signal; since the channel is constantly changing, the channel coefficients need to be continuously updated. In the MMS algorithm for channel estimation, two averaging operations E() are required, where y is the 8-frame received signal after clock recovery and synchronization. Figure 3 The output, x, is the preamble sequence C transmitted in 8 clock cycles. The averaging operation can be simplified by adding the outputs of 8 multiplications and then left-shifting the resulting bits by 3 bits, thus saving FPGA resources. The division module, however, consumes significant resources for dividing two complex values. Therefore, the division operation requires 59 clock cycles or a delay to avoid timing issues and ensure sufficient FPGA resources. To compensate for the channel response, the signal at the frequency point (parallelism) needs to be multiplied by the corresponding tap coefficients or channel coefficients. However, the channel response is dynamic, thus requiring a feedback decision-oriented least mean square algorithm to track and update the tap coefficients.

[0121] The decision-oriented least mean square algorithm has high computational complexity due to the need for a 128-point FFT. Therefore, this invention proposes a simplified feedback decision-oriented least mean square algorithm based on interpolated FFT. After frequency domain equalization and IFFT, only 8 time-domain symbols (i.e., 1-beat signals) are selected at equal intervals for hard decision. The 8-point FFT converts the hard decision symbols (positive numbers are 1, negative numbers are -1) into frequency domain signals. To calculate the decision error, 8 signals Z are selected from the 128 frequency points before IFFT at equal intervals, and delayed by 70 clock cycles. The decision error can be calculated by The interpolation operation repeats the error e of each element 16 times to reconstruct 128 approximate decision errors. The computational complexity is reduced by sacrificing accuracy.

[0122] To align and , a delay of 80 clock cycles is required. The minimum mean square error channel estimation is a feedforward algorithm used to obtain the initial tap coefficients. Then, the tap coefficients can be updated by the feedback decision-directed least mean square algorithm. The initial tap coefficients accelerate the convergence speed of the feedback decision-directed least mean square algorithm.

[0123] The core of this part is to realize fast-converging burst-mode frequency-domain equalization through the feedforward least mean square error and the feedback decision-directed least mean square algorithm, to ensure channel equalization and data recovery of the burst signal. According to the above flow chart, a burst-mode frequency-domain equalizer unit based on a field programmable gate array can be built.

[0124] As shown in steps S4-3 and S4-5, Figure 6 The burst-mode clock recovery is responsible for accurately synchronizing the timing of the received signal, ensuring that data is sampled at the correct time to prevent distortion and information loss. The burst-mode equalization plays a crucial role in compensating for channel impairments such as inter-symbol interference. The preamble sequence allows the burst-mode equalization to quickly initialize and converge its equalization coefficients, ensuring effective processing of each incoming burst data. Through the combination of burst-mode clock recovery and burst-mode equalization, even in the face of burst-mode challenges, the reliability of high-speed uplink signal processing can be promoted.

[0125] Step S150, performing real-time de-overlapping operation on the equalized digital signals in the time domain according to the first overlap ratio.

[0126] In this step, the de-overlapping operation is performed on the equalized digital signals in the time domain, that is, after the equalization step, the method performs inverse Fourier transform on the equalized digital signals to convert them into time-domain digital signals, thereby performing real-time de-overlapping operation on the time-domain digital signals, as shown in step S4-6. Figure 6

[0127] Step S160, determining the frame header position of the de-overlapped digital signals based on the second sequence in the de-overlapped digital signals, to perform real-time frame synchronization on the de-overlapped digital signals, thereby obtaining the recovered passive optical network signal.

[0128] In this step or in the​Figure 6 After step S5, the recovered PON signal is obtained by making a decision on the frame-synchronized digital signals, as shown in step S6. Figure 6 As shown in step S6.

[0129] In an embodiment of the present application, the frame header position of the overlap-removed digital signals is determined based on the second sequence in the overlap-removed digital signals, so as to perform real-time frame synchronization on the overlap-removed digital signals, including the following steps:

[0130] The overlap-removed digital signals are reconstructed to obtain a plurality of reconstructed digital signals.

[0131] The sliding cross-correlation is performed on the second sequence in the overlap-removed digital signals and the reconstructed digital signals, so as to obtain a plurality of cross-correlation values. The binary tree search algorithm is adopted to determine the position of the maximum peak value based on the plurality of cross-correlation values, so as to determine the frame header position of the overlap-removed digital signals.

[0132] The overlap-removed digital signals are frame-synchronized in real time based on the frame header position.

[0133] Figure 5 An example diagram for real-time implementation of the frame synchronization based on the preamble sequence B is shown in FIG. 3. Figure 5As shown, the sampling rate of the input signal is 1sps and the parallelism is 96. By reconstructing two consecutive taps, a tap with parallelism of 192 is generated. In this reconstructed tap, the preamble B of the receiver can be detected. The sequence in the preamble B consists of 1 and -1, which is used for the sliding cross-correlation operation with the reconstructed tap. Since the preamble B consists of 1 and -1, the traditional multiplication operation in the sliding cross-correlation operation can be replaced by addition and subtraction operations, which not only reduces the DSP resource occupation, but also relieves the timing design problem. At the same time, all the 32 parallelism addition and subtraction operations are designed with pipeline, effectively solving the potential wiring congestion problem. After 161 times of sliding cross-correlation operation, 161 cross-correlation values are obtained, and the entire calculation process requires 18 clock cycles. These cross-correlation values are then reorganized into three matrices, each containing 225 values. By adding two all-zero matrices (each containing 32 zeros) in the reconstruction process, perfect padding of the matrix is achieved. The three matrices are then weighted multiplied according to the coefficients of [1, 1, -1], and finally summed to generate a comprehensive matrix containing 225 values. This process takes 6 clock cycles to complete. After the cross-correlation value processing is completed, a binary tree search algorithm is used to detect the maximum peak value. This algorithm gradually narrows down the operation range by comparing two candidate values and retaining the larger value in each round, and finally determines the maximum peak value. The entire search process takes 61 clock cycles to complete. The system determines the frame header position through the position of the maximum peak value, and then feeds back the frame header position for signal position adjustment. For signals with a sampling rate of 1.125sps, the synchronization position can be obtained through mathematical calculation. The fractional part of the synchronization position under the sampling rate of 1.125sps can be finely compensated by the frequency domain clock recovery mechanism.

[0134] The core of this process is to achieve accurate frame synchronization positioning through sliding cross-correlation and maximum value search, to ensure accurate detection of the signal synchronization point, and to provide a reliable timing reference for subsequent signal processing. According to the above process, a frame synchronization unit based on field programmable gate array can be built.

[0135] Corresponding to the above method, the embodiment of the application further provides an uplink burst mode passive optical network signal real-time transmission and processing system, which comprises a field programmable gate array, a photodetector and a high-speed digital-to-analog converter. The photodetector is used to receive each group of signals in the uplink burst mode passive optical network signal transmitted by a sending end in a continuous parallel mode, and directly detects each group of signals in real time to obtain each group of analog electrical signals. The high-speed digital-to-analog converter is used to convert each group of analog electrical signals into digital signals in real time. The field programmable gate array comprises a computer device, and the computer device comprises a processor and a memory. The memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the system implements the following steps of the uplink burst mode passive optical network signal real-time transmission and processing method.

[0136] The first overlap ratio is used to perform real-time overlap operation on each group of digital signals to obtain each group of digital signals after overlap.

[0137] Based on the first sequence in each group of digital signals after overlap, real-time frequency domain clock recovery is performed on each group of digital signals after overlap. Based on the third sequence in each group of digital signals after clock recovery, real-time frequency domain equalization is performed on each group of digital signals after clock recovery.

[0138] The first overlap ratio is used to perform real-time overlap removal operation on each group of digital signals after equalization in the time domain.

[0139] Based on the second sequence in each group of digital signals after overlap removal, the frame header position of each group of digital signals after overlap removal is determined to perform real-time frame synchronization on each group of digital signals after overlap removal, so as to obtain the recovered passive optical network signal.

[0140] In an embodiment, a specific example structure of the uplink burst mode passive optical network signal real-time transmission and processing system can be as shown in Figure 7 The uplink burst mode passive optical network signal generated by the uplink burst mode passive optical network signal generation unit of the sending end is transmitted to the uplink burst mode passive optical network signal recovery unit of the receiving end for real-time processing and recovery. The signal generation, processing and recovery process is as described in the uplink burst mode passive optical network signal real-time transmission and processing method in the foregoing embodiment, which will not be described herein.

[0141] Figure 8 For the clock error result graph using the initial phase estimation, as shown in Figure 8 The clock error converges stably, and fast convergence can be achieved between each frame of data.

[0142] Figure 9The mean square error result obtained using frequency domain equalization is shown in the image. Figure 9 As shown, the mean square error does not show a significant convergence process, indicating that the burst mode frequency domain equalization using the preamble sequence C converges very quickly.

[0143] Figure 10 The bit error rate distribution diagram of the bit XOR at the transmitting and receiving ends when the received optical power is -23dBm is shown below. Figure 10 As shown, the error distribution is uniform, indicating that the equalizer has a significant effect.

[0144] Figure 11 The diagram shows the received optical power-bit error rate performance of the signal transmitted through the transmitter of this invention after back-to-back and fiber optic channel transmission and recovery. Figure 11 As shown, after back-to-back and fiber optic channel transmission, the bit error rate can reach a forward error correction threshold of 20% when the received optical power is -27dBm. Therefore, compared to existing technologies, the method of this invention can realize a real-time transmission and processing system for passive optical network signals suitable for uplink burst mode in resource-constrained field-programmable gate arrays, and also achieves better signal recovery performance.

[0145] The following section conducts a transmission distance test on the signal transmitted by the sending end. The transmission distance for this test is 20 / 40 kilometers. (Combined with...) Figure 11 It can be demonstrated that the signals processed and transmitted by the transmitting end in this embodiment of the invention can achieve normal transmission in both optical back-to-back and fiber optic channels. Furthermore, using... Figure 2 The leader sequence structure can achieve fast convergence of burst modes. By using... Figures 3 to 5 The design enables the transmission, reception, and real-time processing of uplink burst-mode passive optical network signals on a field-programmable gate array (FPGA).

[0146] This invention discloses a method and system for real-time transmission and processing of uplink burst-mode passive optical network signals. The real-time digital signal processing of this uplink burst-mode passive optical network mainly includes burst-mode frequency domain timing recovery and burst-mode frequency domain equalization, achieving fast convergence based on a preamble sequence of approximately 42 ns. Simultaneously, improved implementations of Fast Fourier Transform and Decision-Guided Least Mean Square algorithm reduce digital signal processing resources by 28.57%, enabling real-time uplink burst-mode passive optical network processing within a field-programmable gate array (FPGA) with limited digital signal processing resources. This allows for the transmission and effective reception of optical modulation signals for intensity-modulated or directly detected optical communication systems, resulting in effective signal recovery. This invention achieves real-time digital signal processing in burst mode for 25 Gbit / s uplink reception, meeting the asymmetric mode requirements of 50 Gbit / s passive optical networks.

[0147] The embodiment of the present application also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the following steps of the real-time transmission and processing method of the upstream burst mode passive optical network signal.

[0148] The real-time overlap operation is performed on each group of digital signals with a first overlap ratio to obtain each group of overlapped digital signals; wherein each group of digital signals as input is obtained by directly detecting and analog-to-digital converting each group of signals in the received upstream burst mode passive optical network signal continuously and parallel transmitted by a sending end in real time, the passive optical network signal comprises a preamble sequence and a sequence carrying sending information, and the preamble sequence comprises a first sequence for frame detection and phase estimation, a second sequence for frame synchronization and a third sequence for channel estimation;

[0149] The real-time frequency domain clock recovery is performed on each group of overlapped digital signals based on the first sequence in each group of overlapped digital signals, and the real-time frequency domain equalization is performed on each group of clock recovered digital signals based on the third sequence in each group of clock recovered digital signals;

[0150] The real-time overlap removal operation is performed on each group of equalized digital signals in the time domain with the first overlap ratio;

[0151] The frame header position of each group of overlap removed digital signals is determined based on the second sequence in each group of overlap removed digital signals to perform real-time frame synchronization on each group of overlap removed digital signals, so that the recovered passive optical network signal is obtained. The computer readable storage medium can be a tangible storage medium, such as a random access memory (RAM), an internal memory, a read only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0152] The embodiment of the present application also provides a computer program product, which comprises computer instructions, and the computer instructions are executed by a processor to implement the following steps of the real-time transmission and processing method of the upstream burst mode passive optical network signal.

[0153] The real-time overlap operation is performed on each group of digital signals with a first overlap ratio to obtain each group of overlapped digital signals; wherein each group of digital signals as input is obtained by directly detecting and analog-to-digital converting each group of signals in the received upstream burst mode passive optical network signal continuously and parallel transmitted by a sending end in real time, the passive optical network signal comprises a preamble sequence and a sequence carrying sending information, and the preamble sequence comprises a first sequence for frame detection and phase estimation, a second sequence for frame synchronization and a third sequence for channel estimation;

[0154] The overlapped digital signals are subjected to real-time frequency domain clock recovery based on the first sequence in the overlapped digital signals, and the overlapped digital signals after clock recovery are subjected to real-time frequency domain equalization based on the third sequence in the overlapped digital signals after clock recovery;

[0155] The equalized digital signals are subjected to real-time de-overlapping in time domain with the first overlapping ratio;

[0156] The frame header position of the de-overlapped digital signals is determined based on the second sequence in the de-overlapped digital signals, so as to perform real-time frame synchronization on the de-overlapped digital signals, thereby obtaining the recovered passive optical network signal.

[0157] Those skilled in the art should understand that the exemplary components, systems and methods described in connection with the embodiments disclosed herein can be implemented in hardware, software or a combination thereof. The choice of hardware or software implementation is dependent on the particular application and design constraints imposed on the solution. Skilled persons can use different methods to implement the described functions for each particular application, but such implementation should not be considered beyond the scope of the present application. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the present application are program or code segments used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave in a transmission medium or communication link.

[0158] It should be noted that the present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted herein. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and skilled persons can make various changes, modifications and additions, or change the order of the steps, after understanding the spirit of the present application.

[0159] In the present application, the features described and / or exemplified for one embodiment can be used in the same way or in a similar way in one or more other embodiments, and / or in combination with or instead of the features of other embodiments.

[0160] The above description is only preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the embodiments of the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for real-time transmission and processing of uplink burst-mode passive optical network signals, characterized in that, The method includes: The passive optical network receives multiple sets of signals in the uplink burst mode of the continuously transmitted uplink signal from the transmitter, wherein each set of signals is transmitted in parallel. The passive optical network signal includes a preamble sequence and a sequence carrying transmission information. The preamble sequence includes a first sequence for frame detection and phase estimation, a second sequence for frame synchronization, and a third sequence for channel estimation. The signals are directly detected and converted from analog to digital in real time to obtain the digital signals. The digital signals of each group are overlapped in real time using the first overlap ratio to obtain the overlapped digital signals of each group. Real-time frequency domain clock recovery is performed on each group of overlapping digital signals based on the first sequence in each group of overlapping digital signals, and real-time frequency domain equalization is performed on each group of clock-recovered digital signals based on the third sequence in each group of clock-recovered digital signals. The first overlap ratio is used to perform real-time overlap removal operation on each group of equalized digital signals in the time domain. The frame header position of each group of digital signals after de-overlapping is determined based on the second sequence in each group of digital signals after de-overlapping, so as to perform real-time frame synchronization of each group of digital signals after de-overlapping, thereby obtaining the recovered passive optical network signal.

2. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1, characterized in that, The real-time frequency domain clock recovery of each group of overlapping digital signals based on the first sequence in each group of overlapping digital signals includes: By using the feedforward initial phase estimation module and a tree-structured search comparison algorithm, the frequency point with power peak in the first sequence of each group of overlapping digital signals is determined in the frequency domain to achieve frame detection. The feedforward initial phase estimation module performs feedforward initial sampling phase offset estimation in the frequency domain based on the first sequence in parallel, so as to feed back and compensate the phase of the corresponding group of digital signals after overlapping of the first sequence in the feedback loop module, wherein the frame detection and the output time of the initial sampling phase offset estimation are aligned. Through the feedback loop module, the overlapping digital signals that do not contain the first sequence are sampled and phase estimated, loop filtered, digitally controlled oscillation and phase compensation based on Godard in the frequency domain, so as to perform real-time frequency domain clock recovery for each overlapping digital signal.

3. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1, characterized in that, The real-time frequency domain equalization of each group of digital signals after clock recovery, based on the third sequence in each group of clock-recovered digital signals, includes: The feedforward minimum mean square error algorithm is used to estimate the channel coefficients of the digital signals in the frequency domain based on the third sequence in each group of digital signals after clock recovery and the corresponding group of digital signals after clock recovery containing the third sequence. A feedback decision-oriented least mean square algorithm based on interpolation fast Fourier transform is adopted to estimate the updated channel coefficients of the corresponding group of digital signals after clock recovery without a third sequence in the frequency domain, so as to perform real-time frequency domain equalization on each group of digital signals after clock recovery based on the channel coefficients and the updated channel coefficients.

4. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1, characterized in that, The step of determining the frame header position of each group of digital signals after de-overlapping based on the second sequence in each group of digital signals, in order to perform real-time frame synchronization of each group of digital signals after de-overlapping, includes: Reconstruct multiple sets of reconstructed digital signals by reconstructing every two consecutive sets of digital signals after removing overlap. Sliding cross-correlation is performed on the second sequence in each group of digital signals after removing overlap and the reconstructed signals to obtain multiple cross-correlation values. A binary tree search algorithm is then used to determine the position of the maximum peak value based on the multiple cross-correlation values, thereby determining the frame header position of each group of digital signals after removing overlap. Real-time frame synchronization is performed on each group of digital signals after removing overlap, based on the frame header position.

5. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1, characterized in that, The signals in the uplink burst mode passive optical network signal are generated in advance by the transmitter performing the following steps: The bit sequence to be transmitted is divided into multiple groups according to a preset parallelism to obtain multiple sets of sequences. The bit sequence to be transmitted includes a preamble sequence and a sequence carrying transmission information. The preamble sequence includes a sequence for frame detection and phase estimation, a sequence for frame synchronization, and a sequence for channel estimation. The sequences are overlapped using a second overlap ratio to obtain the overlapped sequences, wherein the second overlap ratio is the same as the first overlap ratio. The overlapping sequences are subjected to Fast Fourier Transform, resampling, filtering, and Inverse Fourier Transform to obtain the time-domain digital signals of each group. The overlap is removed from each group of time-domain digital signals using the second overlap ratio to obtain the overlap-removed groups of time-domain digital signals. The time-domain digital signals after removing overlap are converted from digital to analog and modulated to obtain the signals, thereby generating uplink burst mode passive optical network signals.

6. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1 or 5, characterized in that, The overlap operation includes overlapping the end of the previous group of data according to the overlap ratio for each group of data, wherein for the first group of data, the data in the overlap portion is 0.

7. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1, characterized in that, The first sequence has a length of 192, which consists of multiple sequences of 0 and 1 in the time domain and is represented by two frequency points at half baud rate in the frequency domain; the second sequence has a length of 96, which includes three sets of identical 32-symbol random sequences multiplied by coefficients 1, 1, and -1 respectively; the third sequence includes random symbols of length 768.

8. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1, characterized in that, After performing a real-time overlay operation on each group of digital signals at a first overlap ratio to obtain the overlaid digital signals, the method further includes: Fast Fourier Transform and matched filtering are performed on the overlapping digital signals to obtain the matched frequency domain digital signals.

9. The method for real-time transmission and processing of uplink burst mode passive optical network signals according to claim 1, characterized in that, After performing real-time frequency domain clock recovery on each group of overlapping digital signals based on the first sequence in each group of overlapping digital signals, the method further includes: After clock recovery, each group of digital signals is downsampled in the frequency domain to obtain each group of digital signals with 1x parallelism.

10. A real-time transmission and processing system for uplink burst mode passive optical network signals, characterized in that, The system includes a field-programmable gate array (FPGA), a photodetector, and a high-speed analog-to-digital converter (ADC). The photodetector receives multiple sets of signals from a continuously transmitted uplink burst-mode passive optical network (PON) signal. Each set of signals is transmitted in parallel. The PON signal includes a preamble sequence and a sequence carrying transmission information. The preamble sequence includes a first sequence for frame detection and phase estimation, a second sequence for frame synchronization, and a third sequence for channel estimation. Real-time direct detection of each set of signals yields each set of analog electrical signals. The high-speed ADC performs real-time analog-to-digital conversion on each set of analog electrical signals to obtain each set of digital signals. The FPGA includes a processor, a memory, and computer instructions stored in the memory. The processor executes the computer instructions. When the computer instructions are executed, the system performs the following steps: The digital signals of each group are overlapped in real time using the first overlap ratio to obtain the overlapped digital signals of each group. Real-time frequency domain clock recovery is performed on each group of overlapping digital signals based on the first sequence in each group of overlapping digital signals, and real-time frequency domain equalization is performed on each group of clock-recovered digital signals based on the third sequence in each group of clock-recovered digital signals. The first overlap ratio is used to perform real-time overlap removal operation on each group of equalized digital signals in the time domain. The frame header position of each group of digital signals after de-overlapping is determined based on the second sequence in each group of digital signals after de-overlapping, so as to perform real-time frame synchronization of each group of digital signals after de-overlapping, thereby obtaining the recovered passive optical network signal.

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