Radio frequency chip fan-out type packaging design method based on machine learning optimization

Abstract

The invention relates to the technical field of radio frequency processing, discloses a radio frequency chip fan-out packaging design method based on machine learning optimization, and aims at the design of high-speed packaged high-frequency pins. A high-frequency pin GSG structure design process is decoupled into a mapping problem of an RDL signal line length L, a signal line and ground line spacing S, a signal involute angle alpha and pin characteristic impedance, loss and return loss electrical performance. And by taking the solving process of the positive problem as a training environment, reversely solving a specific combination of GSG structure design size parameters meeting different design demand responses. Meanwhile, in the face of small-batch radio frequency chip product design of customized, small-crowd or technical exploration stage scenes with few products and various forms, a non-ergodic sample collection and later-stage small-amount adjustment mode is adopted, and the situation that ergodic simulation covers all parameter ranges to generate models and simulations in batches is avoided; and the earlier-stage investment time and computing power cost are higher than the small-batch production income.

Description

Technical Field

[0001] This invention relates to the field of radio frequency (RF) technology, and in particular to a fan-out packaging design method for RF chips based on machine learning optimization. Background Technology

[0002] With the increasing integration and operating frequency of electronic products, traditional RF chip packaging design faces numerous challenges in areas such as electromagnetic characteristic optimization, layout planning, cost, and design experience reuse. This is especially true in high-frequency applications, where the extremely high frequencies of the high-speed signal pins in the chip package mean that even minor structural changes can have a significant impact on electrical performance. Furthermore, the interactions between various modules in the package integration process become more complex. However, traditional iterative optimization design methods, which rely on manual experience, often require a great deal of work. Therefore, accelerating the optimization design process and automating it has become a problem that needs to be solved in the field of RF chip packaging.

[0003] like Figure 1 As shown, the high-frequency pin RDL (rerouting layer) of traditional RF chip fan-out package designs uses a GSG (ground-signal-ground) pin design, which is equivalent to a short coplanar waveguide. The existing design process involves deriving approximate geometric dimensions based on the structure and parameter relationships (geometric modeling parameters) of the coplanar waveguide, calculated values, and empirical values. The verification process involves manual parametric modeling, using simulation software with the FEM (finite element method) or MOM (moment of magnitude) matrix method to solve for electrical performance, and then iteratively optimizing the design through multiple simulations to finally obtain the corresponding geometric model that meets the desired electrical performance, such as Ro (characteristic impedance), S11 / S22 (return loss), S21 (insertion loss), etc.

[0004] Therefore, existing technologies typically rely on the designer's experience, complex calculation formulas, and repeated iterative optimization. The complexity of these formulas makes the design process unintuitive, and repeated iterative optimization requires significant human, material, and time resources. Existing methods, when dealing with complex systems, demand extremely high levels of expertise and experience from engineers, resulting in low design efficiency and a lack of transferability and reuse of design experience and methods. Furthermore, when designing small-batch RF chip products with limited quantity and diverse forms, in niche scenarios, or during the technology exploration phase, the initial time and computing power costs of using ergonomic simulation to cover the entire parameter range and generate models for simulation in batches may exceed the benefits of small-batch production. Summary of the Invention

[0005] This invention provides a fan-out packaging design method for radio frequency chips based on machine learning optimization, aiming to solve at least one of the above-mentioned technical problems.

[0006] To achieve the above objectives, this invention provides a machine learning-optimized fan-out package design method for radio frequency chips, the method comprising the following steps: Obtain several radio frequency chip packaging design tasks within a target time period; wherein, the radio frequency chip packaging design tasks include a set of critical size ranges and a set of electrical performance targets; The critical size range set is divided into parameter sampling points according to the initial parameter step size of each critical size range, and a parameter sample set is constructed for each RF chip package design task. The theoretical calculation time of the package size for each RF chip package design task is estimated. Based on the theoretical calculation time of the package size of each RF chip package design, several RF chip package design tasks are assigned to the corresponding RF chip package design terminals. An execution time table for the RF chip design tasks of each RF chip package design terminal is generated, which drives each designer to perform automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task according to the execution time table of the RF chip design tasks received by the configured RF chip package design terminal. The automatic simulation coarse localization includes machine learning model training based on automatic simulation of several key dimensions and key dimension range localization based on electrical performance target set; the manual simulation fine localization includes key dimension fine localization based on key dimension bisection method. The actual calculation time for the package size determined by each designer during automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task is statistically analyzed. Based on the actual calculation time of the package size and the execution time table of the RF chip design task, the initial parameter step size of the automatic simulation coarse positioning of the next RF chip package design task is updated to the real-time parameter step size, so as to adjust the actual calculation time of the package size of the next RF chip package design task.

[0007] Optionally, several RF chip package design task steps within the target time period may be obtained, specifically including: Receive the radio frequency chip packaging design requirements information uploaded by each task request terminal; wherein, the radio frequency chip packaging design requirements information includes a set of electrical performance targets and a first set of key size ranges with several key size ranges; Obtain information on the radio frequency chip packaging design capabilities of the packaging foundry; wherein, the radio frequency chip packaging design capability information includes a second set of key dimension ranges having several key dimension ranges; Based on the intersection of the first critical size range set and the corresponding critical size range in the second critical size range set, a critical size range set is determined. Using the critical size range set and the electrical performance target set, several radio frequency chip packaging design tasks are generated.

[0008] Optionally, the RF chip packaging design requirement information is configured as: several key dimension ranges entered by the task requester in the task request terminal based on several indicator parameters of the RF chip product manual, and the RF chip packaging design capability information is configured as: several key dimension ranges in the RDL process parameter table of the packaging foundry entered by the designer.

[0009] Optionally, the set of key dimensions includes: RDL signal line length L, signal line-to-ground distance S, and signal involute angle α; the set of electrical performance targets includes: characteristic impedance Ro, return loss S11 / S22, and insertion loss S21.

[0010] Optionally, the critical size range set is divided into parameter sampling points according to the initial parameter step size of each critical size range to construct the parameter sample set for each RF chip package design task, and the theoretical calculation time of the package size for each RF chip package design task is estimated, specifically including: The key size range set is divided into parameter sampling points according to the initial parameter step size of each key size range to obtain several size intervals for each key size range; wherein, the initial parameter step size is configured to be greater than the minimum parameter step size; Based on the combination of different size ranges for each critical size range, construct a parameter sample set of different size ranges for each RF chip package design task; Based on the different size range combinations of each parameter sample in the parameter sample set, determine the number of automatic simulation size combinations for each RF chip packaging design task, and determine the number of manual simulation size combinations based on the ratio of the initial parameter step size to the minimum parameter step size. Based on the historical automatic simulation time data and historical manual simulation time data recorded in the historical simulation database, the theoretical calculation time for the package size of each RF chip package design task is estimated.

[0011] Optionally, based on the theoretical calculation time of the package size for each RF chip package design, several RF chip package design tasks are assigned to corresponding RF chip package design terminals. An RF chip design task execution timetable is generated for each RF chip package design terminal. This drives each designer to perform automatic simulation coarse positioning and manual simulation fine positioning steps for each RF chip package design task according to the RF chip design task execution timetable received by the configured RF chip package design terminal. Specifically, this includes: Based on the theoretical calculation of the package size of each RF chip package design, several RF chip package design tasks are allocated to RF chip package design terminals to minimize the total number of allocated RF chip package design terminals and ensure that the execution completion time of the last RF chip package design task of each RF chip package design terminal is within the target time period. Based on the execution time allocated to each RF chip package design task in the corresponding RF chip package design terminal, generate an RF chip design task execution time table for each RF chip package design terminal; This drives each designer to sequentially perform automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task, based on the RF chip design task execution schedule received by the configured RF chip package design terminal.

[0012] Optionally, the automatic simulation coarse positioning specifically includes: Based on the parameter sample set of different size range combinations for each RF chip package design task, the simulation model corresponding to each size range combination is generated in batches. The script automatically submits all simulation models to the simulation software to obtain the electrical performance parameter set output by the simulation software. The size range combination and electrical performance parameters of each RF chip package design task are used to construct training samples. ReLU is used as the activation function to train the neural network model and obtain the trained inverse neural network machine learning model. The electrical performance target set in the RF chip packaging design task is input into the inverse neural network machine learning model to obtain the target critical size range for each critical size range.

[0013] Optional, precise positioning using artificial simulation, specifically including: The binary search method is used to perform software simulations sequentially for each minimum parameter step size combination in the target critical size range of each critical size range, and to determine whether the software simulation results of each time meet the electrical performance target set in the RF chip packaging design task. If so, after completing the precise positioning through artificial simulation, the target key dimensions corresponding to each key dimension range that meet the electrical performance target set in the RF chip packaging design task will be output as the design dimensions.

[0014] Optionally, based on the actual calculation time of the package size and the execution time table of the RF chip design task, the initial parameter step size of the automatic simulation coarse positioning of the next RF chip package design task is updated to the real-time parameter step size to adjust the actual calculation time step of the package size of the next RF chip package design task, specifically including: Based on the actual calculation time of the package size and the execution time table of the RF chip design task, determine whether the time difference between the actual completion time of the current RF chip package design task and the theoretical completion time in the execution time table of the RF chip design task exceeds the tolerance threshold. If so, the initial parameter step size for the automatic simulation coarse positioning of the next RF chip package design task is updated to the real-time parameter step size according to the preset rules, so as to adjust the actual calculation time of the package size of the next RF chip package design task.

[0015] Optionally, the preset rule is configured to: reduce the first parameter step size ratio of the next RF chip packaging design task by a preset adjustment ratio compared to the second parameter step size ratio of the current RF chip packaging design task; wherein, the first parameter step size ratio is configured as the ratio of the initial parameter step size of the next RF chip packaging design task performing automatic simulation coarse positioning to the minimum parameter step size, and the second parameter step size ratio is configured as the ratio of the initial parameter step size of the current RF chip packaging design task performing automatic simulation coarse positioning to the minimum parameter step size.

[0016] The beneficial effects of this invention are as follows: It proposes a machine learning-optimized fan-out package design method for RF chips. Specifically for the design of high-frequency pins in high-speed packages, it innovatively decouples the high-frequency pin GSG structure design process into three key structural dimension parameters: RDL signal line length L, signal line-to-ground distance S, and signal involute angle α, and their mapping to pin characteristic impedance, loss, and return loss electrical performance. By using the forward problem-solving process as a training environment, it solves the problem of finding specific combinations of GSG structure design dimension parameters that meet different design requirements when some responses (characteristic impedance, loss, etc.) are known. Furthermore, when designing small-batch RF chip products with limited quantity and diverse forms, niche scenarios, or technology exploration stages, it adopts a non-ergonomic sample acquisition and minor adjustments later. This approach balances design cost and efficiency, addressing the characteristics of customization and dispersion rather than large-scale design needs. It avoids the situation where ergonomic simulation covering the entire parameter range leads to batch model generation and simulation, resulting in upfront time and computing power costs exceeding the benefits of small-batch production. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the design of a traditional fan-out package for RF chips; Figure 2 This is a flowchart illustrating the fan-out packaging design method for radio frequency chips based on machine learning optimization according to an embodiment of the present invention. Figure 3 A simplified top view of the GSG pin diagram of a fan-out package for an RF chip, as shown in this embodiment of the invention. Figure 4 This is a schematic diagram of the structure of the radio frequency chip fan-out packaging design system based on machine learning optimization according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] This invention provides a machine learning-optimized fan-out package design method for radio frequency chips, referring to... Figure 2 , Figure 2 This is a flowchart illustrating the fan-out packaging design method for radio frequency chips based on machine learning optimization, as described in an embodiment of the present invention.

[0020] In this embodiment, a fan-out packaging design method for radio frequency chips based on machine learning optimization is described, the method comprising the following steps: S100: Obtain several RF chip packaging design tasks within the target time period; wherein, the RF chip packaging design tasks include a set of critical size ranges and a set of electrical performance targets; S200: Divide the critical size range set into parameter sampling points according to the initial parameter step size of each critical size range, construct the parameter sample set for each RF chip package design task, and estimate the theoretical calculation time of the package size for each RF chip package design task; S300: Based on the theoretical calculation time of the package size of each RF chip package design, several RF chip package design tasks are assigned to the corresponding RF chip package design terminals, generating an RF chip design task execution time table for each RF chip package design terminal, driving each designer to perform automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task according to the RF chip design task execution time table received by the configured RF chip package design terminal. The automatic simulation coarse localization includes machine learning model training based on automatic simulation of several key dimensions and key dimension range localization based on electrical performance target set; the manual simulation fine localization includes key dimension fine localization based on key dimension bisection method. S400: Statistics on the actual calculation time of the package size determined by each designer when performing automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task; S500: Based on the actual calculation time of the package size and the execution time table of the RF chip design task, update the initial parameter step size of the automatic simulation coarse positioning of the next RF chip package design task to the real-time parameter step size, so as to adjust the actual calculation time of the package size of the next RF chip package design task.

[0021] It should be noted that the high-frequency pin RDL (rerouting layer) of traditional RF chip fan-out package designs uses a GSG (ground-signal-ground) pin design, which is equivalent to a short coplanar waveguide. The existing design process involves deriving approximate geometric dimensions based on the structural and parameter relationships of the coplanar waveguide, calculation formulas, and experience. The verification process involves manual parametric modeling, multiple simulation iterations to optimize the design, and finally obtaining the corresponding geometric model that meets the desired electrical performance, such as Ro (characteristic impedance), S11 / S22 (return loss), S21 (insertion loss), etc. Therefore, existing technologies typically rely on the designer's experience, complex calculation formulas, and repeated iterative optimization. The complexity of the calculation formulas makes the design process unintuitive, and repeated iterative optimization requires significant human, material, and time resources. When dealing with complex systems, existing methods demand extremely high levels of professional knowledge and experience from engineers, resulting in low design efficiency and a lack of transfer and reuse of design experience and methods. Meanwhile, when designing small-batch RF chip products with a small number of customized products but diverse forms, or in niche scenarios or technology exploration stages, the time and computing power costs invested in the early stage may be higher than the benefits of small-batch production when using ergonomic simulation to cover the entire parameter range and generate models and simulate them in batches.

[0022] To address the aforementioned issues, this embodiment proposes a method for designing high-frequency pins in high-speed packages. It decouples the high-frequency pin GSG structure design process into a mapping problem involving the RDL signal line length L, the signal line-to-ground distance S, the signal involute angle α, and the pin's characteristic impedance, loss, and return loss performance. Using the solution process of the forward problem as a training environment, the specific combination of GSG structure design dimensions that meets different design requirements is solved in reverse. Furthermore, when designing small-batch RF chip products in customized, niche, or technology exploration phases with a limited number of products and diverse forms, a non-ergonomic sample acquisition and minor adjustments are adopted. This avoids the situation where ergonomic simulations cover the entire parameter range, leading to mass model generation and simulations, where the initial time and computing power costs exceed the benefits of small-batch production.

[0023] In a preferred embodiment, the steps for obtaining several RF chip packaging design tasks within a target time period specifically include: S110: Receive the RF chip packaging design requirement information uploaded by each task request terminal; wherein, the RF chip packaging design requirement information includes an electrical performance target set and a first critical size range set having several critical size ranges; S120: Obtain the RF chip packaging design capability information of the packaging foundry; wherein, the RF chip packaging design capability information includes a second critical size range set having several critical size ranges; S130: Based on the intersection of the first critical size range set and the corresponding critical size range in the second critical size range set, determine the critical size range set, and use the critical size range set and the electrical performance target set to generate several RF chip packaging design tasks.

[0024] Furthermore, the RF chip packaging design requirement information is configured as: several key dimension ranges entered by the task requester in the task request terminal based on several indicator parameters from the RF chip product manual, and the RF chip packaging design capability information is configured as: several key dimension ranges from the RDL process parameter table of the packaging foundry entered by the designer.

[0025] In practical applications, such as Figure 3 As shown, the set of key dimensions includes: RDL signal line length L, signal line-to-ground distance S, and signal involute angle α. The set of electrical performance targets includes: characteristic impedance Ro, return loss S11 / S22, and insertion loss S21.

[0026] In this embodiment, the key size range set for each key size range is determined by the intersection of two key size ranges: the RF chip packaging design requirement information and the RF chip packaging design capability information.

[0027] Specifically, information on RF chip packaging design capabilities is usually based on packaging processes (such as RDL fabrication, molding, and cutting processes for fan-out packaging) which impose hard limitations on dimensional parameters. Parameters that exceed these limits cannot be achieved in actual production, so it is necessary to define the boundaries based on process capabilities first.

[0028] (1) Process constraints on signal line length L: Minimum length limit: Affected by the die size and fan-out area layout. For example, the pin pitch of the die is usually 50-200μm. The RDL needs to extend from the die pins to the pads outside the package. The shortest length L cannot be less than the straight-line distance from the die edge to the package pad (otherwise routing is not possible). If the die size is 5mm×5mm and the package size is 10mm×10mm, the minimum possible value of L is about 0.5mm (the shortest path from the edge to the pad). Maximum length limit: Affected by RDL routing accuracy and signal delay. The RDL of the fan-out package is usually made using photolithography. Excessive line length will lead to the accumulation of routing errors (such as uneven line width and corner deviation), and the delay of high-frequency signals (such as millimeter waves) on long lines will degrade system timing. According to industry experience, the maximum length of L in high-frequency scenarios is usually no more than 2.0mm (after exceeding this, the delay and loss will increase significantly).

[0029] (2) Process constraints on the spacing S between signal lines and ground lines: Minimum spacing limit: determined by the resolution of the photolithography process. The line spacing (S) of the RDL needs to be greater than the minimum exposure accuracy of the photoresist, otherwise it will cause a short circuit between the signal line and the ground line. Currently, the minimum spacing of the RDL process for mainstream fan-out packaging is about 10μm (0.01mm), but considering the mass production yield (to avoid short circuits caused by edge burrs), the actual minimum S is usually 0.1mm (100μm). Maximum spacing limit: affected by package size and electromagnetic shielding requirements. When S is too large, the shielding effect of the ground line on the signal line is weakened (high-frequency signals are easily interfered with by external factors), and the overall package size will increase (which does not conform to the trend of miniaturization). For example, the package size of mobile phone RF modules is usually less than 10mm×10mm. If S exceeds 0.5mm, the total width of the two ground lines and one signal line will exceed 2mm (S×2+line width), occupying too much space. Therefore, the maximum value of S is usually set to 0.5mm.

[0030] (3) Process constraints of involute angle α: Minimum angle limit: Affected by the radius of curvature of the RDL corner. If the involute angle is too small (e.g., less than 30°), the signal line corner will be too steep, making it difficult to create a smooth corner in the photolithography process (e.g., the line width will be narrowed or the line will break at the corner), and high-frequency signals will experience impedance abrupt changes at sharp bends (increasing reflection). Maximum angle limit: Affected by the wiring space and signal path length. If α is too large (e.g., more than 120°), the "unfolding range" of the involute will be too large, occupying too much fan-out area space, and may even cross with other signal lines. At the same time, if α is too large, it will indirectly increase the actual length of the signal line (L will become longer), resulting in increased loss. Therefore, the maximum value of α is usually set to 120°.

[0031] Based on this, within the physical limits allowed by the process, it is necessary to further narrow down the parameter range according to the application scenario of the product (such as operating frequency, transmission rate, and anti-interference requirements) to ensure that the parameter combination can meet the core performance indicators.

[0032] (1) The impact of operating frequency on parameter range: High frequency scenarios (e.g., 77GHz millimeter-wave radar): The signal wavelength is extremely short (about 4mm), and small changes in L and S can cause drastic fluctuations in impedance and loss. Therefore, the parameter range needs to be narrowed to ensure stability. For example, L should be 0.5-1.5mm (to avoid excessive length leading to loss), and S should be 0.2-0.4mm (to balance shielding and impedance matching). Mid-to-low frequency scenarios (e.g., 5G Sub-6GHz): The signal wavelength is relatively long (about 50mm), and the impact of parameter changes on performance is relatively gradual. Therefore, the range can be appropriately widened. For example, L should be 0.5-2.0mm, and S should be 0.1-0.5mm.

[0033] (2) The impact of anti-interference requirements on S: If the application scenario has strong electromagnetic interference (such as the engine environment in automotive electronics), stronger ground shielding is required. Therefore, S should be smaller (such as 0.1-0.3mm) to make the ground line closer to the signal line. If it is a low interference environment (such as laboratory instruments), S can be increased appropriately (such as 0.3-0.5mm) to reduce the pressure on the package size.

[0034] (3) The effect of transmission rate on L: High-speed signals (such as above 10Gbps) are sensitive to delay, so L needs to be a smaller value (such as 0.5-1.0mm) to reduce transmission time; Low-speed signals (such as below 1Gbps) have low delay requirements, so L can be appropriately larger (such as 1.0-2.0mm) to simplify wiring.

[0035] Therefore, this embodiment can obtain the RDL process parameter table from the packaging foundry to clarify hard indicators such as minimum line length, maximum line length, minimum pitch, and minimum angle; and then determine indicators such as operating frequency, transmission rate, and upper limit of package size according to the product manual. Taking the process limit as the absolute boundary and the scenario requirements as the performance boundary, the intersection of the two is taken as the final range.

[0036] In a preferred embodiment, the critical size range set is divided into parameter sampling points according to the initial parameter step size of each critical size range, constructing a parameter sample set for each RF chip package design task, and estimating the theoretical calculation time of the package size for each RF chip package design task, specifically including: S210: Divide the key size range set into parameter sampling points according to the initial parameter step size of each key size range to obtain several size intervals for each key size range; wherein, the initial parameter step size is configured to be greater than the minimum parameter step size; S220: Based on the combination of different size ranges for each critical size range, construct a parameter sample set of different size ranges for each RF chip package design task; S230: Based on the different size range combinations of each parameter sample in the parameter sample set, determine the number of automatic simulation size combinations for each RF chip packaging design task; and based on the ratio of the initial parameter step size to the minimum parameter step size, determine the number of manual simulation size combinations. S240: Based on the historical automatic simulation time data and historical manual simulation time data recorded in the historical simulation database, estimate the theoretical calculation time for the package size of each RF chip package design task.

[0037] In this embodiment, the theoretical calculation time for the package size determined by different combinations of automatic and manual simulation sizes is estimated by using historical automatic simulation data and historical manual simulation data from the historical simulation database.

[0038] In a preferred embodiment, based on the theoretical calculation of the package size for each RF chip package design, several RF chip package design tasks are allocated to corresponding RF chip package design terminals. An execution timetable for each RF chip package design terminal is generated, driving each designer to perform automatic simulation coarse positioning and manual simulation fine positioning steps for each RF chip package design task according to the execution timetable received by the configured RF chip package design terminal. Specifically, this includes: S310: Based on the theoretical calculation of the package size of each RF chip package design, several RF chip package design tasks are allocated to RF chip package design terminals to minimize the total number of allocated RF chip package design terminals and ensure that the execution completion time of the last RF chip package design task of each RF chip package design terminal is within the target time period. S320: Generate an execution time table for each RF chip design task in the corresponding RF chip package design terminal, based on the execution time allocated to each RF chip package design task in the corresponding RF chip package design terminal. S330: Drives each designer to perform automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task in sequence, according to the RF chip design task execution schedule received by the configured RF chip package design terminal.

[0039] Furthermore, the automatic simulation coarse positioning specifically includes: S331: Based on the parameter sample set of different size range combinations for each RF chip package design task, generate simulation models corresponding to each size range combination in batches, and use scripts to automatically submit all simulation models to the simulation software to obtain the electrical performance parameter set output by the simulation software. S332: Combine the size range and electrical performance parameters of each RF chip package design task to construct training samples, use ReLU as the activation function to train the neural network model, and obtain the trained inverse neural network machine learning model. S333: Input the electrical performance target set in the RF chip packaging design task into the inverse neural network machine learning model to obtain the target critical size range for each critical size range.

[0040] In this embodiment, simulation software such as ANSYS HFSS can be used to estimate its performance and obtain the corresponding electromagnetic response curves. After integration processing, -10dB is used as the threshold for judging the values ​​of S11 / S22, and -1dB is used as the threshold for judging S21. The structural parameter combination matrix is ​​set as a (1×3) X matrix, and the response parameter matrix is ​​set as a (3×1) Y matrix. Several sets of valid structural parameter-response curve data are obtained. These data are used as a sample training set to train a reverse inversion neural network machine learning model. ReLU is used as the activation function. After training, it can accept actual electromagnetic response curves as input and reverse deduce the structural parameter range that produces this characteristic.

[0041] Furthermore, precise positioning through artificial simulation specifically includes: S334: Use the binary search method to perform software simulation sequentially on each minimum parameter step size combination in the target critical size range for each critical size range, and determine whether the software simulation results of each time meet the electrical performance target set in the RF chip packaging design task. S335: If so, complete the precise positioning of the artificial simulation and output the target key dimensions of each key dimension range that meet the electrical performance target set in the RF chip packaging design task as the design dimensions.

[0042] In this embodiment, when designing small-batch RF chip products with a small number of customized products in diverse forms, niche scenarios, or technology exploration stages, a non-ergonomic sample collection and minor adjustments are adopted. This approach balances design costs and efficiency when targeting customized and decentralized characteristics rather than large-scale design needs. It avoids the situation where the time and computing power costs invested in the early stage exceed the benefits of small-batch production, which would otherwise be due to using ergonomic simulation to cover the entire parameter range and generate models in batches for simulation.

[0043] In a preferred embodiment, based on the actual calculation time of the package size and the execution time table of the RF chip design task, the initial parameter step size for the automatic simulation coarse positioning of the next RF chip package design task is updated to the real-time parameter step size to adjust the actual calculation time of the package size for the next RF chip package design task, specifically including: S510: Based on the actual calculation time of the package size and the execution time table of the RF chip design task, determine whether the time difference between the actual completion time of the current RF chip package design task and the theoretical completion time in the RF chip design task execution time table exceeds the tolerance threshold. S520: If so, update the initial parameter step size of the automatic simulation coarse positioning of the next RF chip package design task to the real-time parameter step size according to the preset rules, so as to adjust the actual calculation time of the package size of the next RF chip package design task.

[0044] Based on this, the preset rule is configured to: reduce the first parameter step size ratio of the next RF chip packaging design task by a preset adjustment ratio compared to the second parameter step size ratio of the current RF chip packaging design task; wherein, the first parameter step size ratio is configured as the ratio of the initial parameter step size of the next RF chip packaging design task performing automatic simulation coarse positioning relative to the minimum parameter step size, and the second parameter step size ratio is configured as the ratio of the initial parameter step size of the current RF chip packaging design task performing automatic simulation coarse positioning relative to the minimum parameter step size.

[0045] In this embodiment, if the completion time of the current RF chip packaging design task is detected to exceed the tolerance threshold of the theoretical completion time in the RF chip design task execution time table, the initial parameter step size of the next chip packaging design task needs to be reduced. By reducing the initial parameter step size, the number of critical size intervals within each critical size range is increased. When using this as a sample for training, a critical size design result with higher inversion accuracy can be obtained. When using this critical size design result for subsequent manual simulation and fine positioning, the fine positioning time can be greatly reduced. The time consumed by the current RF chip packaging design task can be compensated with as little computing power consumption as possible (the computing power consumption will increase exponentially as the number of critical size intervals increases).

[0046] Reference Figure 4 , Figure 4 This is a schematic diagram of the structure of the radio frequency chip fan-out packaging design system based on machine learning optimization according to an embodiment of the present invention.

[0047] like Figure 4 As shown, the RF chip fan-out packaging design system based on machine learning optimization proposed in this embodiment of the invention includes: The task acquisition module 10 is used to acquire several radio frequency chip packaging design tasks within a target time period; wherein, the radio frequency chip packaging design tasks include a set of critical size ranges and a set of electrical performance targets; The time estimation module 20 is used to divide the critical size range set into parameter sampling points according to the initial parameter step size of each critical size range, construct the parameter sample set of each RF chip package design task, and estimate the theoretical calculation time of the package size of each RF chip package design task. The size positioning module 30 is used to calculate the time consumption based on the theoretical package size of each RF chip package design, allocate several RF chip package design tasks to the corresponding RF chip package design terminals, generate an RF chip design task execution time table for each RF chip package design terminal, and drive each designer to perform automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task according to the RF chip design task execution time table received by the configured RF chip package design terminal. The automatic simulation coarse localization includes machine learning model training based on automatic simulation of several key dimensions and key dimension range localization based on electrical performance target set; the manual simulation fine localization includes key dimension fine localization based on key dimension bisection method. The time consumption statistics module 40 is used to calculate the actual calculation time of the package size determined by each designer when performing automatic simulation coarse positioning and manual simulation fine positioning for each RF chip package design task. The step size update module 50 is used to update the initial parameter step size of the automatic simulation coarse positioning of the next RF chip package design task to the real-time parameter step size based on the actual calculation time of the package size and the execution time table of the RF chip design task, so as to adjust the actual calculation time of the package size of the next RF chip package design task.

[0048] Other embodiments or specific implementations of the machine learning-optimized RF chip fan-out packaging design system of the present invention can be found in the above-described method embodiments, and will not be repeated here.

[0049] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for radio frequency chip fan-out package design based on machine learning optimization, characterized in that, The method comprises the following steps: Obtaining a plurality of radio frequency chip packaging design tasks within a target period; wherein the radio frequency chip packaging design task comprises a critical dimension range set and an electrical performance target set; According to the initial parameter step length of each critical dimension range, the parameter sampling point of the critical dimension range set is divided, the parameter sample set of each radio frequency chip packaging design task is constructed, and the packaging size theoretical calculation time of each radio frequency chip packaging design task is estimated; Based on the packaging size theoretical calculation time of each radio frequency chip packaging design, the plurality of radio frequency chip packaging design tasks are distributed to the corresponding radio frequency chip packaging design terminal, the radio frequency chip design task execution time period table of each radio frequency chip packaging design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and artificial simulation fine positioning of each radio frequency chip packaging design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip packaging design terminal; Wherein, the automatic simulation coarse positioning includes machine learning model training based on a plurality of critical dimensions automatic simulation and critical dimension range positioning based on the electrical performance target set, and the artificial simulation fine positioning includes critical dimension fine positioning based on critical dimension dichotomy; Statistical analysis of the packaging size actual calculation time determined by each designer when executing the automatic simulation coarse positioning and artificial simulation fine positioning of each radio frequency chip packaging design task; Based on the packaging size actual calculation time and the radio frequency chip design task execution time period table, the initial parameter step length of the next radio frequency chip packaging design task execution automatic simulation coarse positioning is updated to the real-time parameter step length, so as to adjust the packaging size actual calculation time of the next radio frequency chip packaging design task.

2. The machine learning optimization based radio frequency chip fan-out package design method of claim 1, wherein, The step of obtaining a plurality of radio frequency chip packaging design tasks within a target period comprises: Receiving the radio frequency chip packaging design requirement information uploaded by each task request terminal; wherein the radio frequency chip packaging design requirement information contains an electrical performance target set and a first critical dimension range set with a plurality of critical dimension ranges; Obtaining the radio frequency chip packaging design capability information of the packaging foundry; wherein the radio frequency chip packaging design capability information includes a second critical dimension range set with a plurality of critical dimension ranges; Based on the intersection of corresponding critical dimension ranges in the first critical dimension range set and the second critical dimension range set, the critical dimension range set is determined, and the critical dimension range set and the electrical performance target set are used to generate a plurality of radio frequency chip packaging design tasks.

3. The machine learning optimization based radio frequency chip fan-out package design method of claim 2, wherein, The radio frequency chip packaging design requirement information is configured as a plurality of critical dimension ranges entered by the task requester based on a plurality of index parameters in the radio frequency chip product manual on the task request terminal, and the radio frequency chip packaging design capability information is configured as a plurality of critical dimension ranges in the RDL process parameter table of the packaging foundry entered by the designer.

4. The machine learning optimization based radio frequency chip fan-out package design method of claim 3, wherein, The critical dimension range set includes RDL signal line length L, signal line and ground line spacing S, and signal involute angle α, and the electrical performance target set includes characteristic impedance Ro, return loss S11 / S22 and insertion loss S21.

5. The machine learning optimization based radio frequency chip fan-out package design method of claim 1, wherein, According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes:

6. The machine learning optimization based radio frequency chip fan-out package design method of claim 5, wherein, Based on the package size theoretical calculation time consumption of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to corresponding radio frequency chip package design terminals, a radio frequency chip design task execution time period table of each radio frequency chip package design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and manual simulation fine positioning steps of each radio frequency chip package design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip package design terminal, which specifically includes: Based on the package size theoretical calculation time consumption of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to corresponding radio frequency chip package design terminals, a radio frequency chip design task execution time period table of each radio frequency chip package design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and manual simulation fine positioning steps of each radio frequency chip package design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip package design terminal, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes:

7. The machine learning optimization based radio frequency chip fan-out package design method of claim 6, wherein, The automatic simulation coarse positioning specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: The size interval combination and the electrical performance parameter of each radio frequency chip package design task are constructed as training samples, a RELU is used as an activation function to train a neural network model, and a trained inverse inversion neural network machine learning model is obtained. The electrical performance target set in the radio frequency chip package design task is input into the inverse inversion neural network machine learning model to obtain a target critical dimension interval for each critical dimension range.

8. The machine learning optimization based radio frequency chip fan-out package design method of claim 7, wherein, The artificial simulation fine positioning specifically includes: The bisection method is used to perform software simulation on each minimum parameter step combination in the target critical dimension interval of each critical dimension range in sequence, and it is judged whether the software simulation result each time meets the electrical performance target set in the radio frequency chip package design task. If yes, the artificial simulation fine positioning is completed, and each target critical dimension of each critical dimension range corresponding to the electrical performance target set in the radio frequency chip package design task is output as a design size.

9. The machine learning optimization based radio frequency chip fan-out package design method of claim 1, wherein, Based on the package size actual calculation time consumption and the radio frequency chip design task execution time period table, the initial parameter step of the next radio frequency chip package design task execution automatic simulation coarse positioning is updated to a real-time parameter step to adjust the package size actual calculation time consumption step of the next radio frequency chip package design task, specifically including: Based on the package size actual calculation time consumption and the radio frequency chip design task execution time period table, it is judged whether the actual completion time of the current radio frequency chip package design task exceeds the tolerance threshold compared with the theoretical completion time in the radio frequency chip design task execution time period table. If yes, the initial parameter step of the next radio frequency chip package design task execution automatic simulation coarse positioning is updated to a real-time parameter step according to a preset rule to adjust the package size actual calculation time consumption of the next radio frequency chip package design task.

10. The machine learning optimization based radio frequency chip fan-out package design method of claim 9, wherein, The preset rule is configured to reduce the first parameter step ratio of the next radio frequency chip package design task compared with the second parameter step ratio of the current radio frequency chip package design task by a preset adjustment ratio, wherein the first parameter step ratio is configured as the ratio of the initial parameter step of the next radio frequency chip package design task execution automatic simulation coarse positioning to the minimum parameter step, and the second parameter step ratio is configured as the ratio of the initial parameter step of the current radio frequency chip package design task execution automatic simulation coarse positioning to the minimum parameter step.

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