A radio frequency chip fan-out package design method based on machine learning optimization

Abstract

The application relates to the technical field of radio frequency processing, and discloses a radio frequency chip fan-out type packaging design method based on machine learning optimization, aiming at the design of high-frequency pins of high-speed packaging, the high-frequency pin GSG structure design process is decoupled into the mapping problem of the RDL signal line length L, the signal line and ground line spacing S, the signal involute angle alpha and the pin characteristic impedance, loss and return loss electrical performance. With the solving process of the positive problem as the training environment, the GSG structure design size parameter specific combination meeting the response of different design requirements is reversely solved. Meanwhile, in the case of small-batch radio frequency chip product design in the customization, small group or technical exploration stage scene facing the product quantity is small and the form is various, the non-iterative sample collection and the later small amount of adjustment are adopted, the situation that the time and the algorithm cost of the early investment are higher than the small batch production benefits caused by the batch generation model and simulation caused by the traversal simulation covering all parameter ranges are avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency technology, and in particular to a radio frequency chip fan-out package design method based on machine learning optimization. BACKGROUND

[0002] With the increasing integration and operating frequency of electronic products, traditional radio frequency chip package design faces many challenges in electromagnetic characteristic optimization, layout planning, cost, design experience reuse, etc. Especially in high frequency applications, due to the extremely high signal frequency of high-speed signal pins of the chip package, even a slight structural change will have a huge impact on the electrical performance results. In addition, the interaction between each module in the package integration also becomes complex. However, the traditional iterative optimization design method relying on human experience often requires a lot of work. How to accelerate the optimization design process and realize process automation has become a problem to be solved in the field of radio frequency chip package design.

[0003] As shown in Figure 1 , the high-frequency pin RDL (redistribution layer) of the traditional radio frequency chip fan-out package design adopts GSG (ground-signal-ground) pin design, which is equivalent to a short coplanar waveguide. The design process of the prior art includes deriving the approximate geometric structure size parameters according to the structure and parameter relationship (geometric modeling parameters) of the coplanar waveguide, the calculated value and the empirical value. The verification process is to manually parameterize the model, use FEM finite element method or MOM matrix method to solve the electrical performance by using simulation software, and then iteratively optimize the design through multiple simulations to finally obtain the corresponding geometric model that meets the expected electrical performance such as Ro (characteristic impedance), S11 / S22 (return loss), S21 (insertion loss), etc.

[0004] Therefore, the prior art usually relies on the experience of the designer, complex calculation formulas and repeated iterative optimization. Due to the complexity of the calculation formula relationship, the design process is not intuitive, and repeated iterative optimization requires a lot of manpower, material and time costs. The prior art method requires high professional knowledge and experience of engineers when dealing with complex systems, and the design efficiency is not high, lacking of design experience and method migration and reuse. At the same time, when facing customized demand, small batch radio frequency chip product design in the face of small quantity and multiple forms, the traversal simulation covering all parameter ranges and batch generation of models and simulation, the time and computing power cost of the initial investment may be higher than the small batch production benefit. SUMMARY

[0005] The present application provides a radio frequency chip fan-out package design method based on machine learning optimization, which aims to solve at least one of the above technical problems.

[0006] To achieve the above object, the application provides a radio frequency chip fan-out package design method based on machine learning optimization, which comprises the following steps:

[0007] Obtain a plurality of radio frequency chip package design tasks in a target period; wherein the radio frequency chip package design task comprises a critical dimension range set and an electrical performance target set;

[0008] According to the initial parameter step length of each critical dimension range, the parameter sampling point of the critical dimension range set is divided, and the parameter sample set of each radio frequency chip package design task is constructed, and the theoretical calculation time of the package size of each radio frequency chip package design task is estimated;

[0009] Based on the theoretical calculation time of the package size of each radio frequency chip package design, the plurality of radio frequency chip package design tasks are distributed to the corresponding radio frequency chip package design terminal, the radio frequency chip design task execution period table of each radio frequency chip package design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and artificial simulation fine positioning of each radio frequency chip package design task according to the radio frequency chip design task execution period table received by the configured radio frequency chip package design terminal;

[0010] Wherein, the automatic simulation coarse positioning includes machine learning model training based on a plurality of critical dimension automatic simulations and critical dimension range positioning based on the electrical performance target set, and the artificial simulation fine positioning includes critical dimension fine positioning based on critical dimension dichotomy;

[0011] The actual calculation time of the package size of each designer in executing the automatic simulation coarse positioning and artificial simulation fine positioning of each radio frequency chip package design task is counted;

[0012] Based on the actual calculation time of the package size and the radio frequency chip design task execution period table, the initial parameter step length of the next radio frequency chip package design task execution automatic simulation coarse positioning is updated to the real-time parameter step length, so as to adjust the actual calculation time of the package size of the next radio frequency chip package design task.

[0013] Optionally, the step of obtaining a plurality of radio frequency chip package design tasks in a target period comprises:

[0014] Receiving the radio frequency chip package design requirement information uploaded by each task request terminal; wherein the radio frequency chip package design requirement information contains the electrical performance target set and the first critical dimension range set with a plurality of critical dimension ranges;

[0015] Obtain the radio frequency chip package design capability information of the package foundry; wherein the radio frequency chip package design capability information comprises a second critical dimension range set with a plurality of critical dimension ranges;

[0016] determining a set of critical dimension ranges based on intersections of corresponding critical dimension ranges in the first set of critical dimension ranges and the second set of critical dimension ranges, and generating a plurality of radio frequency chip package design tasks using the set of critical dimension ranges and the set of electrical performance targets.

[0017] Optionally, the radio frequency chip package design requirement information is configured as a plurality of critical dimension ranges entered by a task requester based on a plurality of index parameters in a radio frequency chip product manual, and the radio frequency chip package design capability information is configured as a plurality of critical dimension ranges in a RDL process parameter table of a package foundry entered by a designer.

[0018] Optionally, the set of critical dimension ranges includes a RDL signal line length L, a signal line and ground line spacing S, and a signal involute angle a, and the set of electrical performance targets includes a characteristic impedance Ro, a return loss S11 / S22, and an insertion loss S21.

[0019] Optionally, the set of critical dimension ranges is parameter-sampling-point-divided according to an initial parameter step length of each critical dimension range, a parameter sample set of each radio frequency chip package design task is constructed, and a package size theoretical calculation time consumption step of each radio frequency chip package design task is estimated, and the step specifically includes:

[0020] The set of critical dimension ranges is parameter-sampling-point-divided according to an initial parameter step length of each critical dimension range, and a plurality of size intervals of each critical dimension range are obtained; wherein the initial parameter step length is configured to be greater than a minimum parameter step length;

[0021] A parameter sample set combined by different size intervals in each radio frequency chip package design task is constructed based on combinations of different size intervals of each critical dimension range;

[0022] An automatic simulation size combination number of each radio frequency chip package design task is determined according to different size interval combinations of each parameter sample in the parameter sample set, and a manual simulation size combination number is determined according to a ratio of the initial parameter step length and the minimum parameter step length;

[0023] A package size theoretical calculation time consumption of each radio frequency chip package design task is estimated according to historical automatic simulation time consumption data and historical manual simulation time consumption data recorded in a historical simulation database.

[0024] Optionally, based on the theoretical calculation time of the package size of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to corresponding radio frequency chip package design terminals, a radio frequency chip design task execution time period table of each radio frequency chip package design terminal is generated, and each designer is driven to perform the automatic simulation coarse positioning and manual simulation fine positioning steps of each radio frequency chip package design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip package design terminal, specifically including:

[0025] Based on the theoretical calculation time of the package size of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to radio frequency chip package design terminals, so that the total number of allocated radio frequency chip package design terminals is minimized and the execution completion time of the last radio frequency chip package design task of each radio frequency chip package design terminal is within the target period;

[0026] According to the execution time period of each radio frequency chip package design task allocated to the corresponding radio frequency chip package design terminal, a radio frequency chip design task execution time period table of each radio frequency chip package design terminal is generated;

[0027] Each designer is driven to perform the automatic simulation coarse positioning and manual simulation fine positioning of each radio frequency chip package design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip package design terminal.

[0028] Optionally, the automatic simulation coarse positioning specifically includes:

[0029] According to the parameter sample set combined by different size intervals of each radio frequency chip package design task, the simulation model corresponding to each size interval combination is batch generated, all simulation models are automatically submitted to the simulation software by using scripts, and the electrical performance parameter set output by the simulation software is obtained;

[0030] The size interval combination and the electrical performance parameter of each radio frequency chip package design task are constructed as training samples, and the RELU is used as the activation function to train the neural network model to obtain the trained inverse inversion neural network machine learning model;

[0031] The electrical performance target set in the radio frequency chip package design task is input into the inverse inversion neural network machine learning model, and the target key size interval of each key size range is obtained.

[0032] Optionally, the manual simulation fine positioning specifically includes:

[0033] Each minimum parameter step combination in the target key size interval of each key size range is sequentially simulated by using the dichotomy method, and it is judged whether the software simulation result of each time meets the electrical performance target set in the radio frequency chip package design task.

[0034] If yes, the manual simulation fine positioning is completed, and a target critical dimension of each critical dimension range corresponding to the set of electrical performance targets in the radio frequency chip package design task is output as a design dimension.

[0035] Optionally, based on the package size actual calculation time consumption and the radio frequency chip design task execution time period table, an initial parameter step length of automatic simulation coarse positioning of a next radio frequency chip package design task is updated to a real-time parameter step length to adjust the package size actual calculation time consumption step of the next radio frequency chip package design task, and the method specifically comprises the following steps.

[0036] Based on the package size actual calculation time consumption and the radio frequency chip design task execution time period table, it is judged whether the completion time exceeding length of the actual completion time of the current radio frequency chip package design task compared to the theoretical completion time in the radio frequency chip design task execution time period table exceeds a tolerance threshold value.

[0037] If yes, the initial parameter step length of automatic simulation coarse positioning of a next radio frequency chip package design task is updated to a real-time parameter step length according to a preset rule to adjust the package size actual calculation time consumption of the next radio frequency chip package design task.

[0038] Optionally, the preset rule is configured to reduce a first parameter step length ratio of the next radio frequency chip package design task compared to a second parameter step length ratio of the current radio frequency chip package design task by a preset adjustment ratio, wherein the first parameter step length ratio is configured as a ratio of the initial parameter step length of automatic simulation coarse positioning of the next radio frequency chip package design task to the minimum parameter step length, and the second parameter step length ratio is configured as a ratio of the initial parameter step length of automatic simulation coarse positioning of the current radio frequency chip package design task to the minimum parameter step length.

[0039] The beneficial effects of the present application are that a radio frequency chip fan-out packaging design method based on machine learning optimization is proposed, and for the design of high-frequency pins of high-speed packaging, the high-frequency pin GSG structure design process is innovatively decoupled into three key structure size parameters: RDL signal line length L, signal line and ground line spacing S, signal involute angle a and the mapping problem of pin characteristic impedance, loss and return loss electrical performance. With the solving process of the positive problem as the training environment, the problem of reverse solving to meet the specific combination of GSG structure design size parameters in response to different design requirements is solved under the condition that part of the response (characteristic impedance, loss, etc.) is known. At the same time, when facing the customized demand of small quantity and various forms, the small-batch radio frequency chip product design in the niche scene or the technical exploration stage, using the non-exhaustive sample collection and the way of a small amount of adjustment in the later stage, for the customized and dispersed characteristics rather than the demand of scale design, it can balance the design cost and efficiency, avoid the situation that the time and computing power cost of the early investment is higher than the small-batch production benefit caused by the exhaustive simulation covering all parameter ranges and generating models in batches. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A flowchart of a traditional radio frequency chip fan-out packaging design;

[0041] Figure 2 A flowchart of a radio frequency chip fan-out packaging design method based on machine learning optimization of the embodiment of the present application;

[0042] Figure 3 A schematic diagram of a radio frequency chip fan-out packaging GSG pin of the embodiment of the present application is shown in a top view;

[0043] Figure 4 A structure diagram of a radio frequency chip fan-out packaging design system based on machine learning optimization of the embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0045] The embodiment of the present application provides a radio frequency chip fan-out packaging design method based on machine learning optimization, which is described with reference to Figure 2 , Figure 2 A flowchart of a radio frequency chip fan-out packaging design method based on machine learning optimization of the embodiment of the present application.

[0046] In this embodiment, a radio frequency chip fan-out packaging design method based on machine learning optimization, the method comprises the following steps:

[0047] S100: Obtain a plurality of radio frequency chip package design tasks within a target period; wherein the radio frequency chip package design task includes a set of critical dimension ranges and a set of electrical performance targets;

[0048] S200: According to the initial parameter step length of each critical dimension range, the parameter sampling point of the set of critical dimension ranges is divided, the parameter sample set of each radio frequency chip package design task is constructed, and the theoretical calculation time of the package size of each radio frequency chip package design task is estimated;

[0049] S300: Based on the theoretical calculation time of the package size of each radio frequency chip package design, the plurality of radio frequency chip package design tasks are distributed to the corresponding radio frequency chip package design terminal, the radio frequency chip design task execution period table of each radio frequency chip package design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and manual simulation fine positioning of each radio frequency chip package design task according to the radio frequency chip design task execution period table received by the configured radio frequency chip package design terminal;

[0050] Wherein, the automatic simulation coarse positioning includes machine learning model training based on a plurality of critical dimension automatic simulations and critical dimension range positioning based on the set of electrical performance targets, and the manual simulation fine positioning includes critical dimension fine positioning based on critical dimension dichotomy;

[0051] S400: Statistics of the actual calculation time of the package size determined by each designer when executing the automatic simulation coarse positioning and manual simulation fine positioning of each radio frequency chip package design task;

[0052] S500: Based on the actual calculation time of the package size and the radio frequency chip design task execution period table, the initial parameter step length of the next radio frequency chip package design task execution automatic simulation coarse positioning is updated to the real-time parameter step length, so as to adjust the actual calculation time of the package size of the next radio frequency chip package design task.

[0053] It should be noted that the high-frequency pin RDL (redistribution layer) of the conventional radio frequency chip fan-out package design adopts the GSG (ground-signal-ground) pin design, which is equivalent to a short coplanar waveguide. The design process of the prior art includes obtaining the approximate geometric structure size parameters according to the structure and parameter relationship, calculation formula and experience of the coplanar waveguide. The verification process is to obtain the geometric model corresponding to the expected electrical performance such as Ro (characteristic impedance), S11 / S22 (return loss), S21 (insertion loss) and the like through manual parameterized modeling, multiple simulation iteration optimization design. Therefore, the prior art usually relies on the experience of the designer, complex calculation formula and repeated iteration optimization. Due to the complexity of the calculation formula relationship, the design process is not intuitive, and the repeated iteration optimization requires a large amount of human and material costs and time cost. The prior art method requires high professional knowledge and experience of engineers when dealing with complex systems, and the design efficiency is not high, and the design experience and method are lack of migration and reuse. At the same time, when facing the design of small-batch radio frequency chip products in the stage of product customization, small number of scenes or technical exploration, the use of exhaustive simulation to cover all parameter ranges to generate models and simulate in batches may result in a situation where the time and computing power costs of the early investment are higher than the small-batch production benefits.

[0054] To solve the above problems, the embodiment proposes to decouple the high-frequency pin GSG structure design process into the mapping problem of RDL signal line length L, signal line and ground line spacing S, signal involute angle a and pin characteristic impedance, loss, return loss electrical performance for the design of high-frequency pins of high-speed packaging. With the solving process of the positive problem as the training environment, the specific combination of GSG structure design size parameters that meet the response of different design requirements is solved in reverse. At the same time, when facing the design of small-batch radio frequency chip products in the stage of product customization, small number of scenes or technical exploration, the use of non-exhaustive sample collection and late small amount of adjustment method can avoid the situation that the time and computing power costs of the early investment are higher than the small-batch production benefits caused by the use of exhaustive simulation to cover all parameter ranges to generate models and simulate in batches.

[0055] In a preferred embodiment, the steps of obtaining a plurality of radio frequency chip package design tasks in a target period include:

[0056] S110: receiving radio frequency chip package design requirement information uploaded by each task request terminal; wherein the radio frequency chip package design requirement information includes an electrical performance target set and a first key size range set with a plurality of key size ranges;

[0057] S120: obtaining radio frequency chip package design capability information of a packaging foundry; wherein the radio frequency chip package design capability information includes a second key size range set with a plurality of key size ranges;

[0058] S130: determining a set of critical dimension ranges based on the intersection of corresponding critical dimension ranges in the first set of critical dimension ranges and the second set of critical dimension ranges, and generating a plurality of radio frequency chip package design tasks using the set of critical dimension ranges and the set of electrical performance targets.

[0059] Further, the radio frequency chip package design requirement information is configured as a plurality of critical dimension ranges entered by a task requester based on a plurality of index parameters in a radio frequency chip product manual, and the radio frequency chip package design capability information is configured as a plurality of critical dimension ranges in a RDL process parameter table entered by a designer.

[0060] In actual application, as shown in the figure, Figure 3 The set of critical dimension ranges includes RDL signal line length L, signal line and ground line spacing S, and signal involute angle a, and the set of electrical performance targets includes characteristic impedance Ro, return loss S11 / S22, and insertion loss S21.

[0061] In this embodiment, the set of critical dimension ranges of each critical dimension range is determined by the intersection of the two critical dimension ranges of the radio frequency chip package design requirement information and the radio frequency chip package design capability information.

[0062] Specifically, the radio frequency chip package design capability information usually has hard restrictions on size parameters based on packaging processes (such as RDL manufacturing, plastic packaging, cutting, etc. of fan-out packaging), and parameters exceeding the range cannot be realized in actual production, so the boundary needs to be determined according to the process capability.

[0063] (1) Process constraint of signal line length L: minimum length limit: affected by chip die size and fan-out area layout. For example, the pin pitch of the chip die is usually 50-200 μm, and the RDL needs to extend from the die pin to the pad outside the package, and the minimum length L cannot be less than the "straight-line distance from the edge of the die to the pad of the package" (otherwise it cannot be wired). If the die size is 5 mm x 5 mm and the package size is 10 mm x 10 mm, the minimum possible value of L is about 0.5 mm (the shortest path from the edge to the pad). Maximum length limit: affected by RDL wiring accuracy and signal delay. The RDL of fan-out packaging is usually made by photolithography process, and long line length will cause wiring error accumulation (such as uneven line width, corner deviation), and high-frequency signals (such as millimeter waves) will worsen the system timing on long lines. According to industry experience, the maximum length of L in high-frequency scenarios is usually not more than 2.0 mm (delay and loss will increase significantly after exceeding).

[0064] (2) Process constraints of the signal line and ground line spacing S: Minimum spacing limit: determined by the resolution of the lithography process. The line spacing (S) of the RDL needs to be greater than the minimum exposure accuracy of the photoresist, otherwise it will cause short circuit between the signal line and the ground line. The minimum spacing of the current mainstream fan-out package RDL process is about 10 pm (0.01 mm), but considering the yield in mass production (to avoid edge burr leading to short circuit), the actual minimum S is usually 0.1 mm (100 pm). Maximum spacing limit: affected by the package size and electromagnetic shielding requirements. When S is too large, the shielding effect of the ground line on the signal line is weakened (high-frequency signals are easily disturbed by the outside world), and the overall size of the package is increased (not in line with the miniaturization trend). For example, the package size of a mobile phone radio frequency module is usually less than 10 mm x 10 mm, if S exceeds 0.5 mm, the total width of two ground lines and one signal line will exceed 2 mm (S x 2 + line width), occupying too much space, so the maximum value of S is usually set to 0.5 mm.

[0065] (3) Process constraints of the involute angle a: Minimum angle limit: affected by the curvature radius of the RDL corner. Too small involute angle (such as less than 30°) will cause the signal line corner to be too steep, and the lithography process will be difficult to produce a smooth corner (easy to appear corner line width narrowing or broken line), and high-frequency signals will produce impedance mutation at sharp bends (increase reflection). Maximum angle limit: affected by the wiring space and signal path length. Too large a (such as more than 120°) will cause the "unfolding range" of the involute to be too large, occupying too much fan-out area space, and even possibly crossing with other signal lines. At the same time, too large a will indirectly increase the actual length of the signal line (L becomes longer), resulting in increased loss, so the maximum value of a is usually set to 120°.

[0066] On this basis, within the physical range allowed by the process, the parameter range also needs to be further narrowed according to the application scenario of the product (such as working frequency, transmission rate, anti-interference requirement) to ensure that the parameter combination can meet the core performance indicators.

[0067] (1) Influence of working frequency on parameter range: high-frequency scenario (such as millimeter wave radar 77GHz): signal wavelength is extremely short (about 4 mm), and small changes in L and S will cause impedance and loss to fluctuate sharply. Therefore, the parameter range needs to be narrowed to ensure stability, for example, L is 0.5-1.5 mm (to avoid too long leading to loss), and S is 0.2-0.4 mm (to balance shielding and impedance matching). Low-frequency scenario (such as 5G Sub-6GHz): signal wavelength is relatively long (about 50 mm), and the influence of parameter changes on performance is relatively mild, so the range can be appropriately relaxed, for example, L is 0.5-2.0 mm, and S is 0.1-0.5 mm.

[0068] (2) Anti-interference requirements on S: If the application scenario has strong electromagnetic interference (such as the engine environment in automotive electronics), a stronger ground shield is needed, so S needs to take a smaller value (such as 0.1-0.3mm) to make the ground closer to the signal line; if it is a low-interference environment (such as laboratory instruments), S can be appropriately increased (such as 0.3-0.5mm) to reduce the pressure on the package size.

[0069] (3) Transmission rate on L: High-speed signals (such as 10Gbps and above) are sensitive to delay, and L needs to take a smaller value (such as 0.5-1.0mm) to reduce transmission time; low-speed signals (such as 1Gbps and below) have low delay requirements, and L can be appropriately large (such as 1.0-2.0mm) to simplify wiring.

[0070] Therefore, the embodiment can obtain the RDL process parameter table from the package foundry, and determine the minimum line length, the maximum line length, the minimum spacing, the minimum angle, and other hard indicators; then determine the working frequency, the transmission rate, the upper limit of the package size, and other indicators according to the product manual. The process limit is the absolute boundary, and the scene requirement is the performance boundary, and the intersection of the two is taken as the final range.

[0071] In the preferred embodiment, the parameter sampling point division is performed on the key dimension range set according to the initial parameter step length of each key dimension range, a parameter sample set of each radio frequency chip package design task is constructed, and a package size theoretical calculation time consumption step of each radio frequency chip package design task is estimated, which specifically includes:

[0072] S210: The parameter sampling point division is performed on the key dimension range set according to the initial parameter step length of each key dimension range, and a plurality of size intervals of each key dimension range are obtained; wherein the initial parameter step length is configured to be greater than the minimum parameter step length;

[0073] S220: Based on the combination of different size intervals of each key dimension range, a parameter sample set combined by different size intervals in each radio frequency chip package design task is constructed;

[0074] S230: According to the different size interval combination of each parameter sample in the parameter sample set, the number of automatic simulation size combinations of each radio frequency chip package design task is determined, and the number of manual simulation size combinations is determined according to the ratio of the initial parameter step length to the minimum parameter step length;

[0075] S240: According to the historical automatic simulation time consumption data and the historical manual simulation time consumption data recorded in the historical simulation database, the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated.

[0076] In this embodiment, the execution time of the theoretical calculation of the package size of each radio frequency chip package design is estimated by the historical automatic simulation data and the historical manual simulation data of the historical simulation database.

[0077] In a preferred embodiment, based on the theoretical calculation time of the package size of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to corresponding radio frequency chip package design terminals, a radio frequency chip design task execution time table for each radio frequency chip package design terminal is generated, and each designer is driven to perform the automatic simulation coarse positioning and manual simulation fine positioning steps of each radio frequency chip package design task according to the radio frequency chip design task execution time table received by the configured radio frequency chip package design terminal, which specifically includes:

[0078] S310: Based on the theoretical calculation time of the package size of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to radio frequency chip package design terminals, so that the total number of allocated radio frequency chip package design terminals is minimized and the execution completion time of the last radio frequency chip package design task of each radio frequency chip package design terminal is within the target time period;

[0079] S320: According to the execution time period of each radio frequency chip package design task allocated to the corresponding radio frequency chip package design terminal, a radio frequency chip design task execution time table for each radio frequency chip package design terminal is generated;

[0080] S330: Drive each designer to sequentially perform the automatic simulation coarse positioning and manual simulation fine positioning of each radio frequency chip package design task according to the radio frequency chip design task execution time table received by the configured radio frequency chip package design terminal.

[0081] Further, the automatic simulation coarse positioning specifically includes:

[0082] S331: According to the parameter sample set of each radio frequency chip package design task combined by different size intervals, batch generate the simulation model corresponding to each size interval combination, automatically submit all simulation models to the simulation software by script, and obtain the electrical performance parameter set output by the simulation software;

[0083] S332: The size interval combination and the electrical performance parameter of each radio frequency chip package design task are constructed as training samples, and the RELU is used as the activation function to train the neural network model to obtain the trained inverse inversion neural network machine learning model;

[0084] S333: The electrical performance target set in the radio frequency chip package design task is input into the inverse inversion neural network machine learning model to obtain the target key size interval of each key size range.

[0085] In this embodiment, simulation software such as ansys HFSS can be used to estimate its performance to obtain the corresponding electromagnetic response curve, and then integrate the processing to take -10dB as the threshold for judging the S11 / S22 value, and -1dB as the judgment threshold of S21. The structure parameter combination matrix is set as an X matrix of (1x3), and the response parameter matrix is set as a Y matrix of (3x1). A number of effective structure parameter-response curve data are obtained, which are used as a sample training set to train a reverse inversion neural network machine learning model. ReLU is used as the activation function. After training, the actual electromagnetic response curve can be accepted as input, and the structure parameter interval that produces the characteristics is deduced reversely.

[0086] Further, artificial simulation fine positioning specifically includes:

[0087] S334: using bisection method to sequentially simulate each minimum parameter step combination in the target critical dimension interval of each critical dimension range, and judging whether the simulation result of each time meets the electrical performance target set in the radio frequency chip packaging design task;

[0088] S335: if yes, the artificial simulation fine positioning is completed, and each critical dimension range of the target critical dimension meeting the electrical performance target set in the radio frequency chip packaging design task is output as the design size.

[0089] In this embodiment, when facing the customized demand of small quantity and various forms, the small-batch radio frequency chip product design in the niche scene or the technical exploration stage, using the non-iterative sample collection and the later small amount of adjustment method, for the customized and dispersed characteristics rather than the demand of scale design, the design cost and efficiency can be balanced, and the situation that the time and computing power cost of the early investment is higher than the small-batch production benefit caused by the traversal simulation covering all parameter ranges and generating models in batches can be avoided.

[0090] In the preferred embodiment, based on the packaging size actual calculation time consumption and the radio frequency chip design task execution time period table, the initial parameter step of the next radio frequency chip packaging design task execution automatic simulation coarse positioning is updated to the real-time parameter step to adjust the packaging size actual calculation time consumption step of the next radio frequency chip packaging design task, specifically including:

[0091] S510: based on the packaging size actual calculation time consumption and the radio frequency chip design task execution time period table, judging whether the completion time of the current radio frequency chip packaging design task exceeds the tolerance threshold compared with the theoretical completion time in the radio frequency chip design task execution time period table;

[0092] S520: If yes, update the initial parameter step length of the automatic simulation coarse positioning of the next radio frequency chip package design task to a real-time parameter step length according to a preset rule to adjust the actual calculation time consumption of the package size of the next radio frequency chip package design task.

[0093] On this basis, the preset rule is configured to: reduce a first parameter step length ratio of the next radio frequency chip package design task by a preset adjustment ratio compared with a second parameter step length ratio of the current radio frequency chip package design task; wherein the first parameter step length ratio is configured as a ratio of the initial parameter step length of the automatic simulation coarse positioning of the next radio frequency chip package design task to the minimum parameter step length, and the second parameter step length ratio is configured as a ratio of the initial parameter step length of the automatic simulation coarse positioning of the current radio frequency chip package design task to the minimum parameter step length.

[0094] In the embodiment, if it is monitored that the completion time of the current radio frequency chip package design task exceeds the tolerance threshold of the theoretical completion time in the radio frequency chip design task execution period table, the initial parameter step length of the next chip package design task needs to be adjusted downward. By adjusting the initial parameter step length downward, the number of critical dimension intervals in each critical dimension range is increased, and when training is performed by using the intervals as samples, a critical dimension design result with higher inversion accuracy can be obtained. When subsequent artificial simulation fine positioning is performed by using the critical dimension design result, the fine positioning time consumption can be greatly reduced, and the time consumption occupied by the current radio frequency chip package design task is compensated by using as little computing power consumption as possible (the computing power consumption will be multiplied by the increase in the number of critical dimension intervals).

[0095] Referring to Figure 4 , Figure 4 FIG. 1 is a structural schematic diagram of a radio frequency chip fan-out package design system based on machine learning optimization according to an embodiment of the present application.

[0096] As shown in Figure 4 , the radio frequency chip fan-out package design system based on machine learning optimization according to an embodiment of the present application comprises:

[0097] The task acquisition module 10 is configured to acquire a plurality of radio frequency chip package design tasks in a target period; wherein the radio frequency chip package design task comprises a critical dimension range set and an electrical performance target set;

[0098] The time consumption estimation module 20 is configured to divide the critical dimension range set according to the initial parameter step length of each critical dimension range to perform parameter sampling point division, construct a parameter sample set of each radio frequency chip package design task, and estimate the theoretical calculation time consumption of the package size of each radio frequency chip package design task;

[0099] The size positioning module 30 is used for allocating a plurality of radio frequency chip package design tasks to corresponding radio frequency chip package design terminals based on a theoretical calculation time of a package size of each radio frequency chip package design, generating a radio frequency chip design task execution time period table of each radio frequency chip package design terminal, and driving each designer to perform automatic simulation coarse positioning and manual simulation fine positioning of each radio frequency chip package design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip package design terminal.

[0100] The automatic simulation coarse positioning includes machine learning model training based on a plurality of key sizes and key size range positioning based on an electrical performance target set, and the manual simulation fine positioning includes key size fine positioning based on key size dichotomy.

[0101] The time consumption statistical module 40 is used for statistically determining a package size actual calculation time of each designer when performing the automatic simulation coarse positioning and the manual simulation fine positioning of each radio frequency chip package design task.

[0102] The step updating module 50 is used for updating an initial parameter step of automatic simulation coarse positioning of a next radio frequency chip package design task to a real-time parameter step based on the package size actual calculation time and the radio frequency chip design task execution time period table, so as to adjust the package size actual calculation time of the next radio frequency chip package design task.

[0103] Other embodiments or specific implementations of the radio frequency chip fan-out package design system based on machine learning optimization can refer to the above-mentioned method embodiments, which will not be described here.

[0104] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for radio frequency chip fan-out package design based on machine learning optimization, characterized in that, The method comprises the following steps: Obtaining a plurality of radio frequency chip packaging design tasks within a target period; wherein the radio frequency chip packaging design task comprises a critical dimension range set and an electrical performance target set; According to the initial parameter step length of each critical dimension range, the parameter sampling point of the critical dimension range set is divided, the parameter sample set of each radio frequency chip packaging design task is constructed, and the packaging size theoretical calculation time of each radio frequency chip packaging design task is estimated; Based on the packaging size theoretical calculation time of each radio frequency chip packaging design, the plurality of radio frequency chip packaging design tasks are distributed to the corresponding radio frequency chip packaging design terminal, the radio frequency chip design task execution time period table of each radio frequency chip packaging design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and artificial simulation fine positioning of each radio frequency chip packaging design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip packaging design terminal; Wherein, the automatic simulation coarse positioning includes machine learning model training based on a plurality of critical dimensions automatic simulation and critical dimension range positioning based on the electrical performance target set, and the artificial simulation fine positioning includes critical dimension fine positioning based on critical dimension dichotomy; Statistical analysis of the packaging size actual calculation time determined by each designer when executing the automatic simulation coarse positioning and artificial simulation fine positioning of each radio frequency chip packaging design task; Based on the packaging size actual calculation time and the radio frequency chip design task execution time period table, the initial parameter step length of the next radio frequency chip packaging design task execution automatic simulation coarse positioning is updated to the real-time parameter step length, so as to adjust the packaging size actual calculation time of the next radio frequency chip packaging design task.

2. The machine learning optimization based radio frequency chip fan-out package design method of claim 1, wherein, The step of obtaining a plurality of radio frequency chip packaging design tasks within a target period comprises: Receiving the radio frequency chip packaging design requirement information uploaded by each task request terminal; wherein the radio frequency chip packaging design requirement information contains an electrical performance target set and a first critical dimension range set with a plurality of critical dimension ranges; Obtaining the radio frequency chip packaging design capability information of the packaging foundry; wherein the radio frequency chip packaging design capability information includes a second critical dimension range set with a plurality of critical dimension ranges; Based on the intersection of corresponding critical dimension ranges in the first critical dimension range set and the second critical dimension range set, the critical dimension range set is determined, and the critical dimension range set and the electrical performance target set are used to generate a plurality of radio frequency chip packaging design tasks.

3. The machine learning optimization based radio frequency chip fan-out package design method of claim 2, wherein, The radio frequency chip packaging design requirement information is configured as a plurality of critical dimension ranges entered by the task requester based on a plurality of index parameters in the radio frequency chip product manual on the task request terminal, and the radio frequency chip packaging design capability information is configured as a plurality of critical dimension ranges in the RDL process parameter table of the packaging foundry entered by the designer.

4. The machine learning optimization based radio frequency chip fan-out package design method of claim 3, wherein, The critical dimension range set includes RDL signal line length L, signal line and ground line spacing S, and signal involute angle α, and the electrical performance target set includes characteristic impedance Ro, return loss S11 / S22 and insertion loss S21.

5. The machine learning optimization based radio frequency chip fan-out package design method of claim 1, wherein, According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes:

6. The machine learning optimization based radio frequency chip fan-out package design method of claim 5, wherein, Based on the package size theoretical calculation time consumption of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to corresponding radio frequency chip package design terminals, a radio frequency chip design task execution time period table of each radio frequency chip package design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and manual simulation fine positioning steps of each radio frequency chip package design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip package design terminal, which specifically includes: Based on the package size theoretical calculation time consumption of each radio frequency chip package design, a plurality of radio frequency chip package design tasks are allocated to corresponding radio frequency chip package design terminals, a radio frequency chip design task execution time period table of each radio frequency chip package design terminal is generated, and each designer is driven to execute the automatic simulation coarse positioning and manual simulation fine positioning steps of each radio frequency chip package design task according to the radio frequency chip design task execution time period table received by the configured radio frequency chip package design terminal, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes:

7. The machine learning optimization based radio frequency chip fan-out package design method of claim 6, wherein, The automatic simulation coarse positioning specifically includes: According to the initial parameter step length of each critical dimension range, the parameter sampling point division is performed on the critical dimension range set, the parameter sample set of each radio frequency chip package design task is constructed, and the package size theoretical calculation time consumption of each radio frequency chip package design task is estimated, which specifically includes: The size interval combination and the electrical performance parameter of each radio frequency chip package design task are constructed as training samples, a RELU is used as an activation function to train a neural network model, and a trained inverse inversion neural network machine learning model is obtained. The electrical performance target set in the radio frequency chip package design task is input into the inverse inversion neural network machine learning model to obtain a target critical dimension interval for each critical dimension range.

8. The machine learning optimization based radio frequency chip fan-out package design method of claim 7, wherein, The artificial simulation fine positioning specifically includes: The bisection method is used to perform software simulation on each minimum parameter step combination in the target critical dimension interval of each critical dimension range in sequence, and it is judged whether the software simulation result each time meets the electrical performance target set in the radio frequency chip package design task. If yes, the artificial simulation fine positioning is completed, and each target critical dimension of each critical dimension range corresponding to the electrical performance target set in the radio frequency chip package design task is output as a design size.

9. The machine learning optimization based radio frequency chip fan-out package design method of claim 1, wherein, Based on the package size actual calculation time consumption and the radio frequency chip design task execution time period table, the initial parameter step of the next radio frequency chip package design task execution automatic simulation coarse positioning is updated to a real-time parameter step to adjust the package size actual calculation time consumption step of the next radio frequency chip package design task, specifically including: Based on the package size actual calculation time consumption and the radio frequency chip design task execution time period table, it is judged whether the actual completion time of the current radio frequency chip package design task exceeds the tolerance threshold compared with the theoretical completion time in the radio frequency chip design task execution time period table. If yes, the initial parameter step of the next radio frequency chip package design task execution automatic simulation coarse positioning is updated to a real-time parameter step according to a preset rule to adjust the package size actual calculation time consumption of the next radio frequency chip package design task.

10. The machine learning optimization based radio frequency chip fan-out package design method of claim 9, wherein, The preset rule is configured to reduce the first parameter step ratio of the next radio frequency chip package design task compared with the second parameter step ratio of the current radio frequency chip package design task by a preset adjustment ratio, wherein the first parameter step ratio is configured as the ratio of the initial parameter step of the next radio frequency chip package design task execution automatic simulation coarse positioning to the minimum parameter step, and the second parameter step ratio is configured as the ratio of the initial parameter step of the current radio frequency chip package design task execution automatic simulation coarse positioning to the minimum parameter step.

Images