Drive circuit for chopper switch circuit and chopper

Abstract

The application discloses a kind of chopper switch circuit driving circuit and chopper.The driving circuit is with first level shift module and second level shift module respectively with the input common-mode voltage of chopper switch circuit as reference to obtain first pair of complementary clock signals and second pair of complementary clock signals, and the low level of first pair of complementary clock signals is lower than input common-mode voltage, and the high level of second pair of complementary clock signals is higher than input common-mode voltage, then through gating combination module in the same period alternatively the low level of first pair of complementary clock signals and the high level of second pair of complementary clock signals are alternately transmitted to drive clock output end, to synthesize the drive clock pair with greater voltage swing, so that when the input differential voltage of chopper switch circuit is larger or even close to power supply voltage, reliable conduction and turn-off of switch can still be realized, effectively avoid the generation of high-temperature leakage channel, improve the integrity of signal transmission and system reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a drive circuit and a chopper for a chopper switch circuit. Background Technology

[0002] Chopper modulation technology is widely used in precision amplifiers, sensor interfaces, and ADC front-ends to suppress low-frequency noise and offset voltage. Traditional implementations typically use all-NMOS or PMOS switches to construct the chopper switch circuit, driven either directly by an on-chip clock or via capacitive coupling. When the input signal common-mode level is close to the supply voltage and the input differential voltage is small, this structure can reliably turn the switch on or off, maintaining low on-resistance and leakage current.

[0003] However, as applications demand higher dynamic range, large differential voltages frequently appear at the input of chopper switch circuits. For example, with a power supply voltage of 2.5 V and the input common-mode voltage near the power supply midpoint, if the input differential signal reaches 1 V or even higher, the instantaneous voltage on one side of the chopper switch circuit will approach VCM + 0.5 V, and the instantaneous voltage on the other side will approach VCM - 0.5 V (where VCM represents the input common-mode voltage). In this case, if traditional capacitive coupling drive or internal clock drive methods are still used, the high level of the drive signal will only be higher than the input common-mode voltage VCM by one power supply voltage VDD, and the low level of the drive signal will be equal to the input common-mode voltage VCM. This causes the gate-source voltage of the turn-off switch to be near the turn-off threshold, making complete turn-off difficult, thus forming a situation like... Figure 4 and Figure 5 The leakage current path shown causes signal crosstalk and decreased accuracy. In particular, the leakage current increases significantly under high temperature conditions, which seriously affects the accuracy and stability of chopper modulation.

[0004] To alleviate the aforementioned problems, existing solutions have attempted to increase the driving voltage amplitude, such as by employing a separate high-voltage process or an additional power supply. However, this increases process complexity and system cost. Other solutions involve connecting a resistor in series at the input or adding a compensation current to reduce the impact of leakage current on the output; however, these methods introduce thermal noise, increase the area, and do not fundamentally eliminate the leakage path. Therefore, how to ensure that the chopper switching circuit maintains full conduction and complete turn-off even with a large input differential voltage, without requiring an additional high-voltage power supply, using standard low-voltage processes, remains a pressing challenge in current technology. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a driving circuit and a chopper for a chopper switch circuit, so that the chopper switch circuit can maintain full conduction and full cut-off even when the input differential voltage is large, effectively avoid the generation of high temperature leakage channels, and ensure that the signal can be transmitted stably and correctly in high and low temperature environments, thereby improving the working reliability and signal integrity of the chopper in a wide temperature range.

[0006] According to one aspect of the present invention, a driving circuit for a chopper switch circuit is provided, comprising: a first level shifting module for obtaining a first pair of complementary clock signals based on the input common-mode voltage of the chopper switch circuit, wherein the low level of the first pair of complementary clock signals is lower than the input common-mode voltage; a second level shifting module for obtaining a second pair of complementary clock signals based on the input common-mode voltage, wherein the high level of the second pair of complementary clock signals is higher than the input common-mode voltage; and a gating combination module for selectively transmitting the low level of the first pair of complementary clock signals and the high level of the second pair of complementary clock signals alternately to an output terminal within the same period, so as to generate a driving clock pair for applying to the chopper switch circuit at the output terminal, wherein the high level of the driving clock pair is higher than the input common-mode voltage and the low level is lower than the input common-mode voltage.

[0007] Optionally, the high level of the driving clock pair is equal to the sum of the input common-mode voltage and the power supply voltage, and the low level of the driving clock pair is equal to the voltage difference between the input common-mode voltage and the power supply voltage.

[0008] Optionally, the first level shifting module includes: a first capacitor, the first end of which is used to connect to an input clock signal; a second capacitor, the first end of which is used to connect to the inverted signal of the input clock signal; a first transistor having a first conductivity type, the first end of which is connected to the input common-mode voltage, and the second end of which is connected to the second end of the first capacitor; and a second transistor having the first conductivity type, the first end of which is connected to the input common-mode voltage, the control terminal of which is connected to the second end of the first transistor and the second end of the first capacitor, and the second end of which is connected to the control terminal of the first transistor and the second end of the second capacitor, wherein the second ends of the first transistor and the second transistor serve as the output terminals of the first pair of complementary clock signals.

[0009] Optionally, the second level shifting module includes: a third capacitor, the first end of which is connected to the input clock signal; a fourth capacitor, the first end of which is connected to the inverted signal of the input clock signal; a third transistor having a second conductivity type, the first end of which is connected to the second end of the third capacitor, and the second end of which is connected to the input common-mode voltage; and a fourth transistor having the second conductivity type, the first end of which is connected to the second end of the fourth capacitor and the control terminal of the third transistor, the control terminal of which is connected to the second end of the third transistor and the second end of the third capacitor, and the second end of which is connected to the input common-mode voltage, wherein the first ends of the third transistor and the fourth transistor serve as the output terminals of the second pair of complementary clock signals.

[0010] Optionally, the gating combination module includes: a fifth transistor and a sixth transistor having the second conductivity type, the second terminal of the fifth transistor being connected to one of the first pair of complementary clock signals, the first terminal of the fifth transistor being connected to the first output terminal of the driving clock pair, the second terminal of the sixth transistor being connected to the other of the first pair of complementary clock signals, and the first terminal of the sixth transistor being connected to the second output terminal of the driving clock pair; and a seventh transistor and an eighth transistor having the first conductivity type, the first terminal of the seventh transistor being connected to one of the second pair of complementary clock signals, its second terminal being connected to the first output terminal of the driving clock pair, the first terminal of the eighth transistor being connected to the other of the second pair of complementary clock signals, and its second terminal being connected to the second output terminal of the driving clock pair, wherein the control terminals of the fifth transistor to the eighth transistor are all connected to the input common-mode voltage.

[0011] Optionally, the first conductivity type is P-type, and the second conductivity type is N-type.

[0012] Optionally, the input clock signal has a voltage level range of 0V to the power supply voltage.

[0013] Optionally, the driving circuit further includes: a first inverter for generating the input clock signal based on an initial clock signal; and a second inverter for generating an inverted signal of the input clock signal based on the input clock signal, wherein the power supply terminals of the first inverter and the second inverter are connected to the power supply voltage, such that the level range of the input clock signal and its inverted signal is from 0V to the power supply voltage.

[0014] According to another aspect of the present invention, a chopper is provided, comprising: a chopper switch circuit; and a driving circuit for generating a driving clock signal to control the chopper switch circuit to turn on and off, thereby realizing the periodic reversal of the input signal.

[0015] In summary, the driving circuit for the chopper switch circuit provided in this embodiment of the invention obtains a first pair of complementary clock signals and a second pair of complementary clock signals based on the input common-mode voltage of the chopper switch circuit through a first level shifting module and a second level shifting module, respectively. The low level of the first pair of complementary clock signals is lower than the input common-mode voltage, and the high level of the second pair of complementary clock signals is higher than the input common-mode voltage. Then, through a gating and combining module, the low level of the first pair of complementary clock signals and the high level of the second pair of complementary clock signals are alternately transmitted to the driving clock output terminal in the same cycle, thereby synthesizing a driving clock pair with a larger voltage swing. When the driving clock is directly applied to the gate of the all-NMOS chopper switch circuit, the gate-source voltage of the on-side switch is sufficiently higher than its threshold voltage, and the gate-source voltage of the off-side switch is significantly lower than its threshold voltage. This allows for reliable switching on and off even when the input differential voltage of the chopper switch circuit is large or even close to the power supply voltage. This effectively avoids the generation of high-temperature leakage paths and ensures that the signal can be transmitted stably and correctly in both high and low temperature environments, thereby improving the chopper's operational reliability and signal integrity over a wide temperature range. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic circuit diagram of a conventional chopper switch circuit is shown.

[0018] Figure 2 A schematic circuit diagram of a drive circuit for a chopper switch circuit according to the prior art is shown.

[0019] Figure 3 A schematic waveform diagram of a drive circuit according to the prior art is shown.

[0020] Figure 4 This diagram illustrates the leakage current path generated by a conventional chopper switch circuit during signal pass-through transmission under large differential input.

[0021] Figure 5 This diagram illustrates the leakage current path generated during signal cross-transmission in a conventional chopper switch circuit with large differential input.

[0022] Figure 6 A schematic circuit diagram of a drive circuit for a chopper switch circuit according to an embodiment of the present invention is shown.

[0023] Figure 7 A schematic waveform diagram of a driving circuit according to an embodiment of the present invention is shown.

[0024] Figure 8A schematic structural diagram of a chopper according to an embodiment of the present invention is shown.

[0025] Figure 9 A schematic diagram of the path of a chopper during signal pass-through transmission according to an embodiment of the present invention is shown.

[0026] Figure 10 A schematic diagram of the path of a chopper during signal cross-transmission according to an embodiment of the present invention is shown. Detailed Implementation

[0027] Exemplary embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts.

[0028] In this specification, it should be noted that similar reference numerals already used to denote similar parts in other figures are used for these elements whenever possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are not related to the basic configuration of this disclosure will be omitted. The terminology described in this specification should be understood as follows.

[0029] The advantages and features of this disclosure, and its implementation methods, will be set forth through the embodiments described below with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, so as to fully communicate the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0030] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the illustrated details. Similar reference numerals always denote similar elements. In the following description, detailed descriptions will be omitted where it would inevitably obscure the focus of this disclosure if a detailed description of a related known function or construction were to be determined.

[0031] When using the terms “comprising,” “having,” and “including” as described in this specification, an additional part may be added unless “only” is used. Unless otherwise stated to the contrary, singular terms may include plural forms.

[0032] It should be understood that although the terms "first," "second," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component.

[0033] The term "at least one" should be understood to include any combination of one or more of the items listed. For example, "at least one of the first, second, and third items" means any combination of two or more items proposed from the first, second, and third items, as well as the first, second, or third item alone.

[0034] As will be fully appreciated by those skilled in the art, the features of the various embodiments of this disclosure may be combined or integrated with each other in whole or in part, and may be interoperable and technically driven with each other in various ways. The embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0035] In all embodiments of the present invention, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled intermediate terminal of the MOS transistor is referred to as the control terminal, and the other two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. For ease of consistent expression, in this context, the source, drain, and gate of a PMOS transistor are referred to as the first terminal, the second terminal, and the control terminal, respectively, and the drain, source, and gate of an NMOS transistor are referred to as the first terminal, the second terminal, and the control terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0036] Figure 1 A schematic circuit diagram of a traditional chopper switch circuit is shown. (e.g.) Figure 1As shown, a conventional chopper switch circuit 100 includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first terminals of the first switch S1 and the second switch S2 are connected to the positive input terminal Vinp, the second terminal of the first switch S1 is connected to the positive output terminal Voutp, the second terminal of the second switch S2 is connected to the negative output terminal Voutn, the first terminals of the third switch S3 and the fourth switch S4 are connected to the negative input terminal Vinn, the second terminal of the third switch S3 is connected to the positive output terminal Voutp, and the second terminal of the fourth switch S4 is connected to the negative output terminal Voutn. When the first switch S1 and the fourth switch S4 are on, and the second switch S2 and the third switch S3 are off, the positive input terminal Vinp of the chopper switch circuit 100 is connected to the positive output terminal Voutp, and the negative input terminal Vinn is connected to the negative output terminal Voutn. The signals from the positive and negative input terminals are directly transmitted to the positive and negative output terminals Voutp and Voutn, respectively. When the second switch S2 and the third switch S3 are on, and the first switch S1 and the fourth switch S4 are off, the positive input terminal Vinp of the chopper switch circuit 100 is connected to the negative output terminal Voutn, and the negative input terminal Vinn is connected to the positive output terminal Voutp. The signals from the positive and negative input terminals are transmitted to the negative and positive output terminals Voutp in a cross-transmission manner. By periodically switching the switch combination states, chopping modulation of the input signal can be achieved, effectively suppressing DC offset and low-frequency noise.

[0037] For example, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 in the chopper switch circuit 100 can be constructed from MOS transistors, and their on / off states are controlled by a driving clock pair. Further, this driving clock pair includes a complementary first driving clock signal CLKp and a second driving clock signal CLKn. The first driving clock signal CLKp is used to periodically control the on / off states of the first switch S1 and the fourth switch S4, and the second driving clock signal CLKn is used to periodically control the on / off states of the second switch S2 and the third switch S3, thereby achieving periodic reversal of the input signal. Further, the first switch S1 to the fourth switch S4 can be implemented using NMOS transistors, with the gates of the first switch S1 and the fourth switch S4 connected to the first driving clock signal CLKp, and the gates of the second switch S2 and the third switch S3 connected to the second driving clock signal CLKn. When the first driving clock signal CLKp is high, the first switch S1 and the fourth switch S4 are turned on, and the second driving clock signal CLKn is low, and the second switch S2 and the third switch S3 are turned off; when the second driving clock signal CLKn is high, the second switch S2 and the third switch S3 are turned on, and the first driving clock signal CLKp is low, and the first switch S1 and the fourth switch S4 are turned off.

[0038] Figure 2A schematic circuit diagram of a drive circuit for a chopper switch circuit according to the prior art is shown. Figure 2 As shown, the conventional driving circuit 200 includes a first inverter INV1, a second inverter INV2, a first capacitor C1, a second capacitor C2, a first NMOS transistor Mn1, and a second NMOS transistor Mn2. The input of the first inverter INV1 receives the initial clock signal CLK0, and its output outputs the input clock signal CLK_in, whose level range is from the power supply voltage VDD to the reference ground GND. The input of the second inverter INV2 is connected to the output of the first inverter INV1, and its output outputs the inverted signal CLK_inb, whose level range is from the power supply voltage VDD to the reference ground GND. The first terminal of the first capacitor C1 is connected to the output terminal of the first inverter INV1, and the second terminal of the first capacitor C1 is connected to the drain of the first NMOS transistor Mn1 and the gate of the second NMOS transistor Mn2. The first terminal of the second capacitor C2 is connected to the output terminal of the second inverter INV2, and the second terminal of the second capacitor C2 is connected to the drain of the second NMOS transistor Mn2 and the gate of the first NMOS transistor Mn1. The sources of both the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are connected to the input common-mode voltage VCM of the chopper switch circuit. Furthermore, the second terminal of the first capacitor C1 is also used to connect to the output terminal of the first drive clock signal CLKp, and the second terminal of the second capacitor C2 is also used to connect to the output terminal of the second drive clock signal CLKn, for transmitting the level-shifted drive clock pair to the chopper switch circuit.

[0039] Figure 3 A schematic waveform diagram of a drive circuit according to the prior art is shown. (e.g.) Figure 3As shown, the input clock signal CLK_in and its inverted signal CLK_inb are square wave signals that alternate between a high level with the power supply voltage VDD and a low level with a voltage of 0V. The high and low level states of the input clock signal CLK_in and its inverted signal CLK_inb are completely opposite. When the input clock signal CLK_in is high, its inverted signal CLK_inb is low. At this time, the gate voltage of the second NMOS transistor Mn2 is raised to a level higher than its drain voltage through the first capacitor C1, so the second NMOS transistor Mn2 is turned on. At the same time, the gate voltage of the first NMOS transistor Mn1 is lowered through the second capacitor C2, so the first NMOS transistor Mn1 is turned off. At this time, the first drive clock signal CLKp is at a level equal to VDD + VDD. When VCM is high, the second drive clock signal CLKn is at a low level equal to VCM. When the input clock signal CLK_in is low, its inverted signal CLK_inb is high. At this time, the gate voltage of the first NMOS transistor Mn1 is raised to a higher level than its drain voltage through the coupling of the second capacitor C2, so the first NMOS transistor Mn1 is turned on. At the same time, the gate voltage of the second NMOS transistor Mn2 is lowered through the coupling of the first capacitor C1, so the second NMOS transistor Mn2 is turned off. At this time, the first drive clock signal CLKp is at a low level equal to VCM, and the second drive clock signal CLKn is at a high level equal to VDD + VCM.

[0040] Therefore, the conventional drive circuit 200 can obtain a first drive clock signal CLKp and a second drive clock signal CLKn with a certain voltage offset relative to the input clock signal CLK_in and its inverted signal CLK_inb. The high and low levels of the first drive clock signal CLKp and the second drive clock signal CLKn have an offset relative to the input clock signal CLK_in and its inverted signal CLK_inb that increases the input common-mode voltage VCM, thereby meeting the requirements of the high-voltage domain chopper switch for the drive signal level.

[0041] Figure 4 This diagram illustrates the leakage current path generated by a conventional chopper switch circuit during signal pass-through transmission under large differential input. Figure 5 This diagram illustrates the leakage current path generated during signal cross-transmission in a conventional chopper switch circuit with large differential input. Figure 4 and Figure 5 In the example, taking a power supply voltage VDD of 2.5V and an input differential voltage of 1V as an example, the positive input voltage Vinp of the chopper switch circuit 100 is VCM+0.5V, and the negative input voltage Vinn is VCM-0.5V.

[0042] like Figure 4As shown, when the first driving clock signal CLKp is high (VCM + 2.5V) and the second driving clock signal CLKn is low (VCM), ideally, the first switch S1 and the fourth switch S4 in the chopper switch circuit 100 are turned on, while the second switch S2 and the third switch S3 are turned off. The signal at the positive input terminal Vinp is transmitted to the positive output terminal Voutp through the turned-on first switch S1, and the signal at the negative input terminal Vinn is transmitted to the negative output terminal Voutn through the turned-on fourth switch S4, thus achieving direct signal transmission. However, since the source voltage of the third switch S3 is equal to the negative input terminal voltage Vinn = VCM - 0.5V, and its gate is driven to the VCM level, the gate-source voltage VGS of the third switch S3 is VCM - (VCM - 0.5V) = 0.5V. If this voltage exceeds its threshold voltage, the third switch S3 will not be completely turned off, resulting in... Figure 4 The dashed line PathA in the figure shows the leakage current path, which introduces distortion and error at the output.

[0043] Similarly, such as Figure 5 As shown, when the first driving clock signal CLKp is low (VCM) and the second driving clock signal CLKn is high (VDD + VCM), ideally, the second switch S2 and the third switch S3 are turned on, while the first switch S1 and the fourth switch S4 are turned off. The signal at the positive input terminal Vinp is transmitted to the negative output terminal Voutn through the turned-on second switch S2, and the signal at the negative input terminal Vinn is transmitted to the positive output terminal Voutp through the turned-on third switch S3, thus achieving cross-transmission of signals. However, since the source voltage of the fourth switch S4 is the negative input terminal voltage Vinn = VCM - 0.5V, its gate is driven to the VCM level, resulting in the gate-source voltage VGS of the fourth switch S4 = VCM - (VCM - 0.5V) = 0.5V. If this voltage exceeds its threshold voltage, the fourth switch S4 cannot be completely turned off, forming a situation as follows. Figure 5 The leakage current path shown by the dashed line PathB causes distortion of the output signal.

[0044] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 6 A schematic circuit diagram of a drive circuit for a chopper switch circuit according to an embodiment of the present invention is shown. Figure 6 As shown, the driving circuit 300 in this embodiment includes a first level shifting module 310, a second level shifting module 320, and a gating combination module 330.

[0046] The first level shifting module 310 is used to generate a first pair of complementary clock signals by shifting the input clock signal CLK_in and its inverted signal CLK_inb based on the input common-mode voltage VCM of the chopper switch circuit. For example, the first pair of complementary clock signals includes a first clock signal CLK1 and a second clock signal CLK1b, wherein the low level of the first clock signal CLK1 and the second clock signal CLK1b is lower than the input common-mode voltage VCM. For example, the level range of the input clock signal CLK_in and its inverted signal CLK_inb is from 0V to the power supply voltage VDD, and the level range of the first clock signal CLK1 and the second clock signal CLK1b is from VCM-VDD to VCM, where VCM is the input common-mode voltage of the chopper switch circuit.

[0047] The second level shift module 320 is used to shift the input clock signal CLK_in and its inverted signal CLK_inb by level offset based on the input common-mode voltage VCM to generate a second pair of complementary clock signals. For example, the second pair of complementary clock signals includes a third clock signal CLK2 and a fourth clock signal CLK2b, wherein the high level of the third clock signal CLK2 and the fourth clock signal CLK2b is higher than the input common-mode voltage VCM. For example, the level range of the third clock signal CLK2 and the fourth clock signal CLK2b is from VCM to VCM+VDD, that is, the second level shift module 320 shifts the level of the input clock signal CLK_in and its inverted signal CLK_inb upwards by the VCM level to obtain the third clock signal CLK2 and the fourth clock signal CLK2b.

[0048] The input terminals of the gating combination module 330 are respectively connected to the output terminals of the first level shift module 310 and the second level shift module 320, and are used to selectively transmit the low level of the first pair of complementary clock signals (including the first clock signal CLK1 and the second clock signal CLK1b) and the high level of the second pair of complementary clock signals (including the third clock signal CLK2 and the fourth clock signal CLK2b) to the output terminal within the same cycle, thereby synthesizing a driving clock pair with a larger voltage swing (including the first driving clock signal CLKp and the second driving clock signal CLKn). That is, the low level voltage of the first driving clock signal CLKp and the second driving clock signal CLKn in the driving clock pair is equal to VCM-VDD, and the high level voltage is equal to VCM+VDD.

[0049] Further, the first level shifting module 310 includes a first capacitor C1, a second capacitor C2, a first PMOS transistor Mp1, and a second PMOS transistor Mp2. The first terminal of the first capacitor C1 is connected to the input clock signal CLK_in, and the second terminal is connected to the drain of the first PMOS transistor Mp1 and the gate of the second PMOS transistor Mp2. The first terminal of the second capacitor C2 is connected to the inverted signal CLK_inb of the input clock signal CLK_in, and the second terminal is connected to the drain of the second PMOS transistor Mp2 and the gate of the first PMOS transistor Mp1. The sources of both the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are connected to the input common-mode voltage VCM. The drain of the first PMOS transistor Mp1 is used to output the first clock signal CLK1 in the first pair of complementary clock signals, and the drain of the second PMOS transistor Mp2 is used to output the second clock signal CLK1b in the first pair of complementary clock signals.

[0050] The second level shifting module 320 includes a third capacitor C3, a fourth capacitor C4, a first NMOS transistor Mn1, and a second NMOS transistor Mn2. The first terminal of the third capacitor C3 is connected to the input clock signal CLK_in, and the second terminal is connected to the drain of the first NMOS transistor Mn1 and the gate of the second NMOS transistor Mn2. The first terminal of the fourth capacitor C4 is connected to the inverted signal CLK_inb of the input clock signal CLK_in, and the second terminal is connected to the drain of the second NMOS transistor Mn2 and the gate of the first NMOS transistor Mn1. The sources of both the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are connected to the input common-mode voltage VCM. The drain of the first NMOS transistor Mn1 is used to output the third clock signal CLK2 in the second pair of complementary clock signals, and the drain of the second NMOS transistor Mn2 is used to output the fourth clock signal CLK2b in the second pair of complementary clock signals.

[0051] The gating combination module 330 includes a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a third NMOS transistor Mn3, and a fourth NMOS transistor Mn4. In this configuration, the source of the third NMOS transistor Mn3 is connected to the drain of the first PMOS transistor Mp1 in the first level shift module 310; the source of the fourth NMOS transistor Mn4 is connected to the drain of the second PMOS transistor Mp2 in the first level shift module 310; the source of the third PMOS transistor Mp3 is connected to the drain of the first NMOS transistor Mn1 in the second level shift module 320; the source of the fourth PMOS transistor Mp4 is connected to the drain of the second NMOS transistor Mn2 in the second level shift module 320; the drains of the third NMOS transistor Mn3 and the third PMOS transistor Mp3 are both connected to the output of the first driving clock signal CLKp; the drains of the fourth NMOS transistor Mn4 and the fourth PMOS transistor Mp4 are both connected to the output of the second driving clock signal CLKn; and the gates of the third NMOS transistor Mn3, the fourth NMOS transistor Mn4, the third PMOS transistor Mp3, and the fourth PMOS transistor Mp4 are all connected to the input common-mode voltage VCM.

[0052] Furthermore, the driving circuit 300 in this embodiment also includes a first inverter INV1 to a fourth inverter INV4. The input terminal of the first inverter INV1 is used to receive the initial clock signal CLK0, and its output terminal is connected to the first terminal of the first capacitor C1, for outputting the input clock signal CLK_in with a level range of 0V to the power supply voltage VDD. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and its output terminal is connected to the first terminal of the second capacitor C2, for outputting a clock signal CLK_inb that is inverted from the input clock signal CLK_in. The input terminal of the third inverter INV3 is connected to the initial clock signal CLK0, and its output terminal is connected to the first terminal of the third capacitor C3 to provide it with the input clock signal CLK_in. The input terminal of the fourth inverter INV4 is connected to the output terminal of the third inverter INV3, and its output terminal is connected to the first terminal of the fourth capacitor C4 to output a clock signal CLK_inb that is inverted from the input clock signal CLK_in. This ensures that the four sets of capacitor-transistor structures are strictly symmetrical in phase, improving the matching and stability of clock signal transmission.

[0053] Figure 7 A schematic waveform diagram of a driving circuit according to an embodiment of the present invention is shown. Figure 7 As shown, the input clock signal CLK_in and its inverted signal CLK_inb are square wave signals that alternate between a high level with power supply voltage VDD and a low level with voltage 0V.

[0054] When the input clock signal CLK_in changes from low to high, according to the principle that the voltage across a capacitor cannot change abruptly, the rising edge of the input clock signal CLK_in causes the voltage across the first capacitor C1 to rise. Therefore, the voltage change on the first clock signal CLK1 is +VDD. Simultaneously, the inverted signal CLK_inb of the input clock signal CLK_in changes from high to low, and the voltage across the second capacitor C2 decreases accordingly. Therefore, the voltage change on the second clock signal CLK1b is -VDD. Because the voltage of the second clock signal CLK1b decreases, the first PMOS transistor Mp1 turns on, pulling its source potential high to the input common-mode voltage VCM, which in turn causes the second PMOS transistor Mp2 to turn off. Since the potential of the second clock signal CLK1b in the previous state was VCM, after the clock signal CLK_inb changes from high to low, the potential of the second clock signal CLK1b becomes VCM - VDD. Similarly, since the first clock signal CLK1 was at a potential of VCM-VDD in the previous state, its potential rises to VCM after the input clock signal CLK_in changes from low to high. Likewise, when the input clock signal CLK_in changes from high to low, the voltage across the first capacitor C1 decreases, and the first clock signal CLK1 changes from VCM to VCM-VDD. Simultaneously, the inverted signal CLK_inb of the input clock signal CLK_in changes from low to high, and the voltage across the second capacitor C2 rises. Therefore, the second clock signal CLK1b changes from VCM-VDD to VCM. Finally, the first clock signal CLK1 and the second clock signal CLK1b become as follows: Figure 7 The signal shown is a square wave signal that alternates between a high level of the input common-mode voltage VCM and a low level of the voltage VCM-VDD.

[0055] Similarly, when the input clock signal CLK_in changes from low to high, the voltage of the third clock signal CLK2 rises to +VDD due to the boosting effect of the third capacitor C3. Meanwhile, the inverted signal CLK_inb of the input clock signal CLK_in changes from high to low, and through coupling with the fourth capacitor C4, the voltage of the fourth clock signal CLK2b drops to -VDD. Because the voltage of the third clock signal CLK2 rises and the voltage of the fourth clock signal CLK2b drops, the second NMOS transistor Mn2 turns on, the first NMOS transistor Mn1 turns off, and the potential of the fourth clock signal CLK2b is pulled low to the input common-mode voltage VCM. Since the potential of the third clock signal CLK2 in the previous state was VCM, after the input clock signal CLK_in changes from low to high, the potential of the third clock signal CLK2 becomes VCM + VDD. Similarly, when the input clock signal CLK_in changes from high to low, the third clock signal CLK2 changes from VCM+VDD to VCM, and the fourth clock signal CLK2b changes from VCM to VCM+VDD. Ultimately, the third clock signal CLK2 and the fourth clock signal CLK2b form complementary square wave signals with the input common-mode voltage VCM at a low level and VCM+VDD at a high level.

[0056] Furthermore, after obtaining two sets of complementary clock signals (i.e., the first clock signal CLK1 / the second clock signal CLK1b and the third clock signal CLK2 / the fourth clock signal CLK2b), the two sets of complementary clock signals are logically selected by the gating and combining module 330, ultimately obtaining the first driving clock signal CLKp and the second driving clock signal CLKn with an amplitude of 2*VDD. Specifically, when the input clock signal CLK_in changes from low level to high level, the voltage level of the first clock signal CLK1 is VCM, the voltage level of the second clock signal CLK1b is VCM-VDD, the voltage level of the third clock signal CLK2 is VCM+VDD, and the voltage level of the fourth clock signal CLK2b is VCM. At this time, the fourth NMOS transistor Mn4 and the third PMOS transistor Mp3 in the selection combination module 330 are turned on. The high level VCM+VDD of the third clock signal CLK2 is transmitted to the first drive clock signal CLKp through the third PMOS transistor Mp3, and the low level VCM-VDD of the second clock signal CLK1b is transmitted to the second drive clock signal CLKn through the fourth NMOS transistor Mn4. When the input clock signal CLK_in changes from high to low, the voltage level of the first clock signal CLK1 is VCM-VDD, the voltage level of the second clock signal CLK1b is VCM, the voltage level of the third clock signal CLK2 is VCM, and the voltage level of the fourth clock signal CLK2b is VCM+VDD. At this time, the third NMOS transistor Mn3 and the fourth PMOS transistor Mp4 in the selection combination module 330 are turned on. The low level VCM-VDD of the first clock signal CLK1 is transmitted to the first drive clock signal CLKp through the third NMOS transistor Mn3, and the high level VCM+VDD of the fourth clock signal CLK2b is transmitted to the second drive clock signal CLKn through the fourth PMOS transistor Mp4. As a result, the first drive clock signal CLKp and the second drive clock signal CLKn always maintain a complementary swing with an amplitude of 2*VDD, and the switching point precisely corresponds to the flip edge of the input clock, realizing a high-efficiency, low-jitter clock drive output.

[0057] Figure 8 This diagram illustrates a schematic structural diagram of a chopper according to an embodiment of the present invention. Figure 9 and Figure 10 The diagrams show the signal transmission paths of the chopper under two transmission states according to embodiments of the present invention. Figure 8 As shown, the chopper 400 in this embodiment includes a chopper switch circuit 100 and a drive circuit 300 as described in the previous embodiment.

[0058] The chopper switch circuit 100 includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first terminals of the first switch S1 and the second switch S2 are connected to the positive input terminal Vinp, the second terminal of the first switch S1 is connected to the positive output terminal Voutp, the second terminal of the second switch S2 is connected to the negative output terminal Voutn, the first terminals of the third switch S3 and the fourth switch S4 are connected to the negative input terminal Vinn, the second terminal of the third switch S3 is connected to the positive output terminal Voutp, and the second terminal of the fourth switch S4 is connected to the negative output terminal Voutn. When the first switch S1 and the fourth switch S4 are on, and the second switch S2 and the third switch S3 are off, the positive input terminal Vinp of the chopper switch circuit 100 is connected to the positive output terminal Voutp, and the negative input terminal Vinn is connected to the negative output terminal Voutn. The signals from the positive and negative input terminals are directly transmitted to the positive and negative output terminals Voutp and Voutn, respectively. When the second switch S2 and the third switch S3 are on, and the first switch S1 and the fourth switch S4 are off, the positive input terminal Vinp of the chopper switch circuit 100 is connected to the negative output terminal Voutn, and the negative input terminal Vinn is connected to the positive output terminal Voutp. The signals from the positive and negative input terminals are transmitted to the negative and positive output terminals Voutp in a cross-transmission manner. By periodically switching the switch combination states, chopping modulation of the input signal can be achieved, effectively suppressing DC offset and low-frequency noise.

[0059] For example, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 in the chopper switch circuit 100 can be constructed from MOS transistors, and their on / off states are controlled by a driving clock pair. Further, this driving clock pair includes a complementary first driving clock signal CLKp and a second driving clock signal CLKn. The first driving clock signal CLKp is used to periodically control the on / off states of the first switch S1 and the fourth switch S4, and the second driving clock signal CLKn is used to periodically control the on / off states of the second switch S2 and the third switch S3, thereby achieving periodic reversal of the input signal. Further, the first switch S1 to the fourth switch S4 can be implemented using NMOS transistors, with the gates of the first switch S1 and the fourth switch S4 connected to the first driving clock signal CLKp, and the gates of the second switch S2 and the third switch S3 connected to the second driving clock signal CLKn. When the first driving clock signal CLKp is high, the first switch S1 and the fourth switch S4 are turned on, and the second driving clock signal CLKn is low, and the second switch S2 and the third switch S3 are turned off; when the second driving clock signal CLKn is high, the second switch S2 and the third switch S3 are turned on, and the first driving clock signal CLKp is low, and the first switch S1 and the fourth switch S4 are turned off.

[0060] Furthermore, the drive circuit 300 is used to provide the chopper switch circuit 100 with a first drive clock signal CLKp and a second drive clock signal CLKn with a larger voltage swing, to ensure that the chopper first switch S1 to the fourth switch S4 can be fully turned on and off during signal transmission, to avoid leakage current, and to improve the integrity of signal transmission and system reliability.

[0061] exist Figure 9 and Figure 10 In the example, with a power supply voltage VDD of 2.5V and an input differential voltage of 1V, the positive input voltage Vinp of the chopper switch circuit 100 is VCM+0.5V, and the negative input voltage Vinn is VCM-0.5V.

[0062] like Figure 9 As shown, when the first driving clock signal CLKp is high (VCM+2.5V), the second driving clock signal CLKn is low (VCM-2.5V). At this time, the first switch S1 and the fourth switch S4 are turned on. The signal at the positive input terminal Vinp is transmitted to the positive output terminal Voutp through the first switch S1, and the signal at the negative input terminal Vinn is transmitted to the negative output terminal Voutn through the fourth switch S4, realizing direct signal transmission. Simultaneously, since the gate voltages of the second switch S2 and the third switch S3 are VCM-2.5V, the gate-source voltages of both switches S2 and S3 are less than the threshold voltage, ensuring reliable turn-off and avoiding signal crosstalk.

[0063] Similarly, such as Figure 10 As shown, when the second driving clock signal CLKn is high (VCM+2.5V), the first driving clock signal CLKp is low (VCM-2.5V). At this time, the second switch S2 and the third switch S3 are turned on. The signal at the positive input terminal Vinp is transmitted to the negative output terminal Voutn through the second switch S2, and the signal at the negative input terminal Vinn is transmitted to the positive output terminal Voutp through the third switch S3, realizing the cross-transmission of input signals. At the same time, since the gate voltage of the first switch S1 and the fourth switch S4 is VCM-2.5V, their gate-source voltage is also lower than the threshold voltage, ensuring that the first switch S1 and the fourth switch S4 are reliably turned off, preventing signal backflow and interference.

[0064] In summary, the driving circuit for the chopper switch circuit provided in this embodiment of the invention obtains a first pair of complementary clock signals and a second pair of complementary clock signals based on the input common-mode voltage of the chopper switch circuit through a first level shifting module and a second level shifting module, respectively. The low level of the first pair of complementary clock signals is lower than the input common-mode voltage, and the high level of the second pair of complementary clock signals is higher than the input common-mode voltage. Then, through a gating and combining module, the low level of the first pair of complementary clock signals and the high level of the second pair of complementary clock signals are alternately transmitted to the driving clock output terminal in the same cycle, thereby synthesizing a driving clock pair with a larger voltage swing. When the driving clock is directly applied to the gate of the all-NMOS chopper switch circuit, the gate-source voltage of the on-side switch is sufficiently higher than its threshold voltage, and the gate-source voltage of the off-side switch is significantly lower than its threshold voltage. This allows for reliable switching on and off even when the input differential voltage of the chopper switch circuit is large or even close to the power supply voltage. This effectively avoids the generation of high-temperature leakage paths and ensures that the signal can be transmitted stably and correctly in both high and low temperature environments, thereby improving the chopper's operational reliability and signal integrity over a wide temperature range.

[0065] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0066] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A driving circuit for a chopper switch circuit, comprising: The first level shifting module is used to obtain a first pair of complementary clock signals based on the input common-mode voltage of the chopper switch circuit, wherein the low level of the first pair of complementary clock signals is lower than the input common-mode voltage; The second level shifting module is used to obtain a second pair of complementary clock signals based on the input common-mode voltage, wherein the high level of the second pair of complementary clock signals is higher than the input common-mode voltage. as well as The gating and combining module is used to selectively and alternately transmit the low level of the first pair of complementary clock signals and the high level of the second pair of complementary clock signals to the output terminal within the same cycle, so as to generate a drive clock pair for application to the chopper switching circuit at the output terminal, wherein the high level of the drive clock pair is higher than the input common-mode voltage and the low level is lower than the input common-mode voltage. The first level shifting module includes: The first capacitor has its first terminal used to connect to the input clock signal; The second capacitor has its first terminal connected to the inverted signal of the input clock signal; A first transistor having a first conductivity type, wherein a first terminal is connected to the input common-mode voltage and a second terminal is connected to the second terminal of the first capacitor; and A second transistor having the first conductivity type has its first terminal connected to the input common-mode voltage, its control terminal connected to the second terminal of the first transistor and the second terminal of the first capacitor, and its second terminal connected to the control terminal of the first transistor and the second terminal of the second capacitor. Wherein, the second terminals of the first transistor and the second transistor serve as the output terminals of the first pair of complementary clock signals; The second level shifting module includes: The third capacitor has its first terminal connected to the input clock signal; The fourth capacitor has its first terminal connected to the inverted signal of the input clock signal; A third transistor having a second conductivity type, its first terminal connected to the second terminal of the third capacitor, and its second terminal connected to the input common-mode voltage; and A fourth transistor having the second conductivity type has its first terminal connected to the second terminal of the fourth capacitor and the control terminal of the third transistor, its control terminal connected to the second terminal of the third transistor and the second terminal of the third capacitor, and its second terminal connected to the input common-mode voltage. The first terminals of the third transistor and the fourth transistor serve as the output terminals of the second pair of complementary clock signals.

2. The driving circuit according to claim 1, wherein, The high level of the driving clock pair is equal to the sum of the input common-mode voltage and the power supply voltage, and the low level of the driving clock pair is equal to the voltage difference between the input common-mode voltage and the power supply voltage.

3. The driving circuit according to claim 2, wherein, The gating and combination module includes: A fifth transistor and a sixth transistor having the second conductivity type, the second terminal of the fifth transistor being connected to one of the first pair of complementary clock signals, the first terminal of the fifth transistor being connected to the first output terminal of the driving clock pair, the second terminal of the sixth transistor being connected to the other of the first pair of complementary clock signals, and the first terminal of the sixth transistor being connected to the second output terminal of the driving clock pair; and A seventh transistor and an eighth transistor having the first conductivity type, wherein the first terminal of the seventh transistor is connected to one of the second pair of complementary clock signals, and its second terminal is connected to the first output terminal of the driving clock pair; and the first terminal of the eighth transistor is connected to the other of the second pair of complementary clock signals, and its second terminal is connected to the second output terminal of the driving clock pair. The control terminals of the fifth to eighth transistors are all connected to the input common-mode voltage.

4. The driving circuit according to claim 3, wherein, The first conductivity type is P-type, and the second conductivity type is N-type.

5. The driving circuit according to claim 2, wherein, The input clock signal has a voltage level range of 0V to the power supply voltage.

6. The driving circuit according to claim 5, wherein, Also includes: A first inverter is used to generate the input clock signal based on the initial clock signal; as well as The second inverter is used to generate an inverted signal of the input clock signal based on the input clock signal. The power supply terminals of the first inverter and the second inverter are connected to the power supply voltage, so that the level range of the input clock signal and its inverted signal is from 0V to the power supply voltage.

7. A chopper, comprising: Chopper switch circuit; as well as The driving circuit according to any one of claims 1-6 is used to generate a driving clock signal to control the on and off of the chopper switch circuit, thereby realizing the periodic reversal of the input signal.

Images