An instruction fetch module and related apparatus

Abstract

This invention proposes an instruction fetch module and related devices. The microcode output unit generates a first type of microcode when the first N pre-decoding slots contain at least one valid instruction, and generates a second type of microcode when the cache unit is not empty. Following a priority rule for the second type of microcode, the target microcode is determined from all first and second type microcodes and output through the corresponding microcode output channel. After sending the target microcode, the cache unit caches the remaining valid instructions in the pre-decoding unit into the corresponding free entries. When the cache unit is empty, the instructions in the pre-decoding unit can be directly bypassed and output through the microcode output unit without needing to cache through entries, thereby reducing pipeline depth and improving processor performance. Simultaneously, the instruction fetch module also includes a cache unit to address the bandwidth mismatch between the instruction fetch and decoding modules, achieving data decoupling between them.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to an instruction fetching module and related equipment. Background Technology

[0002] In recent years, whether in the high-end consumer electronics sector or the server field, more powerful processor cores have become a core competitive advantage for major chip companies. High-performance processor cores primarily possess two characteristics: out-of-order execution and superscalar execution. These processor cores mainly consist of the following components: branch prediction module, instruction fetch module, decoding module, renaming module, dispatch module, issue module, execution module, memory access module, and reordering module. Most high-performance processor cores also include floating-point and vector execution modules. Typically, high-performance processors operate at frequencies above 2 GHz and have superscalar widths greater than 4.

[0003] In classic microarchitecture designs based on reduced instruction set computing (RISC) high-performance processor cores, the bandwidth of the fetch module is slightly greater than that of the decode module for performance reasons. To address this bandwidth mismatch, an instruction queue is added at the last stage of the fetch module to decouple the fetch and decode modules. However, in typical designs, the instruction queue is only used for instruction caching. When complex instructions require instruction decomposition, additional pipeline stages are needed, increasing the overall pipeline depth and reducing processor performance. Summary of the Invention

[0004] The purpose of this invention is to provide an instruction fetching module and related equipment to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, embodiments of the present invention provide an instruction fetching module, the instruction fetching module comprising: a pre-decoding unit, a buffer unit, and a microcode output unit, wherein the pre-decoding unit is provided with M pre-decoding slots, the microcode output unit is provided with N microcode output channels, and the buffer unit is provided with G entries, where N≤M≤G;

[0007] When the first N pre-decoding slots include at least one valid instruction, the microcode output unit is used to generate no more than N first-class microcodes based on the valid instructions in the first N pre-decoding slots and the pre-decoding information corresponding to the instructions.

[0008] When the cache unit is not empty, the microcode output unit is used to generate no more than N second-type microcodes based on the valid instructions in the cache unit and the pre-decoding information corresponding to the instructions;

[0009] The microcode output unit is used to determine no more than N target microcodes from all first-class and second-class microcodes according to the second-class microcode priority rule, and output the target microcodes through the corresponding microcode output channel.

[0010] After the target microcode is sent, if the number of free entries in the cache unit is greater than the number of remaining valid instructions in the pre-decoding unit, the cache unit is used to cache the remaining valid instructions in the pre-decoding unit into the corresponding free entries.

[0011] Optionally, the microcode output unit includes a bypass splitter, a queue splitter, and a microcode selector;

[0012] The output of the nth pre-decoding slot is connected to the nth input of the bypass splitter, and the nth output of the bypass splitter is connected to the nth input of the microcode selector, 1≤n≤N;

[0013] The nth input of the queue splitter is connected to the buffer unit, and the nth output of the queue splitter is connected to the N+nth input of the microcode selector.

[0014] When the first N pre-decoding slots include at least one valid instruction, the bypass splitter is used to generate no more than N first-class microcodes based on the valid instructions in the first N pre-decoding slots and the pre-decoding information corresponding to the instructions;

[0015] When the cache unit is not empty, the queue splitter is used to generate no more than N second-type microcodes based on the first N valid instructions in the cache unit and the pre-decoding information corresponding to the instructions;

[0016] The microcode selector is used to determine no more than N target microcodes from all first-class and second-class microcodes according to the second-class microcode priority rule, and output the target microcodes through the corresponding microcode output channel.

[0017] Optionally, the pre-decoding information includes an identifier indicating whether the instruction needs to be split, and the number of split targets corresponding to when the instruction needs to be split;

[0018] When the first N pre-decoding slots include at least one valid instruction, the bypass splitter is used to determine whether the instruction in the i-th pre-decoding slot needs to be split. If it does not need to be split, a first-type microcode corresponding to the instruction in the i-th pre-decoding slot is generated. If it needs to be split, it is determined whether Ri < Q1 is true. If Ri ≥ Q1, Q1 first-type microcodes corresponding to the instruction in the i-th pre-decoding slot are generated. If Ri < Q1, Ri first-type microcodes corresponding to the instruction in the i-th pre-decoding slot are generated, and i = i + 1 is set. If the instruction in the i-th pre-decoding slot is valid, the determination of whether the instruction in the i-th pre-decoding slot needs to be split is repeated.

[0019] Where Ri represents the number of split targets corresponding to the instruction in the i-th pre-decoding slot, 1≤i≤N, and Q1 represents the remaining number of microcodes that can be generated for the first type.

[0020] Optionally, the pre-decoding information includes an identifier indicating whether the instruction needs to be split, and the number of split targets corresponding to when the instruction needs to be split;

[0021] When the cache unit is not empty, the queue splitter is used to determine whether the instruction in the first target entry needs to be split. If it does not need to be split, a second type microcode corresponding to the instruction in the first target entry is generated. If it needs to be split, it determines whether S1 < N is true. If S1 ≥ N, N second type microcodes corresponding to the instruction in the first target entry are generated.

[0022] If S1 < N, the queue splitter generates S1 second-type microcodes corresponding to the instruction in the first target entry, determines whether the instruction in the j-th target entry needs to be split, and if not, generates one second-type microcode corresponding to the instruction in the j-th target entry; if splitting is required, it determines whether Rj < Q2 is true. If Rj ≥ Q2, it generates Q2 second-type microcodes corresponding to the instruction in the j-th target entry; if Rj < Q2, it generates Rj second-type microcodes corresponding to the instruction in the j-th target entry, and sets j = j + 1, and repeats the determination of whether the instruction in the j-th target entry needs to be split.

[0023] Wherein, the first target entry is the first valid entry indicated by the read pointer in the cache unit, the j-th target entry is the j-th valid entry counted from the entry indicated by the read pointer in the cache unit, 2≤j≤N, S1 is the difference between the number of split targets corresponding to the instruction in the first target entry and the number of microcodes already output, Rj represents the number of split targets corresponding to the instruction in the j-th target entry, and Q2 represents the remaining number of microcodes that can be generated for the second type.

[0024] Optionally, the instruction fetch module is further provided with a register, which is connected to the queue splitter, and the register is used to store S1;

[0025] When the cache unit is not empty, the queue splitter is used to determine the number of output microcodes of the instruction corresponding to the Nth type of microcode, and subtract the number of output microcodes of the instruction corresponding to the Nth type of microcode from the target number of splitting instructions corresponding to the Nth type of microcode to obtain the next step S1, and write it into the register.

[0026] Optionally, when N target microcodes include k type 1 microcodes, the microcode output unit is used to determine whether the Kth instruction corresponding to the Kth type 1 microcode needs to be split. If the Kth instruction does not need to be split, the identifier of the (K+1)th pre-decoding slot is sent to the cache unit as the cache start pre-decoding slot identifier.

[0027] When the Kth instruction needs to be split, the microcode output unit checks whether the number of bypassed microcodes corresponding to the Kth instruction reaches the split target number corresponding to the Kth instruction. If yes, the identifier of the (K+1)th pre-decoding slot is sent to the cache unit as the cache start pre-decoding slot identifier. If no, the identifier of the Kth pre-decoding slot is sent to the cache unit as the cache start pre-decoding slot identifier.

[0028] The cache unit is used to cache the valid instructions stored in the first pre-decoding slot to the Mth pre-decoding slot as the remaining valid instructions in the pre-decoding unit.

[0029] Optionally, the buffer unit further includes an input selector and an output selector;

[0030] The output of the m-th pre-decoding slot is connected to the m-th input of the input selector, where 1 ≤ m ≤ M;

[0031] The g-th output of the input selector is connected to the input of the g-th entry, the output of the g-th entry is connected to the g-th input of the output selector, and the n-th output of the output selector is connected to the n-th input of the queue splitter.

[0032] Optionally, the microcode output unit is also connected to the input selector, and the microcode output unit is also connected to the output selector;

[0033] The input selector is used to determine whether the number of free entries in the cache unit is greater than or equal to the number of remaining valid instructions in the pre-decoding unit after receiving the cache start pre-decoding slot identifier sent by the microcode output unit. If so, the valid instructions stored in the cache start pre-decoding slot to the Mth pre-decoding slot are written into the corresponding entries.

[0034] The output selector is used to transmit the instructions from the N valid entries that start counting from the entry indicated by the read pointer in the cache unit to the queue splitter.

[0035] Secondly, embodiments of the present invention provide a processor, the processor including the instruction fetch module described above.

[0036] Thirdly, embodiments of the present invention provide an electronic device including the processor described above.

[0037] Compared to existing technologies, the instruction fetch module and related devices provided in this invention, when the first N pre-decoding slots include at least one valid instruction, generate no more than N first-type microcodes based on the valid instructions in the first N pre-decoding slots and the corresponding pre-decoding information. When the cache unit is not empty, the microcode output unit generates no more than N second-type microcodes based on the valid instructions in the cache unit and the corresponding pre-decoding information. The microcode output unit determines no more than N target microcodes from all first-type and second-type microcodes according to the second-type microcode priority rule, and outputs the target microcodes through the corresponding microcode output channel. After the target microcode is sent, if the number of free entries in the cache unit is greater than the number of remaining valid instructions in the pre-decoding unit, the cache unit caches the remaining valid instructions in the pre-decoding unit to the corresponding free entries. When the cache unit is empty, the instructions in the pre-decoding unit can be directly bypassed and output through the microcode output unit without caching through entries, thereby reducing pipeline depth and improving processor performance. Meanwhile, the instruction fetch module is also equipped with a cache unit to solve the problem of bandwidth mismatch between the instruction fetch module and the decoding module, thereby achieving data decoupling between the instruction fetch module and the decoding module.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is one of the structural schematic diagrams of the instruction fetching module provided in an embodiment of the present invention.

[0041] Figure 2 This is a second schematic diagram of the instruction fetching module provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0044] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0046] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0047] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0048] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0049] Please refer to Figure 1 , Figure 1 This is one of the structural schematic diagrams of the instruction fetch module provided in an embodiment of the present invention. The instruction fetch module includes a pre-decoding unit, a buffer unit, and a microcode output unit. The pre-decoding unit has M pre-decoding slots, the microcode output unit has N microcode output channels, and the buffer unit has G entries, where N ≤ M ≤ G. The outputs of the first N pre-decoding slots are connected to the microcode output unit, and the outputs of the M pre-decoding slots are all connected to the buffer unit. The buffer unit is also connected to the microcode output unit. The value of N can be, but is not limited to, 5, and can also be 6 or 8; the value of M can be, but is not limited to, 8, and can also be 6 or 8; the value of G can be, but is not limited to, 18, and can also be any one of 14, 15, 16, 19, and 20.

[0050] When the first N pre-decoding slots (in the pre-decoding unit) contain at least one valid instruction, the microcode output unit generates no more than N first-type microcodes based on the valid instructions in the first N pre-decoding slots and the corresponding pre-decoding information. The pre-decoding information includes whether the instruction needs to be split, and if splitting is required, the number of splitting targets corresponding to the instruction.

[0051] When the cache unit is not empty, the microcode output unit is used to generate no more than N second-type microcodes based on the valid instructions in the cache unit and the pre-decoding information corresponding to the instructions.

[0052] Not all entries in a cache unit are in an empty state. A cache unit is not empty if it contains at least one entry that is in an occupied state. An occupied entry means that it stores a valid instruction.

[0053] Optionally, the microcode output unit is used to generate no more than N second-type microcode based on the first N valid instructions in the cache unit and the corresponding pre-decoding information. It should be understood that when the number of valid instructions in the cache unit is less than N, there may be cases where the number of second-type microcode generated is less than N. Here, the first N valid instructions in the cache unit are the first N instructions sorted according to the time they were written into the cache unit, and can be pointed to by the read pointer in the cache unit as the first instruction sorted according to the time it was written into the cache unit.

[0054] The microcode output unit is used to determine no more than N target microcodes from all first-class and second-class microcodes according to the second-class microcode priority rule, and output the target microcodes through the corresponding microcode output channel.

[0055] The second type of microcode priority rule means that when the number of second type microcodes is N, all second type microcodes are used as target microcodes, and first type microcodes are not sent. When the number of second type microcodes is less than N, all second type microcodes and the first X first type microcodes are used as target microcodes, where X is the difference between N and the number of second type microcodes. In this case, the remaining first type microcodes will not be sent. If the number of first type microcodes is less than X, then all second type microcodes and all first type microcodes are used as target microcodes.

[0056] It should be understood that when the number of microcode transmissions corresponding to valid instructions in the cache unit reaches its corresponding splitting target number, the instruction can be marked as invalid. This can be done by marking the state of the entry storing the instruction as invalid and moving the read pointer corresponding to the entry. In the next clock cycle, the instruction in the entry will not be read for microcode splitting. When the number of microcode transmissions corresponding to valid instructions in the pre-decoding slot reaches its corresponding splitting target number, the pre-decoding slot can be marked as invalid, and the instructions in it are invalid. After the target microcode is transmitted, it is not necessary to move the instructions in the invalid pre-decoding slot to the free entry.

[0057] After the target microcode is sent, if the number of free entries in the cache unit is greater than the number of remaining valid instructions in the pre-decoding unit, the cache unit is used to cache the remaining valid instructions in the pre-decoding unit into the corresponding free entries.

[0058] Among them, the remaining valid instructions in the pre-decoding unit are the instructions that have not been bypassed and output. If an instruction has not been completely split, it is also considered that it has not been successfully bypassed and output, and it still needs to be stored in the cache unit.

[0059] In the instruction fetch module provided in this embodiment of the invention, when the cache unit is empty, the instructions in the pre-decoding unit can be directly bypassed and output through the microcode output unit without needing to cache through entries, thereby reducing pipeline depth and improving processor performance. Simultaneously, the instruction fetch module also includes a cache unit to address the bandwidth mismatch between the instruction fetch module and the decoding module, achieving data decoupling between the two modules.

[0060] Building upon the foregoing, this embodiment of the invention also provides an optional implementation method for the specific structure of the microcode output unit. Please refer to [link / reference needed]. Figure 2 , Figure 2 This is a second schematic diagram of the instruction fetching module provided in an embodiment of the present invention. The microcode output unit includes a bypass splitter, a queue splitter, and a microcode selector.

[0061] The output of the nth pre-decoding slot is connected to the nth input of the bypass splitter, and the nth output of the bypass splitter is connected to the nth input of the microcode selector, where 1 ≤ n ≤ N.

[0062] The nth input of the queue splitter is connected to the buffer unit, the nth output of the queue splitter is connected to the N+nth input of the microcode selector, and the N output channels of the microcode selector serve as the microcode output channels of the microcode output unit.

[0063] When the first N pre-decoding slots contain at least one valid instruction, the bypass splitter is used to generate no more than N first-class microcodes based on the valid instructions in the first N pre-decoding slots and the pre-decoding information corresponding to the instructions.

[0064] When the cache unit is not empty, the queue splitter is used to generate no more than N second-type microcodes based on the first N valid instructions in the cache unit and the pre-decoding information corresponding to the instructions.

[0065] The microcode selector is used to determine no more than N target microcodes from all first-class and second-class microcodes according to the second-class microcode priority rule, and output the target microcodes through the corresponding microcode output channel.

[0066] Optionally, the pre-decoding information includes an identifier indicating whether the instruction needs to be split, and the number of split targets when the instruction needs to be split.

[0067] When the first N pre-decoding slots contain at least one valid instruction, the bypass splitter is used to determine whether the instruction in the i-th pre-decoding slot needs to be split. If it does not need to be split, a first-class microcode corresponding to the instruction in the i-th pre-decoding slot is generated. It is then determined whether Q1 is 0. If it is 0, the process ends. If it is not 0, i is set to i+1. If the instruction in the i-th pre-decoding slot is valid, the process of determining whether the instruction in the i-th pre-decoding slot needs to be split is repeated.

[0068] If the instruction in the i-th pre-decoding slot needs to be split, the bypass splitter is used to determine whether Ri < Q1 is true. If Ri ≥ Q1, then Q1 Type I microcodes corresponding to the instruction in the i-th pre-decoding slot are generated (at this point, N Type I microcodes have already been generated, and there is no need to continue splitting the subsequent instructions; the bypass splitter stops generating Type I microcodes in the current cycle). If Ri < Q1, then Ri Type I microcodes corresponding to the instruction in the i-th pre-decoding slot are generated, and i = i + 1 is set. If the instruction in the i-th pre-decoding slot is valid, the determination of whether the instruction in the i-th pre-decoding slot needs to be split is repeated.

[0069] Where Ri represents the number of split targets corresponding to the instruction in the i-th pre-decoding slot, 1≤i≤N, and Q1 represents the remaining number of type I microcodes that can be generated, which is equal to N minus the number of type I microcodes already generated in the current batch. The initial value of i is 1, and the maximum value of i is N. Even if all instructions in the first N pre-decoding slots do not need to be split, N type I microcodes can still be obtained when i=N.

[0070] Optionally, after setting i=i+1, it is determined whether the instruction in the i-th pre-decoding slot is valid. If the instruction in the i-th pre-decoding slot is invalid, then only this many Type I microcodes are allowed, and the bypass splitter stops generating Type I microcodes in the current cycle.

[0071] Optionally, the pre-decoding information includes an identifier indicating whether the instruction needs to be split, and the number of split targets when the instruction needs to be split;

[0072] When the cache unit is not empty (the read pointer and write pointer in the cache unit do not coincide), the queue splitter is used to determine whether the instruction in the first target entry needs to be split. If it does not need to be split, a second type microcode corresponding to the instruction in the first target entry is generated. If it needs to be split, it determines whether S1 < N is true. If S1 ≥ N, N second type microcodes corresponding to the instruction in the first target entry are generated. At this time, N second type microcodes have been generated, and it is not necessary to continue splitting the subsequent instructions. The queue splitter stops generating second type microcodes in the current cycle.

[0073] If S1 < N, the queue splitter generates S1 second-type microcodes corresponding to the instruction in the first target entry, determines whether the instruction in the j-th target entry needs to be split, and if not, generates a second-type microcode corresponding to the instruction in the j-th target entry, checks whether Q2 is 0, ends if it is 0, and ends if it is not 0, then sets j = j + 1 and repeats the determination of whether the instruction in the j-th target entry needs to be split.

[0074] If the instruction in the j-th target entry needs to be split, the queue splitter is used to determine whether Rj < Q2 is true. If Rj ≥ Q2, then Q2 second-type microcodes corresponding to the instruction in the j-th target entry are generated (at this point, N second-type microcodes have already been generated, and there is no need to continue splitting the subsequent instructions; the queue splitter stops generating second-type microcodes in the current cycle). If Rj < Q2, then Rj second-type microcodes corresponding to the instruction in the j-th target entry are generated, and j = j + 1 is set, and the determination of whether the instruction in the j-th target entry needs to be split is repeated.

[0075] It should be understood that the maximum value of j is N. Even if all instructions in N target entries do not need to be split, N Type II microcodes can still be obtained when j=N.

[0076] Wherein, the first target entry is the first valid entry indicated by the read pointer in the cache unit, the j-th target entry is the j-th valid entry counted from the entry indicated by the read pointer in the cache unit, 2≤j≤N, when the total number of valid entries in the cache unit is less than or equal to N, j≤ the total number of valid entries in the cache unit, after j= the total number of valid entries in the cache unit, if N second-type microcodes are still not generated, then no more second-type microcodes will be generated, that is, the number of second-type microcodes is less than N, S1 is the difference between the number of split targets corresponding to the instruction in the first target entry and the number of output microcodes corresponding to it (the instruction in the first target entry), Rj represents the number of split targets corresponding to the instruction in the j-th target entry, Q2 represents the remaining number of second-type microcodes that can be generated, which is equal to N minus the number of second-type microcodes generated in the current batch.

[0077] The queue splitter controls the read pointer to point to the entry corresponding to the last instruction of the second type of microcode when S1 is not 0, and controls the read pointer to point to the next entry corresponding to the last instruction of the second type of microcode when S1 is 0. Specifically, the queue splitter sends a read pointer adjustment instruction to the output selector in the buffer unit to achieve the above read pointer control.

[0078] Optionally, the instruction fetch module is also provided with a register connected to the queue splitter (and bypass splitter), and the register is used to store S1.

[0079] When the cache unit is not empty, the queue splitter is used to determine the number of output microcodes of the instruction corresponding to the Nth type 2 microcode (that is, the instruction in the first target entry of the next cycle), and subtract the number of output microcodes of the instruction corresponding to the Nth type 2 microcode from the number of split targets of the instruction corresponding to the Nth type 2 microcode to obtain S1 of the next cycle, and write it into the register.

[0080] Optionally, when the N target microcodes include k type 1 microcodes, the microcode output unit (which may be a bypass splitter) is used to determine whether the Kth instruction corresponding to the kth type 1 microcode needs to be split. If the Kth instruction does not need to be split (at this time, the microcode corresponding to the Kth instruction has been sent, and the Kth instruction does not need to be cached, K≤N), then the identifier of the (K+1)th pre-decoding slot (the pre-decoding slot storing the K+1th instruction) is sent to the cache unit (which may be sent to the input selector in the cache unit) as the cache start pre-decoding slot identifier.

[0081] When the Kth instruction needs to be split, the microcode output unit (which may be a bypass splitter) checks whether the number of bypassed microcodes corresponding to the Kth instruction reaches the splitting target number corresponding to the Kth instruction (i.e., whether the kth type I microcode is the last microcode corresponding to the Kth instruction). If yes, the identifier of the (K+1)th pre-decoding slot (the pre-decoding slot storing the (K+1)th instruction) is sent to the cache unit (which may be sent to the input selector in the cache unit) as the cache start pre-decoding slot identifier. If no, the identifier of the Kth pre-decoding slot (the pre-decoding slot storing the Kth instruction) is sent to the cache unit (which may be sent to the input selector in the cache unit) as the cache start pre-decoding slot identifier.

[0082] If the number of bypassed microcodes corresponding to the Kth instruction does not reach the split target number corresponding to the Kth instruction, the instruction in the Kth pre-decode slot will be written as the first entry indicated by the write pointer of the cache unit (the read pointer also points to this entry). At this time, the cache unit (bypass splitter) will write the difference between the split target number corresponding to the Kth instruction and the number of bypassed microcodes corresponding to the Kth instruction into the register as the new S1.

[0083] The cache unit is used to cache the valid instructions stored in the first pre-decoding slot (e.g., the Kth or K+1th pre-decoding slot) to the Mth pre-decoding slot, as the remaining valid instructions in the pre-decoding unit.

[0084] The cache unit can update its corresponding write pointer after caching the remaining valid instructions in the pre-decoding unit to the corresponding free entry.

[0085] When N target microcodes include 0 type 1 microcodes, the microcode output unit (which may be one of the bypass splitters) sends the identifier of the first pre-decode slot (the pre-decode slot storing the first instruction) to the cache unit as the cache start pre-decode slot identifier.

[0086] Please continue to refer to this. Figure 2 In one alternative implementation, the buffer unit further includes an input selector and an output selector.

[0087] The output of the m-th pre-decoding slot is connected to the m-th input of the input selector, 1≤m≤M; the g-th output of the input selector is connected to the input of the g-th entry, the output of the g-th entry is connected to the g-th input of the output selector, and the n-th output of the output selector is connected to the n-th input of the queue splitter.

[0088] The microcode output unit (including the bypass splitter) is also connected to the input selector, and the microcode output unit (including the queue splitter) is also connected to the output selector.

[0089] The input selector is used to determine whether the number of free entries in the cache unit is greater than or equal to the number of remaining valid instructions in the pre-decoding unit after receiving the cache start pre-decoding slot identifier sent by the microcode output unit (bypass splitter). If so, the valid instructions stored in the cache start pre-decoding slot (e.g., the Kth or K+1th pre-decoding slot) to the Mth pre-decoding slot are written into the corresponding entries.

[0090] When writing instructions to a cache unit, you can start writing from the first entry indicated by the write pointer and continue until all entries are written. If the number of free entries in the cache unit is less than the number of remaining valid instructions in the pre-decode unit, wait for the next clock cycle and re-evaluate the process.

[0091] The output selector is used to transmit the instructions from the N valid entries starting from the entry indicated by the read pointer in the cache unit to the queue splitter, so that it can generate the corresponding second type of microcode.

[0092] It should be understood that the input selector can switch the continuity between its input and output terminals to connect the pre-decode slot to different entries, and the output selector can switch the continuity between its input and output terminals to connect different entries to the queue splitter.

[0093] This invention also provides a processor, which includes the instruction fetch module described above.

[0094] This invention also provides an electronic device including the processor described above.

[0095] In summary, the instruction fetch module and related device provided in this embodiment of the invention, when the first N pre-decoding slots include at least one valid instruction, generates no more than N first-type microcodes based on the valid instructions in the first N pre-decoding slots and the corresponding pre-decoding information. When the cache unit is not empty, the microcode output unit generates no more than N second-type microcodes based on the valid instructions in the cache unit and the corresponding pre-decoding information. The microcode output unit determines no more than N target microcodes from all first-type and second-type microcodes according to the second-type microcode priority rule, and outputs the target microcodes through the corresponding microcode output channel. After the target microcode is sent, if the number of free entries in the cache unit is greater than the number of remaining valid instructions in the pre-decoding unit, the cache unit caches the remaining valid instructions in the pre-decoding unit to the corresponding free entries. When the cache unit is empty, the instructions in the pre-decoding unit can be directly bypassed and output through the microcode output unit without caching through entries, thereby reducing pipeline depth and improving processor performance. Meanwhile, the instruction fetch module is also equipped with a cache unit to solve the problem of bandwidth mismatch between the instruction fetch module and the decoding module, thereby achieving data decoupling between the instruction fetch module and the decoding module.

[0096] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0097] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. An instruction fetching module, characterized in that, The instruction fetching module includes: a pre-decoding unit, a buffer unit, and a microcode output unit. The pre-decoding unit has M pre-decoding slots, the microcode output unit has N microcode output channels, and the buffer unit has G entries, where N≤M≤G. When the first N pre-decoding slots include at least one valid instruction, the microcode output unit is used to generate no more than N first-class microcodes based on the valid instructions in the first N pre-decoding slots and the pre-decoding information corresponding to the instructions. When the cache unit is not empty, the microcode output unit is used to generate no more than N second-type microcodes based on the valid instructions in the cache unit and the pre-decoding information corresponding to the instructions; The microcode output unit is used to determine no more than N target microcodes from all first-class and second-class microcodes according to the second type of microcode priority rule, and output the target microcodes through the corresponding microcode output channel. The second type of microcode priority rule means that: when the number of second-class microcodes is N, all second-class microcodes are used as target microcodes; when the number of second-class microcodes is less than N, all second-class microcodes and the first X first-class microcodes are used as target microcodes, where X is the difference between N and the number of second-class microcodes; if the number of first-class microcodes is less than X, then all second-class microcodes and all first-class microcodes are used as target microcodes. After the target microcode is sent, if the number of free entries in the cache unit is greater than the number of remaining valid instructions in the pre-decoding unit, the cache unit is used to cache the remaining valid instructions in the pre-decoding unit into the corresponding free entries.

2. The instruction fetching module as described in claim 1, characterized in that, The microcode output unit includes a bypass splitter, a queue splitter, and a microcode selector; The output of the nth pre-decoding slot is connected to the nth input of the bypass splitter, and the nth output of the bypass splitter is connected to the nth input of the microcode selector, 1≤n≤N; The nth input of the queue splitter is connected to the buffer unit, and the nth output of the queue splitter is connected to the N+nth input of the microcode selector. When the first N pre-decoding slots include at least one valid instruction, the bypass splitter is used to generate no more than N first-class microcodes based on the valid instructions in the first N pre-decoding slots and the pre-decoding information corresponding to the instructions; When the cache unit is not empty, the queue splitter is used to generate no more than N second-type microcodes based on the first N valid instructions in the cache unit and the pre-decoding information corresponding to the instructions; The microcode selector is used to determine no more than N target microcodes from all first-class and second-class microcodes according to the second-class microcode priority rule, and output the target microcodes through the corresponding microcode output channel.

3. The instruction fetching module as described in claim 2, characterized in that, The pre-decoding information includes an identifier indicating whether the instruction needs to be split, and the number of split targets when the instruction needs to be split; When the first N pre-decoding slots include at least one valid instruction, the bypass splitter is used to determine whether the instruction in the i-th pre-decoding slot needs to be split. If it does not need to be split, a first-type microcode corresponding to the instruction in the i-th pre-decoding slot is generated. If splitting is required, determine whether Ri < Q1 holds true. If Ri ≥ Q1, generate Q1 Type I microcodes corresponding to the instruction in the i-th pre-decoding slot. If Ri < Q1, generate Ri Type I microcodes corresponding to the instruction in the i-th pre-decoding slot, and let i = i + 1. If the instruction in the i-th pre-decoding slot is valid, repeat the determination of whether the instruction in the i-th pre-decoding slot needs to be split. Where Ri represents the number of split targets corresponding to the instruction in the i-th pre-decoding slot, 1≤i≤N, and Q1 represents the remaining number of microcodes that can be generated for the first type.

4. The instruction fetching module as described in claim 2, characterized in that, The pre-decoding information includes an identifier indicating whether the instruction needs to be split, and the number of split targets when the instruction needs to be split; When the cache unit is not empty, the queue splitter is used to determine whether the instruction in the first target entry needs to be split. If it does not need to be split, a second type microcode corresponding to the instruction in the first target entry is generated. If it needs to be split, it determines whether S1 < N is true. If S1 ≥ N, N second type microcodes corresponding to the instruction in the first target entry are generated. If S1 < N, the queue splitter generates S1 second-type microcodes corresponding to the instruction in the first target entry, determines whether the instruction in the j-th target entry needs to be split, and if not, generates one second-type microcode corresponding to the instruction in the j-th target entry; if splitting is required, it determines whether Rj < Q2 is true. If Rj ≥ Q2, it generates Q2 second-type microcodes corresponding to the instruction in the j-th target entry; if Rj < Q2, it generates Rj second-type microcodes corresponding to the instruction in the j-th target entry, and sets j = j + 1, and repeats the determination of whether the instruction in the j-th target entry needs to be split. Wherein, the first target entry is the first valid entry indicated by the read pointer in the cache unit, the j-th target entry is the j-th valid entry counted from the entry indicated by the read pointer in the cache unit, 2≤j≤N, S1 is the difference between the number of split targets corresponding to the instruction in the first target entry and the number of microcodes already output, Rj represents the number of split targets corresponding to the instruction in the j-th target entry, and Q2 represents the remaining number of microcodes that can be generated for the second type.

5. The instruction fetching module as described in claim 4, characterized in that, The instruction fetching module is also provided with a register, which is connected to the queue splitter and is used to store S1; When the cache unit is not empty, the queue splitter is used to determine the number of output microcodes of the instruction corresponding to the Nth type of microcode, and subtract the number of output microcodes of the instruction corresponding to the Nth type of microcode from the target number of splitting instructions corresponding to the Nth type of microcode to obtain the next step S1, and write it into the register.

6. The instruction fetching module as described in claim 1, characterized in that, When N target microcodes include k type 1 microcodes, the microcode output unit is used to determine whether the Kth instruction corresponding to the Kth type 1 microcode needs to be split. If the Kth instruction does not need to be split, the identifier of the (K+1)th pre-decoding slot is sent to the cache unit as the cache start pre-decoding slot identifier. When the Kth instruction needs to be split, the microcode output unit checks whether the number of bypassed microcodes corresponding to the Kth instruction reaches the split target number corresponding to the Kth instruction. If yes, the identifier of the (K+1)th pre-decoding slot is sent to the cache unit as the cache start pre-decoding slot identifier. If no, the identifier of the Kth pre-decoding slot is sent to the cache unit as the cache start pre-decoding slot identifier. The cache unit is used to cache the valid instructions stored in the first pre-decoding slot to the Mth pre-decoding slot as the remaining valid instructions in the pre-decoding unit.

7. The instruction fetching module as described in claim 2, characterized in that, The buffer unit also includes an input selector and an output selector; The output of the m-th pre-decoding slot is connected to the m-th input of the input selector, where 1 ≤ m ≤ M; The g-th output of the input selector is connected to the input of the g-th entry, the output of the g-th entry is connected to the g-th input of the output selector, and the n-th output of the output selector is connected to the n-th input of the queue splitter.

8. The instruction fetching module as described in claim 7, characterized in that, The microcode output unit is also connected to the input selector, and the microcode output unit is also connected to the output selector; The input selector is used to determine whether the number of free entries in the cache unit is greater than or equal to the number of remaining valid instructions in the pre-decoding unit after receiving the cache start pre-decoding slot identifier sent by the microcode output unit. If so, the valid instructions stored in the cache start pre-decoding slot to the Mth pre-decoding slot are written into the corresponding entries. The output selector is used to transmit the instructions from the N valid entries that start counting from the entry indicated by the read pointer in the cache unit to the queue splitter.

9. A processor, characterized in that, The processor includes the instruction fetch module as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the processor as described in claim 9.

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