High-voltage N-type MOS tube structure, linear voltage stabilization protection device and power supply system

Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a high-voltage N-type MOS (Metal Oxide Semiconductor) tube structure, a linear voltage stabilization protection device and a power supply system. A high-voltage N well; the first P-type well region is located in the high-voltage N well; the second P-type well region is located outside the high-voltage N well; the N-type well regions are located in the high-voltage N well and symmetrically arranged on the two sides of the first P-type well region; a plurality of active regions are sequentially arranged on the surface of the P-type substrate at intervals, and field regions are arranged on the two sides of each active region; forming outer oxide layers which are arranged at intervals on the surface of the P-type substrate, and forming metal connecting layers between the outer oxide layers and at positions corresponding to the active region and part of the field region; and the withstand voltage adjustment layer is located in the P-type substrate and used for adjusting withstand voltage between the high-voltage N well and the P-type substrate and / or between the high-voltage N well and the first P-type well region. The high-voltage N-type MOS tube structure provided by the invention can have overcurrent protection and overvoltage protection at the same time under the condition that the power consumption of the current linear voltage stabilizing circuit is not increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a high-voltage N-type MOS tube structure, a linear voltage protection device and a power supply system. BACKGROUND

[0002] With the rapid development of electronic technology, portable electronic products, such as mobile phones and smart wear, are also becoming more and more familiar and widely used by people. The increasing market demand for portable electronic products has promoted the booming development of power management chip market including switching voltage regulator, charge pump voltage regulator, linear voltage regulator, etc. As we all know, portable electronic products are generally small in size, and the built-in battery is also relatively small. At the same time, people also hope that portable electronic products can work and standby for as long as possible, so they hope that power management chips can work with low power consumption and as small as possible. The reduction of power management chip power consumption means the improvement of electronic product service life and standby time and the improvement of electronic product performance; at the same time, it can avoid the use of large battery to prolong the use time, which is contrary to the portable feature of electronic equipment. Therefore, as a power management chip, the low dropout linear regulator (LDO) becomes a key part in the power management chip market due to its simple structure, low power consumption and small size. According to statistics, LDO, as one of the core circuits in the power management field, accounts for about 25% of the entire power management chip market, which is the largest proportion of all products.

[0003] An important parameter closely related to the power consumption of LDO circuit is its static current, which directly determines the standby power consumption of the product. Although the static current of LDO circuit on the market can reach μA level, once the overcurrent protection function and overvoltage protection function are added, it will inevitably increase the static power consumption, which is obviously contrary to the development direction of low power consumption and low cost of linear voltage regulator.

[0004] In addition, the current conventional linear voltage regulator circuit generally only has overcurrent protection function, but no overvoltage protection function. If the input voltage of the circuit abnormally rises and exceeds the source-drain breakdown voltage of the output tube, the output voltage will rise and cannot be adjusted by the negative feedback function of the operational amplifier. This will cause the working voltage of the MCU circuit connected in the rear stage to abnormally rise, damaging the MCU circuit, and at the same time, the output tube is in a high power consumption state of high voltage and large current after being broken down, which is also easy to burn out.

[0005] Therefore, how to simultaneously have overcurrent protection and overvoltage protection without increasing the power consumption of the current linear voltage regulator circuit has become a technical problem to be solved by those skilled in the art. SUMMARY

[0006] The application provides a high-voltage N-type MOS tube structure, a linear voltage stabilizing protection device and a power supply system, and solves the problem that overcurrent protection and overvoltage protection cannot be simultaneously achieved without increasing power consumption in the prior art.

[0007] As a first aspect of the application, a high-voltage N-type MOS tube structure is provided, comprising: a P-type substrate; a high-voltage N-well extending from the surface of the P-type substrate to the interior of the P-type substrate; a first P-type well region located in the high-voltage N-well and having a depth smaller than that of the high-voltage N-well; a second P-type well region located outside the high-voltage N-well, symmetrically arranged on both sides of the high-voltage N-well and having a spacing with the high-voltage N-well, extending from the surface of the P-type substrate to the interior of the P-type substrate, and having a depth smaller than that of the high-voltage N-well; an N-type well region located in the high-voltage N-well, symmetrically arranged on both sides of the first P-type well region and having a spacing with the first P-type well region, and having a depth smaller than that of the high-voltage N-well; a plurality of active regions are sequentially and spacedly arranged on the surface of the P-type substrate, and field regions are arranged on both sides of each active region; an outer oxide layer is formed on the surface of the P-type substrate and spacedly arranged, and a metal connection layer is formed between the spacedly arranged outer oxide layer and the active region and part of the field region to realize port leading-out of the high-voltage N-type MOS tube; a voltage adjustment layer is located in the interior of the P-type substrate and used for adjusting the voltage between the high-voltage N-well and the P-type substrate and / or the voltage between the high-voltage N-well and the first P-type well region.

[0008] Further, the voltage adjustment layer comprises a P-type deep implantation layer located below the high-voltage N-well and in contact with the high-voltage N-well, the P-type deep implantation layer has a width smaller than that of the high-voltage N-well, the P-type deep implantation layer has a depth smaller than the distance from the lower surface of the P-type substrate to the lower surface of the high-voltage N-well, and the P-type deep implantation layer can adjust the voltage between the high-voltage N-well and the P-type substrate.

[0009] Further, the voltage adjustment layer comprises an N-type floating implantation layer located in the high-voltage N-well and between the N-type well region and the first P-type well region, the upper surface of the N-type floating implantation layer is in contact with the field oxide layer in the field region, and the lower surface of the N-type floating implantation layer has a spacing with the lower surface of the high-voltage N-well, and the N-type floating implantation layer can adjust the voltage between the high-voltage N-well and the first P-type well region.

[0010] Further, the active regions include first to seventh active regions arranged in sequence, the first and seventh active regions are located at corresponding positions of symmetrically arranged second P-type well regions, the second and sixth active regions are located at corresponding positions of symmetrically arranged N-type well regions, and the third, fourth and fifth active regions are located at corresponding positions of the first P-type well region. The first, fourth and seventh active regions are provided with P+ implantation diffusion regions, the second, third, fifth and sixth active regions are provided with N+ implantation diffusion regions, the P+ implantation diffusion region at the position of the fourth active region can form a back gate lead-out port of the high-voltage N-type MOS tube structure, the N+ implantation diffusion regions at the positions of the second and sixth active regions can form drain lead-out ports of the high-voltage N-type MOS tube structure, and the N+ implantation diffusion regions at the positions of the third and fifth active regions can form source lead-out ports of the high-voltage N-type MOS tube structure.

[0011] Further, a polysilicon layer is arranged above the third active region and the field region adjacent to the side of the second active region close to the third active region, and above the fifth active region and the field region adjacent to the side of the sixth active region close to the fifth active region, and the polysilicon layer can form a gate lead-out port of the high-voltage N-type MOS tube structure.

[0012] Further, the coverage area of the outer oxide layer on the surface of the P-type substrate includes all areas except the metal connection layer and the polysilicon layer, and the thickness of the outer oxide layer is 10000-12000 angstroms.

[0013] Further, each of the field regions is provided with a field oxide layer with a thickness of 5000-8000 angstroms.

[0014] As another aspect of the application, a linear voltage stabilizing protection device is provided, which includes a front-stage input unit, an intermediate-stage protection unit and a rear-stage output unit, the front-stage input unit is electrically connected to the intermediate-stage protection unit and the rear-stage output unit, the rear-stage output unit is electrically connected to the intermediate-stage protection unit, The front-stage input unit is used for amplifying an input voltage signal. The intermediate-stage protection unit includes the high-voltage N-type MOS tube structure described above, and is used for realizing overvoltage protection when the input voltage signal abnormally rises, and realizing overcurrent protection when an output current signal abnormally rises. The rear-stage output unit is used for outputting a linear voltage stabilized voltage signal.

[0015] Further, the front-stage input unit comprises an operational amplifier and a first resistor, a positive input terminal of the operational amplifier is connected with a reference voltage, a negative input terminal of the operational amplifier is connected with the rear-stage output unit, a positive power supply terminal of the operational amplifier is connected with one end of the first resistor, the other end of the first resistor is connected with a power input terminal, a negative power supply terminal of the operational amplifier is connected with a signal ground, and an output terminal of the operational amplifier is connected with the intermediate-stage protection unit. The intermediate-stage protection unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second resistor and a third resistor, the first NMOS tube comprises the high-voltage N-type MOS tube structure, a gate of the first PMOS tube is connected with a gate of the second PMOS tube, a source of the first PMOS tube is connected with a source of the second PMOS tube, and the source of the first PMOS tube and the source of the second PMOS tube are both connected with one end of the first resistor, a back gate of the first PMOS tube is short-circuited with the source of the first PMOS tube, and a drain of the first PMOS tube is short-circuited with the gate of the first PMOS tube and then connected with one end of the second resistor, the other end of the second resistor is connected with a drain of the first NMOS tube, a back gate of the first NMOS tube is connected with a signal ground, a source of the first NMOS tube is connected with one end of the third resistor, and the other end of the third resistor is connected with a gate of the first NMOS tube, a back gate of the second PMOS tube is short-circuited with the source of the second PMOS tube, and a drain of the second PMOS tube is connected with an output terminal of the operational amplifier, a gate of the third PMOS tube is connected with the output terminal of the operational amplifier, a back gate of the third PMOS tube is short-circuited with the source of the third PMOS tube and then connected with one end of the first resistor, and a drain of the third PMOS tube is connected with the other end of the third resistor; The rear-stage output unit comprises a fourth PMOS tube, a fourth resistor and a fifth resistor, a gate of the fourth PMOS tube is connected with a gate of the third PMOS tube, a back gate of the fourth PMOS tube is short-circuited with the source of the fourth PMOS tube and then connected with a power input terminal, a drain of the fourth PMOS tube is connected with one end of the third resistor, one end of the fourth resistor is connected with one end of the third resistor, the other end of the fourth resistor is connected with a negative input terminal of the operational amplifier, one end of the fifth resistor is connected with the other end of the fourth resistor, the other end of the fifth resistor is connected with a signal ground, and the drain of the fourth PMOS tube is an output terminal of the rear-stage output unit.

[0016] As another aspect of the present application, a power supply system is provided, wherein the linear voltage stabilizing protection device described above is included.

[0017] The high-voltage N-type MOS tube structure provided by the application sets a voltage-withstanding adjustment layer in the P-type substrate, which can adjust the voltage withstanding between the high-voltage N well and the P-type substrate and / or between the high-voltage N well and the first P-type well region, so that the high-voltage N-type MOS tube can provide overvoltage protection when an abnormal high voltage occurs at the input end of the linear voltage stabilizing protection device. At the same time, the voltage-withstanding adjustment layer set in the P-type substrate itself has a certain volume, so that the PN junction area between the high-voltage N well and the voltage-withstanding adjustment layer and between the first P-type well region and the voltage-withstanding adjustment layer is large, thereby enabling the high-voltage N-type MOS tube to provide strong continuous current capability after the above-mentioned PN junction is broken down. This strong continuous current capability not only improves the anti-breakdown capability of the high-voltage N-type MOS tube, but also improves the voltage range of the overvoltage protection at the input end of the linear voltage stabilizing protection device. Therefore, the high-voltage N-type MOS tube structure not only has the overcurrent protection function itself, but also has the stable overvoltage protection function, and the change of the high-voltage N-type MOS tube structure has no effect on the normal operation and electrostatic protection performance of the linear voltage stabilizing protection device. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. The drawings are provided solely for purposes of illustration and should not be considered a limitation of the application.

[0019] Figure 1 A structure schematic diagram of the high-voltage N-type MOS tube structure provided by the application.

[0020] Figure 2 A structure schematic diagram of one embodiment of the high-voltage N-type MOS tube structure provided by the application.

[0021] Figure 3 A structure schematic diagram of another embodiment of the high-voltage N-type MOS tube structure provided by the application.

[0022] Figure 4 A structure schematic diagram of another embodiment of the high-voltage N-type MOS tube structure provided by the application.

[0023] Figure 5 A structure schematic diagram of the linear voltage stabilizing protection device provided by the application. DETAILED DESCRIPTION

[0024] It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other without conflict. The application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0025] In order to make the technical personnel better understand the present application, the following will be combined with the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application are described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0027] In the present embodiment, a high-voltage N-type MOS tube structure is provided, Figure 1 is a longitudinal sectional view of the high-voltage N-type MOS tube structure provided according to the embodiments of the present application, as Figure 1 shown, comprising: A P-type substrate 100; A high-voltage N-well 110 extending along the surface of the P-type substrate 100 to the inside of the P-type substrate 100; A first P-well region 121 located in the high-voltage N-well 110, and the depth of the first P-well region 121 is less than the depth of the high-voltage N-well 110; A second P-well region 122 located outside the high-voltage N-well 110, symmetrically arranged on both sides of the high-voltage N-well 110 and having a gap between the high-voltage N-well 110, extending along the surface of the P-type substrate 100 to the inside of the P-type substrate 100, the depth of the second P-well region 122 is less than the depth of the high-voltage N-well 110; An N-well region 130 located in the high-voltage N-well 110, symmetrically arranged on both sides of the first P-well region 121 and having a gap between the first P-well region 121, the depth of the N-well region 130 is less than the depth of the high-voltage N-well 110; A plurality of active regions 140 are arranged in sequence and spaced apart on the surface of the P-type substrate 100, and field regions 150 are arranged on both sides of each active region; The spaced-out outer oxide layer 160 is formed on the surface of the P-type substrate 100, and the metal connecting layer 190 is formed between the spaced-out outer oxide layer 160 and the active region and the position corresponding to the partial field region, so as to realize the port leading-out of the high-voltage N-type MOS tube. The voltage adjustment layer 170 is located in the P-type substrate 100, and is used for adjusting the voltage between the high-voltage N well 110 and the P-type substrate 100 and / or the voltage between the high-voltage N well 110 and the first P-type well region 121.

[0028] In the embodiment of the present application, the voltage adjustment layer is arranged in the P-type substrate, so that when the high-voltage N-type MOS tube with the structure is applied to the linear voltage stabilizing protection device, the overvoltage protection can be provided in the case that the abnormal high voltage appears at the input end of the linear voltage stabilizing protection device. Meanwhile, because the voltage adjustment layer itself has a certain volume, the PN junction area between the high-voltage N well and the voltage adjustment layer and the PN junction area between the first P-type well region and the voltage adjustment layer are both large, so that the strong continuous current capability can be provided after the PN junction of the high-voltage N-type MOS tube is broken down. The strong continuous current capability can not only improve the anti-breakdown capability of the high-voltage N-type MOS tube itself, but also improve the voltage range of the overvoltage protection at the input end of the linear voltage stabilizing protection device. When the high-voltage N-type MOS tube is applied to the linear voltage stabilizing protection device, the overvoltage protection can be provided in the case that the abnormal high voltage appears at the input end. The change of the structure of the high-voltage N-type MOS tube has no influence on the normal work and the electrostatic protection performance of the linear voltage stabilizing protection device.

[0029] Therefore, the high-voltage N-type MOS tube structure provided by the present application arranges the voltage adjustment layer in the P-type substrate, so as to adjust the voltage between the high-voltage N well and the P-type substrate and / or the voltage between the high-voltage N well and the first P-type well region. When the high-voltage N-type MOS tube is applied to the linear voltage stabilizing protection device, the overvoltage protection can be provided in the case that the abnormal high voltage appears at the input end of the linear voltage stabilizing protection device. Meanwhile, because the voltage adjustment layer arranged in the P-type substrate itself has a certain volume, the PN junction area between the high-voltage N well and the voltage adjustment layer and the PN junction area between the first P-type well region and the voltage adjustment layer are both large, so that the strong continuous current capability can be provided after the PN junction of the high-voltage N-type MOS tube is broken down. The strong continuous current capability can not only improve the anti-breakdown capability of the high-voltage N-type MOS tube itself, but also improve the voltage range of the overvoltage protection at the input end of the linear voltage stabilizing protection device. Therefore, the high-voltage N-type MOS tube structure can not only realize the overcurrent protection function itself, but also realize the stable overvoltage protection function, and the change of the structure of the high-voltage N-type MOS tube has no influence on the normal work and the electrostatic protection performance of the linear voltage stabilizing protection device.

[0030] In the embodiment of the present application, as shown inFigure 2 As shown, the active regions include first active region 141 to seventh active region 147 arranged in sequence, the first active region 141 and the seventh active region 147 are respectively located at the corresponding positions of the symmetrically arranged second P-type well region 122, the second active region 142 and the sixth active region 146 are respectively located at the corresponding positions of the symmetrically arranged N-type well region 130, and the third active region 143, the fourth active region 144 and the fifth active region 145 are all located at the corresponding positions of the first P-type well region 121. The positions of the first active region 141, the fourth active region 144 and the seventh active region 147 are provided with P+ implantation diffusion regions 104, the positions of the second active region 142, the third active region 143, the fifth active region 145 and the sixth active region 146 are provided with N+ implantation diffusion regions 105, the P+ implantation diffusion region 104 at the position of the fourth active region 144 can form a back gate lead-out port of the high-voltage N-type MOS tube structure, the N+ implantation diffusion regions 105 at the positions of the second active region 142 and the sixth active region 146 can form drain lead-out ports of the high-voltage N-type MOS tube structure, and the N+ implantation diffusion regions 105 at the positions of the third active region 143 and the fifth active region 145 can form source lead-out ports of the high-voltage N-type MOS tube structure.

[0031] It should be noted that the P+ implantation diffusion region 104 can increase the doping concentration at the first P-type well region 121 and the second P-type well region 122, so as to form a good ohmic contact through the contact hole and the metal connection layer 190, wherein the P+ implantation diffusion region 104 at the positions of the first active region 141 and the seventh active region 147 serves as a ground terminal lead-out port, the P+ implantation diffusion region 104 at the position of the fourth active region 144 serves as a back gate lead-out port, and the N+ implantation diffusion region 105 can increase the doping concentration at the N-type well region 130 and the first P-type well region 121, so as to increase the doping concentration at the position, so as to form a good ohmic contact through the contact hole and the metal connection layer, the N+ implantation diffusion regions 105 at the positions of the second active region 142 and the sixth active region 146 serve as drain lead-out ports, and the N+ implantation diffusion regions 105 at the positions of the third active region 143 and the fifth active region 145 serve as source lead-out ports.

[0032] In the embodiment of the present application, a polysilicon layer 180 is arranged above the third active region 143 and the field region adjacent to the side close to the second active region 142 thereof, and above the fifth active region 145 and the field region adjacent to the side close to the sixth active region 146 thereof, and the polysilicon layer 180 can form a gate lead-out port of the high-voltage N-type MOS tube structure.

[0033] It should be understood that the first active region 141 and the seventh active region 147 are respectively located at the corresponding positions of the symmetrically arranged second P-type well region 122, the second active region 142 and the sixth active region 146 are respectively located at the corresponding positions of the symmetrically arranged N-type well region 130, and the third active region 143, the fourth active region 144 and the fifth active region 145 are all located at the corresponding positions of the first P-type well region 121. Figures 2 to 4The direction of the cross-sectional view is shown as an example. The polysilicon layer 180 is located above the third active region 143 and its left field region (i.e. the field region close to the second active region 142), and above the fifth active region 145 and its right field region (i.e. the field region close to the sixth active region 146).

[0034] In the embodiment of the present application, the field oxide layer 151 with a thickness of 5000-8000 angstroms is arranged at the position of each field region 150, which can serve as an isolation between two adjacent active regions.

[0035] In addition, the second P-type well region 122 in the embodiment of the present application serves as the ground terminal of the high-voltage N-type MOS tube, i.e. the ground terminal of the entire circuit.

[0036] In the embodiment of the present application, the covering area of the outer oxide layer 160 on the surface of the P-type substrate 100 includes all areas except the metal connection layer 190 and the polysilicon layer 180. The thickness of the outer oxide layer 160 is 10000-12000 angstroms.

[0037] It should be understood that, as shown, Figure 2 The polysilicon layers arranged symmetrically are located above the third active region 143 and its adjacent field oxide layer 151, and above the fifth active region 145 and its adjacent field oxide layer 151. The metal connection layer 190 is located at the corresponding positions of the first active region 141 to the seventh active region 147 and the polysilicon layer 180.

[0038] In the embodiment of the present application, the outer oxide layer 160 with a thickness of 10000-12000 angstroms is arranged above all field oxide layers and active regions, covering the surface of the high-voltage N-type MOS tube. The corresponding positions of the outer oxide layer 160 at the P+ implantation diffusion region 104 of the first active region 141, the fourth active region 144 and the seventh active region 147, at the N+ implantation diffusion region 105 of the second active region 142, the third active region 143, the fifth active region 145 and the sixth active region 146, and at the corresponding positions of the symmetrically arranged polysilicon layer 180 are removed to form contact holes reaching the silicon surface. The metal connection layer 190 is arranged at the position of each contact hole to contact the silicon surface and the surface of the polysilicon layer 180, and the ports of the high-voltage N-type MOS tube are led out to form a complete high-voltage N-type MOS tube structure.

[0039] In the embodiment of the present application, as a specific implementation of the voltage adjustment layer, as shown, Figure 2As shown, the withstand voltage adjustment layer 170 includes a P-type deep injection layer 171, which is located below and in contact with the high-voltage N-well 110. The width of the P-type deep injection layer 171 is smaller than the width of the high-voltage N-well 110, and the depth of the P-type deep injection layer 171 is smaller than the distance from the bottom of the high-voltage N-well 110 to the lower surface of the P-type substrate 100. The P-type deep injection layer 171 can adjust the withstand voltage between the high-voltage N-well 110 and the P-type substrate 100.

[0040] It should be understood that a P-type deep implantation layer 171 is provided below the bottom of the high-voltage N-well 110 to adjust the breakdown voltage between the high-voltage N-well 110 and the P-type substrate 100. The lateral width of the P-type deep implantation layer 171 is equivalent to that of the high-voltage N-well 110; the longitudinal width of the P-type deep implantation layer 171 extends downward from the bottom of the high-voltage N-well 110 by 1 to 3 micrometers. In this embodiment, by providing the P-type deep implantation layer 171, the breakdown voltage between the high-voltage N-well 110 and the P-type substrate 100 can be adjusted. Specifically, adjusting the concentration of the P-type deep implantation layer 171 can adjust the breakdown voltage of the high-voltage N-well and the P-type substrate, that is, the breakdown voltage from the drain of the high-voltage N-type MOSFET to the circuit ground, so that it meets the overvoltage protection voltage setting value of the circuit.

[0041] As another specific implementation method, such as Figure 3 As shown, the withstand voltage adjustment layer 170 includes an N-type suspended injection layer 172, which is located within the high-pressure N-well 110 and between the N-type well region 130 and the first P-type well region 121. The upper surface of the N-type suspended injection layer 172 is in contact with the field oxide layer 151 in the field region, and there is a gap between the lower surface of the N-type suspended injection layer 172 and the lower surface of the high-pressure N-well 110. The N-type suspended injection layer 172 can adjust the withstand voltage between the high-pressure N-well 110 and the first P-type well region 121.

[0042] In this embodiment, the lateral width of the N-type floating injection layer 172 is equal to the spacing between the N-type well region 130 and the first P-type well region 121. The longitudinal width of the N-type floating injection layer 172 extends downward from the bottom of the field oxide layer 151 within the high-voltage N-well 110 by 3 to 4 micrometers. In this embodiment, by providing the N-type floating injection layer 172, the withstand voltage between the high-voltage N-well 110 and the first P-type well region 121 can be adjusted. Specifically, by providing the N-type floating injection layer 172 between the drain N-well and the back gate P-well, the breakdown voltage of the drain and the back gate is adjusted to the overvoltage protection voltage setting value. In addition, by simultaneously optimizing the width of the polysilicon layer 180 and the underlying field oxide layer 151, as well as the overlap between them, the high drain-source breakdown voltage and other electrical parameters of the high-voltage N-type MOSFET can be maintained unchanged.

[0043] As another specific implementation method, such as Figure 4 As shown, the withstand voltage adjustment layer 170 may include a P-type deep implantation layer 171 and an N-type floating implantation layer 172. The P-type deep implantation layer 171 is located below and in contact with the high-voltage N-well 110. The width of the P-type deep implantation layer 171 is smaller than the width of the high-voltage N-well 110, and the depth of the P-type deep implantation layer 171 is smaller than the distance from the bottom of the high-voltage N-well 110 to the lower surface of the P-type substrate 100. The P-type deep implantation layer 171 is capable of adjusting the high-voltage N-well 110. The withstand voltage between the high-voltage N-well 110 and the P-type substrate 100 is adjusted. An N-type levitation injection layer 172 is located within the high-voltage N-well 110 and between the N-type well region 130 and the first P-type well region 121. The upper surface of the N-type levitation injection layer 172 contacts the field oxide layer 151 within the field region, and a gap exists between the lower surface of the N-type levitation injection layer 172 and the lower surface of the high-voltage N-well 110. The N-type levitation injection layer 172 can adjust the withstand voltage between the high-voltage N-well 110 and the first P-type well region 121. Therefore, in this embodiment, by providing the P-type deep injection layer 171 and the N-type levitation injection layer 172, the withstand voltage between the high-voltage N-well 110 and the P-type substrate 100, and between the high-voltage N-well 110 and the first P-type well region 121, can be adjusted.

[0044] Therefore, the high-voltage N-type MOS tube structure provided by the application can make the breakdown voltage of the drain of the high-voltage N-type MOS tube to the ground lower than the breakdown voltage of the source and the drain, so that the breakdown between the drain and the ground of the high-voltage N-type MOS tube can be preferentially caused and protection can be started when the input voltage is abnormally high, thereby protecting the structure of the output tube in the later stage and realizing the overvoltage protection function. In addition, the N-type floating injection layer is added between the drain N-type well and the back gate P-type well of the N-type MOS tube, so that the breakdown voltage between the drain and the back gate is reduced, and the breakdown between the drain and the back gate of the N-type MOS tube can be preferentially caused and protection can be started when the input voltage is abnormally high, thereby realizing the overvoltage protection function of the input as described above. Therefore, the high-voltage N-type MOS tube structure can realize the overcurrent protection function and the overvoltage protection function without changing the existing circuit connection, without increasing the circuit chip area and the power consumption, thereby making the circuit reliability realize a qualitative leap.

[0045] As another embodiment of the application, a linear voltage stabilizing protection device 10 is provided, as shown in Figure 5 which comprises a front-stage input unit 11, an intermediate-stage protection unit 12 and a rear-stage output unit 13, the front-stage input unit 11 is electrically connected to the intermediate-stage protection unit 12 and the rear-stage output unit 13, and the rear-stage output unit 13 is electrically connected to the intermediate-stage protection unit 12, the front-stage input unit 11 is used for amplifying the input voltage signal; the intermediate-stage protection unit 12 comprises the high-voltage N-type MOS tube structure as described above, which is used for realizing the overvoltage protection function when the input voltage signal is abnormally high and realizing the overcurrent protection function when the output current signal is abnormally high; the rear-stage output unit 13 is used for outputting the linear voltage stabilized voltage signal.

[0046] In the embodiment of the application, as shown in Figure 5 the front-stage input unit comprises an operational amplifier OP and a first resistor R1, the positive input end of the operational amplifier OP is connected to a reference voltage Vref, the negative input end of the operational amplifier OP is connected to the rear-stage output unit 13, one end of the first resistor R1 is connected to the positive power supply end of the operational amplifier OP, the other end of the first resistor R1 is connected to the power input end Vin, the negative power supply end of the operational amplifier OP is connected to the signal ground Gnd, and the output end of the operational amplifier OP is connected to the intermediate-stage protection unit 12; The intermediate stage protection unit 12 comprises a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a first NMOS tube NM1, a second resistor R2 and a third resistor R3, the first NMOS tube NM1 comprises the high-voltage N-type MOS tube structure, The gate of the first PMOS tube PM1 is connected with the gate of the second PMOS tube PM2, the source of the first PMOS tube PM1 is connected with the source of the second PMOS tube PM2, and the source of the first PMOS tube PM1 and the source of the second PMOS tube PM2 are both connected to one end of the first resistor R1, the back gate of the first PMOS tube PM1 is short-circuited with the source thereof, and the drain of the first PMOS tube PM1 is short-circuited with the gate thereof and then connected to one end of the second resistor R2, The other end of the second resistor R2 is connected to the drain of the first NMOS tube NM1, the back gate of the first NMOS tube NM1 is connected to the signal ground, the source of the first NMOS tube NM1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the gate of the first NMOS tube NM1, The back gate of the second PMOS tube PM2 is short-circuited with the source thereof, and the drain of the second PMOS tube PM2 is connected to the output end of the operational amplifier OP, The gate of the third PMOS tube PM3 is connected to the output end of the operational amplifier OP, the back gate of the third PMOS tube PM3 is short-circuited with the source thereof and then connected to one end of the first resistor R1, and the drain of the third PMOS tube PM3 is connected to the other end of the third resistor R3; The later stage output unit 13 comprises a fourth PMOS tube PM4, a fourth resistor R4 and a fifth resistor R5, the gate of the fourth PMOS tube PM4 is connected to the gate of the third PMOS tube PM3, the back gate of the fourth PMOS tube PM4 is short-circuited with the source thereof and then connected to the power input end Vin, the drain of the fourth PMOS tube PM4 is connected to one end of the third resistor R3, one end of the fourth resistor R4 is connected to one end of the third resistor R3, the other end of the fourth resistor R4 is connected to the negative phase input end of the operational amplifier OP, one end of the fifth resistor R5 is connected to the other end of the fourth resistor R4, the other end of the fifth resistor R5 is connected to the signal ground Gnd, and the drain of the fourth PMOS tube PM4 is the output end Vout of the later stage output unit 13.

[0047] In the embodiment of the present application, the specific working principle of the linear voltage stabilizing protection circuit is that the positive input terminal of the operational amplifier OP receives the reference voltage Vref provided in the front, and the negative input terminal is connected to the common terminal of the fourth resistor R4 and the fifth resistor R5, so as to realize the negative feedback adjustment of the output voltage Vout, so that the output voltage is stabilized at the set value. In this structure, the first NMOS tube NM1 is used as an overcurrent protection switch. When the current of the fourth PMOS tube PM4 of the output stage is abnormally large, an incremental current mirrored on the third PMOS tube PM3 is generated. The abnormal incremental current causes the voltage across the third resistor R3 to rise, thereby causing the gate and source voltages of the first NMOS tube NM1 to rise, and the first NMOS tube NM1 is turned from the original off state to the on state. After the first NMOS tube NM1 is turned on, the first PMOS tube PM1 and the second PMOS tube PM2 are turned on, causing the drain potential of the second PMOS tube PM2 to rise, that is, the gate potential of the output tube fourth PMOS tube PM4 rises, thereby causing the current of the output stage fourth PMOS tube PM4 to decrease, playing a negative feedback role in controlling the current of the fourth PMOS tube PM4, and protecting the circuit. The first NMOS tube NM1 is off during normal operation of the circuit, and is only turned on when the current of the output tube fourth PMOS tube PM4 reaches a certain value, triggering the overcurrent protection function. It can be seen that the first NMOS tube NM1 functions as an overcurrent protection switch.

[0048] In the existing conventional circuit, when the input voltage Vin abnormally rises and exceeds the source-drain breakdown voltage of the output tube fourth PMOS tube PM4, the output voltage Vout will abnormally rise, and the output voltage cannot be adjusted by the negative feedback function of the operational amplifier OP. This will cause the working voltage of the subsequent MCU circuit to abnormally rise, damaging the subsequent MCU circuit. At the same time, after the output tube PM4 is broken down, it is in a high-power consumption state of high voltage and large current, and is also easy to burn out. If an overvoltage protection function is separately added to the linear voltage stabilizing protection circuit, an additional circuit module structure needs to be added, which will increase the static power consumption and the chip area (i.e. the cost), which is obviously contrary to the development direction of low power consumption and low cost of linear voltage stabilizing circuits. Therefore, in the embodiment of the present application, the first NMOS tube NM1 adopts the structure of the high-voltage N-type MOS tube described in the foregoing, thereby realizing the perfect unification of the overcurrent protection and overvoltage protection functions of the circuit without changing the circuit connection mode of the linear voltage stabilizing protection device, without increasing the circuit chip area and power consumption, and greatly improving the reliability of the circuit.

[0049] Specifically, as a specific implementation manner, in combination with Figure 2 As shown in the figure, a P-type deep implantation layer 171 is added below the bottom of the high-voltage N-well 110 of the first NMOS tube NM1, so as to adjust the voltage resistance of the high-voltage N-well 110 to the P-type substrate 100, that is, Figure 5The voltage resistance between the drain of the first NMOS transistor NM1 and the ground terminal Gnd is lower than the source-drain breakdown voltage of the first NMOS transistor NM1 and the fourth PMOS transistor PM4. For example, if the maximum working voltage of the input terminal Vin of the linear voltage stabilizer is 24V, and the source-drain breakdown voltage of the first NMOS transistor NM1 and the fourth PMOS transistor PM4 is greater than 50V, the voltage resistance between the drain of the first NMOS transistor NM1 and the ground terminal Gnd can be reduced to about 40V by the P-type deep implantation layer 171. In this way, when the voltage of the input terminal Vin abnormally rises, the breakdown between the drain of the first NMOS transistor NM1 and the ground terminal Gnd will occur before the breakdown between the source and the drain of the first NMOS transistor NM1 and the fourth PMOS transistor PM4, and the current will flow from the drain of the first NMOS transistor NM1 to the ground terminal Gnd. The current will turn on the first PMOS transistor PM1 and the second PMOS transistor PM2, and gradually turn off the fourth PMOS transistor PM4, so that the voltage of the output terminal Vout decreases. Thus, when the voltage of the input terminal Vin abnormally rises, the MCU circuit in the subsequent stage is protected from being damaged by the high voltage of the output terminal, and the fourth PMOS transistor PM4 in the output stage of the circuit is also protected from being damaged under high voltage and high power, thereby realizing the overvoltage protection function of the linear voltage stabilizer itself.

[0050] As another specific embodiment, unlike the first structure described above, there is no P-type deep implantation layer 171 under the bottom of the high-voltage N-well 110 of the first NMOS transistor NM1, and the conventional structure between the high-voltage N-well 110 of the first NMOS transistor NM1 and the P-type substrate 100 is maintained unchanged, that is, the Figure 5 The voltage resistance between the drain of the first NMOS transistor NM1 and the ground terminal Gnd is lower than the source-drain breakdown voltage of the first NMOS transistor NM1 and the fourth PMOS transistor PM4. For example, if the maximum working voltage of the input terminal Vin of the linear voltage stabilizer is 24V, and the source-drain breakdown voltage of the first NMOS transistor NM1 and the fourth PMOS transistor PM4 is greater than 50V, the voltage resistance between the drain of the first NMOS transistor NM1 and the ground terminal Gnd can be reduced to about 40V by the P-type deep implantation layer 171. In this way, when the voltage of the input terminal Vin abnormally rises, the breakdown between the drain of the first NMOS transistor NM1 and the ground terminal Gnd will occur before the breakdown between the source and the drain of the first NMOS transistor NM1 and the fourth PMOS transistor PM4, and the current will flow from the drain of the first NMOS transistor NM1 to the ground terminal Gnd. The current will turn on the first PMOS transistor PM1 and the second PMOS transistor PM2, and gradually turn off the fourth PMOS transistor PM4, so that the voltage of the output terminal Vout decreases. Thus, when the voltage of the input terminal Vin abnormally rises, the MCU circuit in the subsequent stage is protected from being damaged by the high voltage of the output terminal, and the fourth PMOS transistor PM4 in the output stage of the circuit is also protected from being damaged under high voltage and high power, thereby realizing the overvoltage protection function of the linear voltage stabilizer itself. Figure 5 The voltage resistance between the drain of the first NMOS transistor NM1 and the ground terminal Gnd is lower than the source-drain breakdown voltage of the first NMOS transistor NM1 and the fourth PMOS transistor PM4. For example, if the maximum working voltage of the input terminal Vin of the linear voltage stabilizer is 24V, and the source-drain breakdown voltage of the first NMOS transistor NM1 and the fourth PMOS transistor PM4 is greater than 50V, the voltage resistance between the drain of the first NMOS transistor NM1 and the ground terminal Gnd can be reduced to about 40V by the P-type deep implantation layer 171. In this way, when the voltage of the input terminal Vin abnormally rises, the breakdown between the drain of the first NMOS transistor NM1 and the ground terminal Gnd will occur before the breakdown between the source and the drain of the first NMOS transistor NM1 and the fourth PMOS transistor PM4, and the current will flow from the drain of the first NMOS transistor NM1 to the ground terminal Gnd. The current will turn on the first PMOS transistor PM1 and the second PMOS transistor PM2, and gradually turn off the fourth PMOS transistor PM4, so that the voltage of the output terminal Vout decreases. Thus, when the voltage of the input terminal Vin abnormally rises, the MCU circuit in the subsequent stage is protected from being damaged by the high voltage of the output terminal, and the fourth PMOS transistor PM4 in the output stage of the circuit is also protected from being damaged under high voltage and high power, thereby realizing the overvoltage protection function of the linear voltage stabilizer itself. Figure 5As shown, by adding the N-type floating implant layer 172, the breakdown voltage between the drain of the first NMOS transistor NM1 and the back gate is reduced to about 40V, the breakdown voltage between the source and the drain of the first NMOS transistor NM1 and the fourth PMOS transistor PM4 is greater than 50V, and the maximum working voltage of the input terminal Vin of the linear voltage stabilizing protection circuit is 24V. In this way, when the voltage of the input terminal Vin abnormally rises, the breakdown between the drain of the first NMOS transistor NM1 and the back gate will occur prior to the breakdown between the source and the drain of the first NMOS transistor NM1 and the fourth PMOS transistor PM4, and at this time, the current will flow from the drain of the first NMOS transistor NM1 to the back gate and then to the ground terminal Gnd through the metal line. The current will also turn on the first PMOS transistor PM1 and the second PMOS transistor PM2 and gradually turn off the fourth PMOS transistor PM4, so as to lower the voltage of the output terminal Vout and achieve the same overvoltage protection function of the input terminal Vin as described above.

[0051] It should be noted that, due to the P-type deep implant layer 171 and / or the N-type floating implant layer 172 added to the first NMOS transistor NM1, the P-type deep implant layer 171 and the two PN junctions of the high-voltage N-well 110 and / or the first P-type well region 121 and the N-type floating implant layer 172 have a certain volume, and the two PN junctions have a large junction area, which can provide a strong current after the PN junction is broken down, so as to not only protect the first NMOS transistor NM1 from being broken down and damaged, but also improve the voltage range of the overvoltage protection, i.e., the overvoltage protection can be provided in a relatively high voltage range of the input terminal. It can also be seen that the changes of the above two structures of the first NMOS transistor NM1 have no effect on the normal operation and electrostatic protection of the circuit.

[0052] It should be understood that, the embodiment of the present application only exemplifies the case that the working voltage of the input terminal Vin is 24V, the breakdown voltage between the source and the drain of the first NMOS transistor NM1 and the fourth PMOS transistor PM4 is 50V, and the voltage resistance of the drain of the first NMOS transistor NM1 to the Gnd and the drain of the first NMOS transistor NM1 to the back gate is 40V. For those skilled in the art, the overvoltage protection structure with different levels of voltage resistance of the drain of NM1 to the Gnd and the drain to the back gate can be easily obtained by changing the working voltage of the input terminal, the breakdown voltage of the high-voltage NMOS and the high-voltage PMOS, and adjusting the doping concentration of the P-type deep implant layer and the N-type floating implant layer.

[0053] As another embodiment of the present application, a power supply system is provided, which comprises the linear voltage stabilizing protection device described above.

[0054] The power supply system provided by the application has the functions of overcurrent protection and overvoltage protection without changing the structure of the linear voltage stabilizing protector and without affecting the normal operation and electrostatic protection performance of the linear voltage stabilizing protector, so that the power supply system does not increase power consumption and cost, and has high product competitiveness.

[0055] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the application, and the application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the application, and these modifications and improvements are also considered to be within the protection scope of the application.

Claims

1. A high voltage N-type MOSFET structure, characterized by, include: P-type substrate; A high-voltage N-well extends along the surface of the P-type substrate into the interior of the P-type substrate; A first P-type well region is located within the high-pressure N-well, and the depth of the first P-type well region is less than the depth of the high-pressure N-well; The second P-type well region is located outside the high-voltage N-well, symmetrically arranged on both sides of the high-voltage N-well and spaced apart from the high-voltage N-well, and extends along the surface of the P-type substrate into the interior of the P-type substrate. The depth of the second P-type well region is less than the depth of the high-voltage N-well. The N-type well region is located inside the high-pressure N-well, symmetrically arranged on both sides of the first P-type well region, and there is a gap between the N-type well region and the first P-type well region. The depth of the N-type well region is less than the depth of the high-pressure N-well. Multiple active regions are sequentially and spaced apart on the surface of the P-type substrate, and field regions are provided on both sides of each active region; An external oxide layer is formed at intervals on the surface of the P-type substrate, and a metal connection layer is formed between the intervals of the external oxide layer and at the corresponding positions of the active region and part of the field region to realize the port lead-out of the high voltage N-type MOS transistor. A withstand voltage adjustment layer, located inside the P-type substrate, is used to adjust the withstand voltage between the high-voltage N-well and the P-type substrate and / or between the high-voltage N-well and the first P-type well region.

2. The high-voltage NMOS structure of claim 1, wherein, The withstand voltage adjustment layer includes a P-type deep implantation layer, which is located below and in contact with the high-voltage N-well. The width of the P-type deep implantation layer is smaller than the width of the high-voltage N-well, and the depth of the P-type deep implantation layer is smaller than the distance from the bottom of the high-voltage N-well to the lower surface of the P-type substrate. The P-type deep implantation layer can adjust the withstand voltage between the high-voltage N-well and the P-type substrate.

3. The high-voltage NMOS structure of claim 1 or 2, wherein, The withstand voltage adjustment layer includes an N-type suspended injection layer located within the high-pressure N-well and between the N-type well region and the first P-type well region. The upper surface of the N-type suspended injection layer is in contact with the field oxide layer in the field region, and there is a gap between the lower surface of the N-type suspended injection layer and the lower surface of the high-pressure N-well. The N-type suspended injection layer can adjust the withstand voltage between the high-pressure N-well and the first P-type well region.

4. The high voltage NMOS structure of claim 1, wherein, The active region includes a first active region to a seventh active region arranged at intervals in sequence. The first active region and the seventh active region are respectively located at corresponding positions of a symmetrically arranged second P-type well region. The second active region and the sixth active region are respectively located at corresponding positions of a symmetrically arranged N-type well region. The third active region, the fourth active region and the fifth active region are all located at corresponding positions of the first P-type well region. The first active region, the fourth active region and the seventh active region are provided with P+ injection diffusion regions, and the second active region, the third active region, the fifth active region and the sixth active region are provided with N+ injection diffusion regions; the P+ injection diffusion region at the position of the fourth active region can form a back gate lead-out port of the high-voltage N-type MOS structure; the N+ injection diffusion regions at the positions of the second active region and the sixth active region can form a drain lead-out port of the high-voltage N-type MOS structure; and the N+ injection diffusion regions at the positions of the third active region and the fifth active region can form a source lead-out port of the high-voltage N-type MOS structure.

5. The high-voltage NMOS structure of claim 4, wherein, A polysilicon layer is arranged above the third active region and the field region adjacent to the side close to the second active region of the third active region, and above the fifth active region and the field region adjacent to the side close to the sixth active region of the fifth active region, and the polysilicon layer can form a gate lead-out port of the high-voltage N-type MOS structure.

6. The high-voltage NMOS structure of claim 5, wherein, The outer oxide layer covers all regions of the surface of the P-type substrate except the metal connection layer and the polysilicon layer, and the thickness of the outer oxide layer is 10000 Å~ 12000 Å.

7. The high voltage NMOS structure of claim 1, wherein, The position of each field region is provided with a field oxide layer with a thickness of 5000 Å~ 8000 Å.

8. A linear voltage regulator guard, comprising: Comprise: a front-stage input unit, an intermediate-stage protection unit and a rear-stage output unit, the front-stage input unit is electrically connected with the intermediate-stage protection unit and the rear-stage output unit respectively, and the rear-stage output unit is electrically connected with the intermediate-stage protection unit, the front-stage input unit is used for amplifying and processing an input voltage signal; the intermediate-stage protection unit comprises the high-voltage N-type MOS structure of any one of claims 1 to 7, and is used for realizing overvoltage protection function when the input voltage signal abnormally rises, and realizing overcurrent protection function when an output current signal abnormally rises; the rear-stage output unit is used for outputting a linearly stabilized voltage signal.

9. The linear voltage regulator guard of claim 8, wherein, the front-stage input unit comprises an operational amplifier and a first resistor, the positive-phase input end of the operational amplifier is connected with a reference voltage, the negative-phase input end of the operational amplifier is connected with the rear-stage output unit, one end of the first resistor is connected with the positive power supply end of the operational amplifier, the other end of the first resistor is connected with a power supply input end, the negative power supply end of the operational amplifier is connected with a signal ground, and the output end of the operational amplifier is connected with the intermediate-stage protection unit; the intermediate-stage protection unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second resistor and a third resistor, and the first NMOS tube comprises the high-voltage N-type MOS structure, the gate of the first PMOS tube is connected with the gate of the second PMOS tube, the source of the first PMOS tube is connected with the source of the second PMOS tube, and the source of the first PMOS tube and the source of the second PMOS tube are both connected with one end of the first resistor, the back gate of the first PMOS tube is short-circuited with the source of the first PMOS tube, and the drain of the first PMOS tube is short-circuited with the gate of the first PMOS tube and then connected with one end of the second resistor, The other end of the second resistor is connected to the drain of the first NMOS, the back gate of the first NMOS is connected to a signal ground, the source of the first NMOS is connected to one end of a third resistor, and the other end of the third resistor is connected to the gate of the first NMOS, The back gate of the second PMOS is short-circuited to the source of the second PMOS, and the drain of the second PMOS is connected to the output of the operational amplifier, The gate of the third PMOS is connected to the output of the operational amplifier, the back gate of the third PMOS is short-circuited to the source of the third PMOS and then connected to one end of a first resistor, and the drain of the third PMOS is connected to the other end of the third resistor; The back gate of the fourth PMOS is short-circuited to the source of the fourth PMOS and then connected to a power input end, the drain of the fourth PMOS is connected to one end of the third resistor, one end of the fourth resistor is connected to one end of the third resistor, the other end of the fourth resistor is connected to the negative input end of the operational amplifier, one end of the fifth resistor is connected to the other end of the fourth resistor, the other end of the fifth resistor is connected to a signal ground, and the drain of the fourth PMOS is the output of the post-stage output unit.

10. A power supply system characterized by comprising: The linear voltage stabilizing protection device of claim 8 or 9. The linear voltage stabilizing protection device of claim 8 or 9.

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