Circuit for reducing electric leakage of digital circuit

Abstract

According to the circuit for reducing the electric leakage of the digital circuit, the substrate voltage of a PMOS device is biased, so that the voltage of the PMOS device is higher than the voltage of a first power supply, the back gate effect is increased, so that the threshold voltage of the PMOS device is increased to reduce the electric leakage, and meanwhile, the potential of a first grounding end connected with a source electrode of an NMOS tube group is increased; the potential difference between the substrate and the source electrode of the NMOS tube group is a negative number, the threshold voltage of the NMOS tube group can also be increased, and the mode can ensure that the whole digital circuit body works in a safe voltage range and does not face the risk that the circuit is broken down.

Description

Technical Field

[0001] The embodiments of this application belong to the field of circuit technology, and in particular relate to a circuit for reducing leakage current in digital circuits. Background Technology

[0002] Based on the power supply layout of traditional digital circuits and the substrate connection method of N / P transistors, the source and substrate of almost all devices are connected to the same node. There is no substrate bias voltage for this device, meaning the threshold voltage remains unchanged. In this case, the leakage current of the digital circuit depends entirely on the intrinsic characteristics of the device. To minimize leakage current in devices, the industry generally employs three common practices: 1) Selecting devices with higher threshold voltages. Generally, a higher threshold voltage can reduce leakage current. However, this approach is limited by the manufacturing process itself. If the process does not provide devices with high threshold voltages, or if further reduction in leakage current is desired after selecting devices with high threshold voltages, this approach is not feasible. 2) Reducing the power supply voltage. When the power supply voltage is reduced, the leakage current of digital circuits will also decrease. However, there is an upper limit to simply reducing the power supply voltage; it cannot be reduced indefinitely. If the power supply voltage is too low, it may cause abnormal operation of the logic circuit. 3) Biasing the substrate of the PMOS device separately, making its voltage higher than the power supply voltage, increases the back gate effect and increases the threshold voltage of the PMOS. If the substrate voltage is raised without limit, the devices used in the digital circuits may exceed the safe voltage range, facing the risk of breakdown. Summary of the Invention

[0003] In order to solve or alleviate the problems of the third solution in the prior art, the technical solution of this application can enable the devices used in digital circuits to not exceed the safe voltage range and not face the risk of breakdown.

[0004] This application provides a method for reducing leakage current in digital circuits, including: a digital circuit body and a bias voltage generating circuit;

[0005] The digital circuit body includes a PMOS transistor group and an NMOS transistor group;

[0006] The gate of the PMOS transistor group is connected to the gate of the NMOS transistor group, and the drain of the PMOS transistor group is connected to the drain of the NMOS transistor group.

[0007] One end of the bias voltage generating circuit is connected to the substrate of the PMOS transistor group, and the other end of the bias voltage generating circuit is connected to the first power supply. The first power supply provides a bias voltage to the substrate of the PMOS transistor group through the bias voltage generating circuit, and the bias voltage is greater than the voltage of the second power supply.

[0008] The source of the NMOS transistor group is connected to the first ground terminal, and the substrate of the NMOS transistor group is connected to the second ground terminal. The potential of the first ground terminal is higher than the potential of the second ground terminal.

[0009] As a preferred embodiment of this application, the circuit further includes: a first low-dropout linear regulator;

[0010] One end of the first low-dropout linear regulator and the source of the PMOS transistor group are both connected to the second power supply, and the other end of the first low-dropout linear regulator is connected to the first power supply. The first power supply provides voltage to the second power supply through the first low-dropout linear regulator.

[0011] In a preferred embodiment of this application, the circuit further includes: a second low-dropout linear regulator;

[0012] The second low-dropout linear regulator includes a first NMOS transistor and a first error amplifier;

[0013] The drain of the first NMOS transistor and the source of the NMOS transistor group are both connected to the first ground terminal. The drain of the first NMOS transistor is connected to the first input terminal of the first error amplifier. The second input terminal of the first error amplifier is connected to the reference voltage of the first ground terminal. The gate of the first NMOS transistor is connected to the output terminal of the first error amplifier. The source of the first NMOS transistor is connected to the second ground terminal.

[0014] In a preferred embodiment of this application, the circuit further includes a first switch and a second switch;

[0015] A first common terminal is provided between one end of the bias voltage generating circuit and the substrate of the PMOS transistor group; one end of the first switch is connected to the second power supply; and the other end of the first switch is connected to the first common terminal.

[0016] A second common terminal is provided between the gate of the first NMOS transistor and the output terminal of the first error amplifier; one end of the second switch is connected to the second power supply, and the other end of the second switch is connected to the second common terminal.

[0017] When both the first and second switches are closed, the substrate potential of the PMOS transistor group and the gate potential of the first NMOS transistor are the same as the potential of the second power supply; the potentials of the first ground terminal and the second ground terminal are the same.

[0018] When both the first and second switches are open, the substrate potential of the PMOS transistor group is the same as the output potential of the bias voltage generation circuit, and the bias voltage generation circuit provides a bias voltage to the substrate of the PMOS transistor group; the gate potential of the first NMOS transistor is the same as the output potential of the first error amplifier.

[0019] As a preferred embodiment of this application, it includes: a first low-dropout linear regulator comprising a second NMOS transistor and a second error amplifier;

[0020] The output terminal of the second error amplifier is connected to the gate of the second NMOS transistor, the source of the second NMOS transistor is connected to the first input terminal of the second error amplifier, the second input terminal of the second error amplifier is connected to the first power supply reference voltage, and the common node between the source of the second NMOS transistor and the first input terminal of the second error amplifier is connected to the second power supply.

[0021] As a preferred embodiment of this application, the bias voltage generating circuit is a third low-dropout linear regulator, including a third error amplifier and a third NMOS transistor;

[0022] The output terminal of the third error amplifier is connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is connected to the first input terminal of the third error amplifier, the second input terminal of the third error amplifier is connected to the bias voltage reference voltage, the drain of the third NMOS transistor is connected to the first power supply, and the common node between the source of the third NMOS transistor and the first input terminal of the second error amplifier is connected to the substrate of the PMOS transistor group.

[0023] In a preferred embodiment of this application, the difference between the bias voltage reference voltage and the first power supply reference voltage is equal to the second ground terminal reference voltage.

[0024] In a preferred embodiment of this application, the digital circuit body is one or more of an inverter, an OR gate, an AND gate, and a NOT gate.

[0025] Compared with the prior art, this application biases the voltage of the substrate of the PMOS transistor group to be higher than the voltage of the first power supply, thereby increasing the back gate effect and increasing the threshold voltage of the PMOS transistor group to reduce leakage current. At the same time, the potential of the first ground terminal connected to the source of the NMOS transistor group is too high, making it higher than the potential of the second ground terminal. In this way, the potential difference between the substrate and the source of the NMOS transistor group is also negative, which can also increase the threshold voltage of the NMOS transistor group. However, this method can ensure that the entire digital circuit works within a safe voltage range and will not face the risk of circuit breakdown. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0027] Figure 1 This application provides a circuit diagram for reducing leakage current in digital circuits. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0029] like Figure 1 As shown, this application provides a circuit for reducing leakage current in digital circuits, including: a digital circuit body 1 and a bias voltage generating circuit 2;

[0030] The digital circuit body 1 includes a PMOS transistor group 11 and an NMOS transistor group 12;

[0031] The gate of the PMOS transistor group 11 is connected to the gate of the NMOS transistor group 12, and the drain of the PMOS transistor group 11 is connected to the drain of the NMOS transistor group 12.

[0032] It should be noted that the PMOS transistor group 11 includes one PMOS transistor or multiple PMOS transistors connected in parallel, multiple PMOS transistors connected in series, or multiple PMOS transistors connected in series and parallel.

[0033] The NMOS transistor group 12 includes one NMOS transistor or multiple NMOS transistors in parallel, multiple NMOS transistors in series, or multiple NMOS transistors in series and parallel.

[0034] In this case, the gates of the PMOS transistors in the PMOS transistor group are not necessarily connected to the gates of the NMOS transistors in the NMOS transistor group, but the gate of one PMOS transistor in the PMOS transistor group will definitely be connected to the gate of one NMOS transistor in the NMOS transistor group.

[0035] One end of the bias voltage generating circuit 2 is connected to the substrate of the PMOS transistor group 11, and the other end of the bias voltage generating circuit 2 is connected to the first power supply 3. The first power supply 3 provides a bias voltage to the substrate of the PMOS transistor group 11 through the bias voltage generating circuit 2, and the bias voltage is greater than the voltage of the second power supply 6.

[0036] The source of the NMOS transistor group 12 is connected to the first ground terminal 4, and the substrate of the NMOS transistor group 12 is connected to the second ground terminal 5. The potential of the first ground terminal 4 is higher than the potential of the second ground terminal 5.

[0037] This application embodiment primarily increases the threshold voltage of the PMOS transistor group 11 by biasing its substrate voltage to be greater than that of the second power supply 6. This reduces leakage current in the digital circuit body 1, as a higher threshold voltage of the PMOS transistor group 11 results in less leakage. Simultaneously, by raising the potential of the first ground terminal 4, the potential difference between the source and substrate of the NMOS transistor group 12 is increased, further increasing the threshold voltage of the NMOS transistor group 12 and consequently reducing leakage current in the entire digital circuit body 1. Furthermore, when the NMOS transistor group 12 is on and the PMOS transistor group 11 is off, the potential difference between the substrate of the PMOS transistor group 11 and the source of the NMOS transistor group 12 is smaller than that in the three prior art solutions. This ensures that the entire digital circuit body 1 can still operate within a safe voltage range and will not face the risk of breakdown.

[0038] In a preferred embodiment of this application, the circuit further includes: a first low-dropout linear regulator 10;

[0039] One end of the first low-dropout linear regulator 10 and the source of the PMOS transistor group 11 are both connected to the second power supply 6. The other end of the first low-dropout linear regulator 10 is connected to the first power supply 3. The first power supply 3 provides voltage to the second power supply 6 through the first low-dropout linear regulator 10.

[0040] It should be noted that in this embodiment, the first low-dropout linear regulator 10 provides voltage to the digital circuit body 1. In this embodiment, the first power supply 3 is the main power supply, and the second power supply 6 is the digital circuit power supply for the digital circuit body 1. A low-dropout linear regulator (LDO) is a common voltage regulator used to stably convert a high-voltage input to a lower-voltage output.

[0041] As a preferred embodiment of this application, the circuit further includes: a second low-dropout linear regulator 7;

[0042] The second low-dropout linear regulator 7 includes a first NMOS transistor 72 and a first error amplifier 71;

[0043] The drain of the first NMOS transistor 72 and the source of the NMOS transistor group 12 are both connected to the first ground terminal 4. The drain of the first NMOS transistor 72 is connected to the first input terminal of the second error amplifier 10171. The second input terminal of the first error amplifier 71 is connected to the first ground terminal reference voltage 73. The gate of the first NMOS transistor 72 is connected to the output terminal of the first error amplifier 71. The source of the first NMOS transistor 72 is connected to the second ground terminal 5.

[0044] It should be noted that by adding a second low-dropout linear regulator 7, consisting of a first NMOS transistor 72 and a first error amplifier 71, the drain potential of the first NMOS transistor 72 can be raised. This not only increases the threshold voltage of the NMOS transistor group 12, thereby reducing the leakage current of the digital circuit body 1, but also ensures that the entire digital circuit body 1 can still operate within a safe voltage range and will not face the risk of breakdown.

[0045] In a preferred embodiment of this application, the circuit further includes a first switch 8 and a second switch 9;

[0046] A first common terminal is provided between one end of the bias voltage generating circuit 2 and the substrate of the PMOS transistor group 11. One end of the first switch 8 is connected to the second power supply 6, and the other end of the first switch 8 is connected to the first common terminal.

[0047] A second common terminal is provided between the gate of the first NMOS transistor 72 and the output terminal of the first error amplifier 71. One end of the second switch 9 is connected to the second power supply 6, and the other end of the second switch 9 is connected to the second common terminal.

[0048] When both the first switch 8 and the second switch 9 are closed, the substrate potential of the PMOS transistor group 11 and the gate potential of the first NMOS transistor 72 are the same as the potential of the second power supply 6; the potentials of the first ground terminal 4 and the second ground terminal 5 are the same.

[0049] When both the first switch 8 and the second switch 9 are open, the substrate potential of the PMOS transistor group 11 is the same as the output potential of the bias voltage generation circuit 2, and the bias voltage generation circuit 2 provides a bias voltage to the substrate of the PMOS transistor group 11; the gate potential of the first NMOS transistor 72 is the same as the output potential of the first error amplifier 71.

[0050] It should be noted that in the specific application of the digital circuit body 1, the first switch 8 and the second switch 9 enable the digital circuit body 1 to be applicable to both high-power and low-power operating scenarios. Under high-power operating conditions, the leakage current of the digital circuit body 1 can be ignored. When both the first switch 8 and the second switch 9 are closed, the substrate potential of the PMOS transistor group 11 and the gate potential of the first NMOS transistor 72 are the same as the potential of the second power supply 6. This disconnects the bias circuit to avoid generating a bias voltage. At the same time, the threshold voltage of the PMOS transistor group 11 is the original threshold voltage of the PMOS transistor group 11 itself. In addition, the first NMOS transistor 72 forms a conducting switch, providing a low-impedance path. Thus, the potential of the second ground terminal 5 is the same as the potential of the first ground terminal 4, and the threshold voltage of the NMOS transistor group 12 is the original threshold voltage of the NMOS transistor group 12 itself.

[0051] To ensure that the leakage current of the digital circuit body 1 cannot be ignored under low-power operating conditions, when both the first switch 8 and the second switch 9 are open, the substrate potential of the PMOS transistor group 11 is the same as the output potential of the bias voltage generation circuit 2. The bias voltage generation circuit 2 provides a bias voltage to the substrate of the PMOS transistor group 11. In this way, the leakage current of the PMOS transistor group 11 is reduced by increasing the threshold voltage of the PMOS transistor group 11. The leakage current of the NMOS transistor group 12 is reduced by increasing the potential of the first ground terminal 4. This also ensures that the entire digital circuit body 1 can still operate within a safe voltage range and will not face the risk of breakdown.

[0052] As a preferred embodiment of this application, the first low-dropout linear regulator 10 includes a second NMOS transistor 102 and a second error amplifier 101;

[0053] The output terminal of the second error amplifier 101 is connected to the gate of the second NMOS transistor 102, the source of the second NMOS transistor 102 is connected to the first input terminal of the second error amplifier 101, and the second input terminal of the second error amplifier 101 is connected to the first power supply reference voltage 103; the common node between the source of the second NMOS transistor 102 and the first input terminal of the second error amplifier 101 is connected to the second power supply 6.

[0054] It should be noted that the first low-dropout linear regulator 10 mainly provides voltage to the digital circuit body 1, and can reduce the voltage of the second power supply 6. When the voltage of the second power supply 6 is reduced, the leakage current of the digital circuit body 1 will also decrease.

[0055] As a preferred embodiment of this application, the bias voltage generating circuit 2 is a third low-dropout linear regulator, including a third error amplifier 21 and a third NMOS transistor 22;

[0056] The output terminal of the third error amplifier 21 is connected to the gate of the third NMOS transistor, the source of the third NMOS transistor 22 is connected to the first input terminal of the third error amplifier 21, and the second input terminal of the third error amplifier 21 is connected to the bias voltage reference voltage 23; the drain of the third NMOS transistor 22 is connected to the first power supply 3; the common node between the source of the third NMOS transistor 22 and the first input terminal of the third error amplifier 21 is connected to the substrate of the PMOS transistor group 11.

[0057] It should be noted that the second low-dropout linear regulator 7 mainly provides bias voltage for the substrate of the PMOS transistor group 11.

[0058] In a preferred embodiment of this application, the difference between the bias voltage reference voltage 23 and the first power supply reference voltage 103 is equal to the first ground terminal reference voltage 73.

[0059] It should be noted that as long as the difference between the bias voltage reference voltage 23 and the first power supply reference voltage 103 is equal to the first ground terminal reference voltage 73, the digital circuit body 1 can avoid the risk of breakdown caused by overvoltage, and at the same time reduce the voltage of the second power supply 6; substrate biasing of PMOS transistor group 11 and NMOS transistor group 12 increases the threshold voltage of PMOS transistor group 11, thereby reducing the leakage current of digital circuit body 1 in low power consumption scenarios without risk.

[0060] In a preferred embodiment of this application, the digital circuit body 1 is one or more of an inverter, an OR gate, an AND gate, and a NOT gate.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A circuit for reducing leakage current in a digital circuit, comprising: The circuit comprises: a digital circuit body and a bias voltage generating circuit; the digital circuit body comprises a PMOS tube group and an NMOS tube group; the gate of the PMOS tube group is connected with the gate of the NMOS tube group, and the drain of the PMOS tube group is connected with the drain of the NMOS tube group; one end of the bias voltage generating circuit is connected with the substrate of the PMOS tube group, and the other end of the bias voltage generating circuit is connected with a first power supply, the first power supply provides a bias voltage for the substrate of the PMOS tube group through the bias voltage generating circuit, and the bias voltage is greater than the voltage of a second power supply; the source of the NMOS tube group is connected with a first ground end, and the substrate of the NMOS tube group is connected with a second ground end, the potential of the first ground end is higher than the potential of the second ground end.

2. A circuit for reducing leakage current in a digital circuit as recited in claim 1, wherein, The circuit further comprises a first low-dropout linear voltage regulator; one end of the first low-dropout linear voltage regulator and the source of the PMOS tube group are both connected with the second power supply, and the other end of the first low-dropout linear voltage regulator is connected with the first power supply, the first power supply provides a voltage for the second power supply through the first low-dropout linear voltage regulator.

3. A circuit for reducing leakage current in a digital circuit as recited in claim 1, wherein, The circuit further comprises a second low-dropout linear voltage regulator; the second low-dropout linear voltage regulator comprises a first NMOS tube and a first error amplifier; the drain of the first NMOS tube and the source of the NMOS tube group are both connected with the first ground end, the drain of the first NMOS tube is connected with the first input end of the first error amplifier, the second input end of the first error amplifier is connected with a first ground end reference voltage; the gate of the first NMOS tube is connected with the output end of the first error amplifier, and the source of the first NMOS tube is connected with the second ground end.

4. A circuit for reducing leakage current in a digital circuit as recited in claim 3, wherein, The circuit further comprises a first switch and a second switch; one end of the bias voltage generating circuit and the substrate of the PMOS tube group are provided with a first common end, one end of the first switch is connected with the second power supply, and the other end of the first switch is connected with the first common end; the gate of the first NMOS tube and the output end of the first error amplifier are provided with a second common end, one end of the second switch is connected with the second power supply, and the other end of the second switch is connected with the second common end; when the first switch and the second switch are both closed, the potential of the substrate of the PMOS tube group and the potential of the gate of the first NMOS tube are both the same as the potential of the second power supply; the potentials of the first ground end and the second ground end are the same; when the first switch and the second switch are both opened, the potential of the substrate of the PMOS tube group is the same as the potential of the output end of the bias voltage generating circuit, and the bias voltage for the substrate of the PMOS tube group is provided through the bias voltage generating circuit; the potential of the gate of the first NMOS tube is the same as the potential of the output end of the first error amplifier.

5. A circuit for reducing leakage current in a digital circuit as recited in claim 2, wherein, the first low-dropout linear voltage regulator comprises a second NMOS tube and a second error amplifier; The output terminal of the second error amplifier is connected to the gate of the second NMOS transistor, the source of the second NMOS transistor is connected to the first input terminal of the second error amplifier, the second input terminal of the second error amplifier is connected to the first power supply reference voltage, and the common node between the source of the second NMOS transistor and the first input terminal of the second error amplifier is connected to the second power supply.

6. A circuit for reducing leakage current in a digital circuit as recited in claim 5, wherein, The bias voltage generation circuit is a third low-dropout linear regulator, including a third error amplifier and a third NMOS transistor; The output terminal of the third error amplifier is connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is connected to the first input terminal of the third error amplifier, the second input terminal of the third error amplifier is connected to the bias voltage reference voltage, the drain of the third NMOS transistor is connected to the first power supply, and the common node between the source of the third NMOS transistor and the first input terminal of the third error amplifier is connected to the substrate of the PMOS transistor group.

7. A circuit for reducing leakage current in a digital circuit as defined in claim 6, wherein, The difference between the bias voltage reference voltage and the first power supply reference voltage is equal to the first ground terminal reference voltage.

8. A circuit for reducing leakage current in a digital circuit as claimed in any one of claims 1 to 7, wherein, The digital circuit body is one or more of an inverter, OR gate, AND gate, and NOT gate.

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