A trench power device and a method for manufacturing the same

Abstract

The application relates to a trench power device and a preparation method thereof, which comprises the following steps: providing a semiconductor substrate, forming an epitaxial layer on one side of the semiconductor substrate; forming a plurality of first trenches in the epitaxial layer; forming a first shielding area with a conductive type opposite to that of the epitaxial layer on the epitaxial layer at the side wall and the bottom of the first trench; forming a second shielding area with the same conductive type as that of the bottom of the first shielding area, which is connected with the bottom of the first shielding area and is arranged at intervals with the bottom of the epitaxial layer, on the epitaxial layer at the bottom of the first shielding area; forming a filling structure layer comprising a first dielectric layer and a second dielectric layer arranged in a stack in the first trench, the first dielectric layer covers the inner wall of the first trench, the second dielectric layer covers the first dielectric layer and fills the first trench, the second dielectric layer is a semiconductor material and its band gap width is not less than that of the epitaxial layer; forming a second trench between two adjacent first trenches; and forming a gate structure layer in the second trench. The trench power device and the preparation method thereof can significantly improve the withstand voltage level of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a trench power device and its fabrication method. Background Technology

[0002] With the increasing demand for high-efficiency, high-power-density, and high-reliability power conversion in fields such as new energy vehicles, renewable energy power generation, photovoltaic systems, energy storage devices, and rail transportation, traditional silicon-based power devices (such as silicon MOSFETs and IGBTs) are struggling to meet the development requirements of next-generation power electronic systems due to inherent limitations in voltage withstand capability, switching speed, and temperature resistance. Silicon carbide (SiC), with its high breakdown electric field, high thermal conductivity, and high electron saturation drift velocity, has become a key material for realizing high-performance power electronic devices. SiC-based MOSFETs, especially trench-gate structures, have become the mainstream technology in medium- and high-voltage applications due to their higher channel mobility and significantly increased cell density, which effectively reduces on-resistance and increases device power density.

[0003] However, the bottom of the trench in a trench-gate SiC MOSFET has a structural bend. Under high-voltage operating conditions, this area is prone to severe electric field concentration, causing the gate oxide layer covering it to be subjected to electric field stresses much higher than in other areas. This leads to reliability issues such as gate oxide breakdown, charge trapping, and interface state degradation, becoming the main bottleneck restricting the long-term stable operation of this type of device.

[0004] To alleviate electric field concentration at the bottom of the trench, existing technologies generally incorporate a deep ion implantation region at the bottom of the trench with a conductivity type opposite to that of the epitaxial layer. This disperses the local electric field, thereby reducing the electric field strength of the gate oxide layer and improving device reliability. Current deep ion region fabrication processes mainly include deep trench etching combined with implantation and high-energy ion implantation. The former requires etching trench structures with a large depth-to-width ratio, heavily relying on the precision of the etching equipment and thick, hard mask materials. This process is complex and prone to introducing sidewall roughness. While the latter eliminates the need for deep trench etching, it requires high-energy implantation equipment exceeding 200 keV, leading to high costs, severe lattice damage, and the need for subsequent high-temperature annealing. High-temperature annealing can also cause doping diffusion and interface state deterioration, affecting device yield and reliability.

[0005] In summary, existing electric field control schemes for trench gate SiC MOSFETs suffer from problems such as high equipment cost, complex processes, difficulty in damage repair, and insufficient reliability, making it difficult to meet the needs of large-scale applications of high-performance SiC devices. Therefore, a new device structure and fabrication method are urgently needed to overcome the limitations of existing technologies. Summary of the Invention

[0006] Therefore, it is necessary to provide a trench power device and its fabrication method to address the problems of complex processes, high equipment requirements, severe lattice damage, and limited device reliability in existing trench gate MOS technologies.

[0007] To achieve the above objectives, this application provides a method for fabricating a trench-type power device, comprising the following steps:

[0008] A semiconductor substrate is provided, and an epitaxial layer is formed on one side of the semiconductor substrate;

[0009] Multiple spaced first trenches are formed within the epitaxial layer;

[0010] Ion implantation is performed on the epitaxial layer located on the sidewalls and bottom of the first trench to form a first shielding region, the conductivity type of the first shielding region being opposite to that of the epitaxial layer;

[0011] Ion implantation is performed in the epitaxial layer located at the bottom of the first shielding region to form a second shielding region, wherein the top of the second shielding region is connected to the bottom of the first shielding region, the implantation depth of the second shielding region is greater than the implantation depth of the first shielding region, the doping concentration of the first shielding region is greater than the doping concentration of the second shielding region, and the first shielding region and the second shielding region have the same conductivity type, and the bottom of the second shielding region is spaced apart from the bottom of the epitaxial layer.

[0012] A filling structure layer is formed in the first trench. The filling structure layer includes a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer covers the inner wall of the first trench, and the second dielectric layer covers the first dielectric layer and fills the first trench. The second dielectric layer is a semiconductor material and the band gap of the second dielectric layer is not less than the band gap of the epitaxial layer.

[0013] A second trench is formed between two adjacent first trenches;

[0014] A gate structure layer is formed within the second trench.

[0015] In one embodiment, forming a filling structure layer within the first trench includes:

[0016] A first dielectric material layer is formed to cover the inner wall of the first trench and to be located on the side of the epitaxial layer away from the semiconductor substrate;

[0017] A second dielectric material layer is formed to fill the first trench and cover the first dielectric material layer;

[0018] The first dielectric material layer and the second dielectric material layer located on the side of the epitaxial layer away from the semiconductor substrate are removed to obtain the first dielectric layer and the second dielectric layer. The first dielectric layer covers the sidewall of the first trench, and the second dielectric layer covers the first dielectric layer and fills the first trench. The first dielectric layer and the second dielectric layer form the filling structure layer.

[0019] In one embodiment, the epitaxial layer is made of silicon carbide; the first dielectric layer is made of silicon dioxide or silicon nitride; and the second dielectric layer is made of silicon carbide, gallium nitride, gallium oxide, or diamond.

[0020] In one embodiment, forming a second trench between two adjacent first trenches includes:

[0021] A patterned first photoresist layer is formed, wherein the first photoresist layer masks the filling structure layer and exposes the epitaxial layer located between two adjacent first trenches;

[0022] Based on the patterned first photoresist layer, the epitaxial layer exposed between two adjacent first trenches is etched to obtain the second trench;

[0023] Remove the patterned first photoresist layer.

[0024] In one embodiment, the step of performing ion implantation in the epitaxial layer located at the bottom of the first shielding region to form a second shielding region includes:

[0025] The semiconductor substrate is adjusted to tilt at a preset angle, wherein the preset angle is set according to the crystal orientation of the epitaxial layer;

[0026] Based on the preset angle and using a preset injection temperature, a second shielding area is formed in the epitaxial layer at the bottom of the first trench. The preset injection temperature ranges from 20°C to 30°C, and the preset angle ranges from 4°C to 8°C.

[0027] In one embodiment, after forming the gate structure layer in the second trench, the method further includes:

[0028] A first electrode layer electrically connected to the first shielding region and a second electrode layer electrically connected to the gate structure layer are formed;

[0029] A third electrode layer is formed on the side of the semiconductor substrate away from the epitaxial layer.

[0030] In one embodiment, the formation of a first electrode layer electrically connected to the first shielding region and a second electrode layer electrically connected to the gate structure layer includes:

[0031] An interlayer dielectric layer is formed on the side of the epitaxial layer away from the semiconductor substrate;

[0032] A first contact hole and a second contact hole are sequentially formed in the interlayer dielectric layer, wherein the bottom of the first contact hole exposes the first shielding area, and the bottom of the second contact hole exposes the gate structure layer;

[0033] An electrode material layer is formed that fills the first contact hole and the second contact hole and is located on the side of the interlayer dielectric layer away from the semiconductor substrate;

[0034] The electrode material layer located on the side of the interlayer dielectric layer away from the semiconductor substrate is etched to separate the electrode material layer electrically connected to the first shielding region and the electrode material layer electrically connected to the gate structure layer. The etched electrode material layer electrically connected to the first shielding region serves as the first electrode layer, and the electrode material layer electrically connected to the gate structure layer serves as the second electrode layer.

[0035] In one embodiment, forming a third electrode layer on the side of the semiconductor substrate away from the epitaxial layer includes:

[0036] The side of the semiconductor substrate away from the epitaxial layer is thinned.

[0037] The third electrode layer is formed on the surface of the thinned semiconductor substrate.

[0038] In one embodiment, before forming a plurality of spaced-apart first trenches within the epitaxial layer, the method further includes:

[0039] Ion implantation is performed on the upper surface of the epitaxial layer to obtain a well region, wherein the conductivity type of the well region is opposite to that of the epitaxial layer, and the first trench penetrates the well region.

[0040] Ion implantation is performed on the upper surface layer of the well region to obtain a source region, the source region having the opposite conductivity type to the well region, and the first electrode layer is electrically connected to the source region.

[0041] This application also provides a trench-type power device, which is prepared by the trench-type power device preparation method described in any of the above embodiments.

[0042] The aforementioned trench-type power device and its fabrication method form a filling structure layer within a first trench. This filling structure layer comprises a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer covers the inner wall of the first trench, and the second dielectric layer covers the first dielectric layer and fills the first trench. The second dielectric layer is a semiconductor material, and its bandgap is not less than that of the epitaxial layer. This structure enables more precise and efficient modulation of the electric field in the trench region, particularly at the bottom corner of the gate trench. Utilizing the potential modulation characteristics of wide-bandgap semiconductor materials, the internal electric field of the device can be more uniformly and flattened in both the lateral and longitudinal directions, effectively suppressing local electric field peaks at the bottom of the trench. This significantly reduces the maximum electric field stress borne by the gate oxide layer, improving its long-term reliability and overall withstand voltage level. Simultaneously, this filling structure layer possesses high thermal conductivity and structural stability, effectively reducing the thermal resistance of the trench region, improving the device's heat dissipation capacity, increasing power density, and reducing thermal stress accumulation during operation. This results in higher mechanical robustness and longer service life for the device under harsh conditions such as high temperature and high power cycling. Furthermore, by first forming a first shielding region in the sidewalls and bottom epitaxial layer of the first trench, and then forming a second shielding region connected to the bottom of the first shielding region, not only is the connection process simpler and the connection tighter, but the electric field modulation capability at the bottom of the trench is also significantly improved, the synergistic effect between the shielding regions is enhanced, and the interface transition and defects between different doped regions are effectively reduced, thereby improving the local electric field homogenization level and the stability of the conductive path. This structure can further improve the device's breakdown voltage, reduce leakage current, and enhance overall operational stability. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a flowchart of a method for fabricating a trench-type power device provided in one embodiment;

[0045] Figure 2 This is a schematic diagram of the cross-sectional structure after the source region is formed in the fabrication method of the trench-type power device provided in one embodiment;

[0046] Figure 3 This is a schematic diagram of the cross-sectional structure after the first trench is formed in the fabrication method of the trench-type power device provided in one embodiment;

[0047] Figure 4This is a schematic cross-sectional view of the structure after the first shielding region is formed in the fabrication method of the trench-type power device provided in one embodiment;

[0048] Figure 5 This is a schematic diagram of the cross-sectional structure after the second shielding region is formed in the fabrication method of the trench-type power device provided in one embodiment;

[0049] Figure 6 This is a schematic diagram of the cross-sectional structure after removing the first hard mask layer in the fabrication method of the trench-type power device provided in one embodiment;

[0050] Figure 7 This is a schematic cross-sectional view of the structure after the first dielectric material layer is formed in the fabrication method of the trench-type power device provided in one embodiment;

[0051] Figure 8 This is a schematic diagram of the cross-sectional structure after the formation of the second dielectric material layer in the fabrication method of the trench-type power device provided in one embodiment;

[0052] Figure 9 This is a schematic cross-sectional view of the trench power device fabrication method provided in one embodiment after the formation of the filling structure layer;

[0053] Figure 10 This is a schematic cross-sectional view of the patterned first photoresist layer after it has been formed in a method for fabricating a trench-type power device according to one embodiment.

[0054] Figure 11 This is a schematic diagram of the cross-sectional structure after the second trench is formed in the fabrication method of the trench-type power device provided in one embodiment;

[0055] Figure 12 This is a schematic cross-sectional view of the structure after the gate oxide layer is formed in the fabrication method of the trench power device provided in one embodiment;

[0056] Figure 13 This is a schematic cross-sectional view of the structure after the gate layer is formed in the fabrication method of the trench power device provided in one embodiment;

[0057] Figure 14 This is a schematic cross-sectional view of the trench power device fabrication method provided in one embodiment after forming the interlayer dielectric layer and the first contact hole;

[0058] Figure 15 This is a schematic diagram of the cross-sectional structure after the formation of the first ohmic contact layer in the fabrication method of the trench-type power device provided in one embodiment;

[0059] Figure 16 This is a schematic diagram of the cross-sectional structure after the first electrode layer is formed in the fabrication method of the trench-type power device provided in one embodiment.

[0060] Explanation of reference numerals in the attached figures:

[0061] 1-Semiconductor substrate, 2-Epipolar layer, 21-Well region, 22-Source region, 23-First hard mask layer, 24-First photoresist layer, 25-Interlayer dielectric layer, 251-First contact hole, 26-First ohmic contact layer, 3-First trench, 4-First shielding region, 5-Second shielding region, 6-Fill structure layer, 61-First dielectric layer, 611-First dielectric material layer, 62-Second dielectric layer, 621-Second dielectric material layer, 7-Second trench, 8-Gate structure layer, 81-Gate oxide layer, 82-Gate layer, 9-First electrode layer. Detailed Implementation

[0062] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0065] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0066] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0067] Please see Figure 1 This application provides a method for fabricating a trench-type power device, comprising the following steps:

[0068] Step S1: Provide a semiconductor substrate 1, and form an epitaxial layer 2 on one side of the semiconductor substrate 1;

[0069] Step S2: Form a plurality of spaced first trenches 3 within the epitaxial layer 2;

[0070] Step S3: Ion implantation is performed on the epitaxial layer 2 located on the sidewall and bottom of the first trench 3 to form a first shielding region 4. The conductivity type of the first shielding region 4 is opposite to that of the epitaxial layer 2.

[0071] Step S4: Ion implantation is performed in the epitaxial layer 2 located at the bottom of the first shielding region 4 to form a second shielding region 5, wherein the top of the second shielding region 5 is connected to the bottom of the first shielding region 4, the implantation depth of the second shielding region 5 is greater than the implantation depth of the first shielding region 4, the doping concentration of the first shielding region 4 is greater than the doping concentration of the second shielding region 5, and the first shielding region 4 and the second shielding region 5 have the same conductivity type, and the bottom of the second shielding region 5 is spaced apart from the bottom of the epitaxial layer 2.

[0072] Step S5: A filling structure layer 6 is formed in the first trench 3. The filling structure layer 6 includes a first dielectric layer 61 and a second dielectric layer 62 stacked together. The first dielectric layer 61 covers the inner wall of the first trench 3, and the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3. The second dielectric layer 62 is a semiconductor material and the band gap of the second dielectric layer 62 is not less than the band gap of the epitaxial layer 2.

[0073] Step S6: Form a second groove 7 between two adjacent first grooves 3;

[0074] Step S7: Form a gate structure layer 8 in the second trench 7.

[0075] In the above example, by forming a filling structure layer 6 within the first trench 3, the filling structure layer 6 includes a first dielectric layer 61 and a second dielectric layer 62 stacked together. The first dielectric layer 61 covers the inner wall of the first trench 3, and the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3. The second dielectric layer 62 is a semiconductor material, and the bandgap width of the second dielectric layer 62 is not less than the bandgap width of the epitaxial layer 2. This structure enables more precise and efficient modulation of the electric field in the trench region, especially at the bottom corner of the gate trench. Utilizing the potential modulation characteristics of wide-bandgap semiconductor materials, the electric field inside the device can be distributed more uniformly and flattened in both the lateral and longitudinal directions, effectively suppressing local electric field peaks at the bottom of the trench. This significantly reduces the maximum electric field stress borne by the gate oxide layer 81, improving the long-term reliability and overall withstand voltage level of the gate oxide layer 81. Meanwhile, this filling structure exhibits high thermal conductivity and structural stability, effectively reducing the thermal resistance of the trench region, improving device heat dissipation, increasing power density, and reducing thermal stress accumulation during operation. This results in higher mechanical robustness and longer lifespan for the device under harsh conditions such as high temperature and high power cycling. Furthermore, by sequentially forming a first shielding region 4 and a second shielding region 5 connected to its bottom in the sidewalls and bottom epitaxial layer 2 of the first trench 3, the two are structurally continuously connected. This not only significantly enhances the electric field modulation capability at the bottom of the trench and strengthens the synergistic effect between the shielding regions, but also effectively reduces interface transitions and defects between different doped regions, improving the local electric field homogenization level and conductivity path stability. This structure further enhances the device's withstand voltage, reduces leakage current, and strengthens overall operational stability.

[0076] Specifically, please refer to Figures 2 to 3 Steps S1 to S2 are performed, a semiconductor substrate 1 is provided, an epitaxial layer 2 is formed on one side of the semiconductor substrate 1, and a plurality of spaced first trenches 3 are formed in the epitaxial layer 2.

[0077] In one embodiment, the semiconductor substrate 1 is made of silicon carbide, such as a 4H-SiC single-crystal substrate. Compared to traditional silicon substrates, silicon carbide materials have higher breakdown electric field strength, higher thermal conductivity, wider bandgap, and better radiation resistance, and can maintain stable electrical properties under high temperature, high pressure, and high frequency environments. Therefore, using SiC as the substrate material for devices can significantly improve the breakdown voltage, switching speed, and power density of power devices, making it particularly suitable for the fabrication and application of medium- and high-voltage power devices.

[0078] In one embodiment, the epitaxial layer 2 is formed on the surface of the semiconductor substrate 1 by an epitaxial growth process. The epitaxial layer can be prepared using epitaxial technologies suitable for silicon carbide materials, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), or thermal plasma-enhanced epitaxy. The specific process can be selected according to equipment conditions, device performance indicators, and cost requirements.

[0079] To ensure the structural stability and electrical performance consistency of the device, the material of epitaxial layer 2 is consistent with that of semiconductor substrate 1, both using silicon carbide. Achieving lattice constant matching through the same material system can significantly reduce the stress at the substrate-epitaxy interface and decrease the interface defect density, thereby improving the long-term reliability and performance stability of the device.

[0080] Furthermore, the epitaxial layer 2 and the semiconductor substrate 1 have the same conductivity type, both possessing the first conductivity type. The doping element is nitrogen (N), and the doping concentration is controlled at 1 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 Within this range, the doping concentration design can precisely match the structural requirements of superjunction devices, providing a foundation for the subsequent formation of superjunction structures and the realization of low on-resistance characteristics of devices.

[0081] In addition, the thickness of epitaxial layer 2 can be designed according to the target breakdown voltage. By adjusting the thickness of the epitaxial layer, it can be ensured that the device can withstand the required high voltage load under actual working conditions, thereby meeting the withstand voltage performance requirements under different application scenarios.

[0082] In one embodiment, such as Figure 2 As shown, before forming a plurality of spaced-apart first trenches 3 within the epitaxial layer 2, the method further includes:

[0083] Ion implantation is performed on the upper surface of epitaxial layer 2 to form well region 21. The conductivity type of well region 21 is opposite to that of epitaxial layer 2; epitaxial layer 2 has the first conductivity type, while well region 21 has the second conductivity type. The dopant element used in well region 21 is aluminum (Al), and the doping concentration is controlled at 1×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 Within the range, the well region 21 is the key channel formation region of the device. When a suitable bias voltage is applied to the gate, a conductive channel can be induced to form in the well region, providing a stable and low-resistance channel for charge carriers. It is an important structural unit for realizing the switching function of the device.

[0084] Ion implantation is further performed on the upper surface layer of well region 21 to form source region 22. Source region 22 has the same first conductivity type as epitaxial layer 2, and the doping element is nitrogen, with the doping concentration controlled at 1×10⁻⁶.19 cm -3 ~1×10 21 cm -3 Within the highly doped range, the highly doped source region 22 can establish an ohmic contact with the subsequently formed electrode layer with low contact resistance, thereby effectively reducing the series resistance of the source region, improving the on-state performance of the device, and reducing conduction losses.

[0085] In one embodiment, before performing ion implantation on the upper surface of the epitaxial layer 2 to form the well region 21, the method further includes:

[0086] A patterned second hard mask layer (not shown) is formed on the side of the epitaxial layer 2 away from the semiconductor substrate 1. The subsequent ion implantation steps for forming the well region 21 and the source region 22 are based on this second hard mask layer to achieve precise definition of the implantation region.

[0087] The formation of the patterned second hard mask layer includes:

[0088] A second hard mask material layer (not shown) is deposited on the side of the epitaxial layer 2 away from the semiconductor substrate 1. The material can be silicon nitride, silicon dioxide or other mask materials with high etching resistance and high selectivity.

[0089] A patterned second photoresist layer (not shown) is formed on the second hard mask material layer. Through photolithography exposure and development processes, the second photoresist layer forms a patterned structure corresponding to the distribution and size of the device's cell regions.

[0090] Using a patterned second photoresist layer as a mask, the second hard mask material layer is etched to obtain a patterned second hard mask layer. The etching method of the second hard mask material layer can be dry etching or other suitable etching processes to ensure accurate transfer of the mask pattern.

[0091] Remove the patterned second photoresist layer. The photoresist can be removed by dry etching, wet etching or other appropriate methods. It should be noted that the patterned first hard mask layer only covers the terminal region of the device, while the cell regions used for subsequent ion implantation are fully exposed to ensure precise control over the implantation position, size and depth of the well region 21 and the source region 22.

[0092] In one embodiment, after ion implantation of the upper surface layer of the well region 21 to form the source region 22, the method further includes:

[0093] The second hard mask layer is removed. The removal method can be wet etching or other suitable etching methods for the mask material to avoid affecting the subsequent etching process of the first trench 3. During the removal process, it is necessary to ensure that the hard mask material is completely removed to avoid any mask residue. Simultaneously, it is crucial to prevent etching damage or surface defects on the already formed source region 22 surface, thereby ensuring the interface quality and device reliability of subsequent processes.

[0094] It should be noted that in this embodiment, the first conductivity type and the second conductivity type are opposite to each other; that is, when the first conductivity type is N-type, the second conductivity type is P-type; and when the first conductivity type is P-type, the second conductivity type is N-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0095] In one embodiment, such as Figure 3 As shown, a plurality of spaced first trenches 3 are formed within the epitaxial layer 2, including:

[0096] A patterned first hard mask layer 23 is formed on one side of the epitaxial layer 2. The first hard mask layer 23 is used to define the location and size of the first trench 3 and to provide high selectivity etching protection during subsequent deep trench etching.

[0097] The first hard mask layer 23 forming the pattern includes:

[0098] A first hard mask material layer is deposited on one side of the epitaxial layer 2. The material of the first hard mask material layer includes silicon nitride, silicon dioxide, or other materials with high etch selectivity and good etch resistance, so as to ensure that the pattern of the first trench 3 can be accurately transferred to the epitaxial layer 2 during the etching process.

[0099] A third photoresist layer (not shown) is formed on the first hard mask material layer, and patterned by photolithography exposure and development process. The resulting pattern is consistent with the layout and size of the first trench 3 to be formed.

[0100] Using a patterned third photoresist layer as a mask, the first hard mask material layer is etched to form a patterned first hard mask layer 23. The etching method can be dry etching or other suitable etching processes to ensure accurate transfer of the mask pattern.

[0101] The patterned second photoresist layer is removed by dry etching, wet etching, or a combination of both to avoid photoresist residue affecting subsequent etching processes.

[0102] Based on the patterned first hard mask layer 23, the epitaxial layer 2 is etched to form a first trench 3. The etching of the epitaxial layer 2 can be performed using dry etching or other suitable methods. The first trench 3 formed by etching does not penetrate the epitaxial layer 2 in depth, but at least penetrates the well region 21, such that the bottom of the trench is spaced apart from the bottom of the epitaxial layer 2. It should be noted that the depth of the first trench 3 can be flexibly determined according to the device structure design and electric field control requirements; this embodiment does not impose specific limitations on this.

[0103] Specifically, please refer to Figure 4 Step S3 is executed, in which ion implantation is performed on the epitaxial layer 2 located on the sidewall and bottom of the first trench 3 to form a first shielding region 4. The conductivity type of the first shielding region 4 is the same as that of the epitaxial layer 2.

[0104] In one embodiment, such as Figure 4 As shown, ion implantation is performed on the epitaxial layer 2 located on the sidewalls and bottom of the first trench 3 to form a first shielding region 4, including:

[0105] The semiconductor substrate 1 is tilted, and high-temperature ion implantation is performed on the epitaxial layer 2 located on the sidewalls and bottom of the first trench 3. The tilt angle of the semiconductor substrate 1 is set according to the opening depth and opening size of the first trench 3 and the thickness of the second hard mask layer to ensure that the ion implantation can accurately reach the sidewalls and bottom regions of the first trench 3. The specific value of the tilt angle can be flexibly adjusted according to the actual structural parameters and is not limited here. The tilting of the semiconductor substrate 1 is achieved by adjusting the support stage supporting the semiconductor substrate 1. The first shielding region 4 has a second conductivity type, and the doping element of the first shielding region 4 is aluminum, with a doping concentration ranging from 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 Its conductivity type is opposite to that of epitaxial layer 2, and its doping concentration is extremely high. It can serve as a connection region for forming an ohmic contact with the source metal layer, ensuring low-resistance conduction between the electrode and the source region 22. The temperature range for high-temperature ion implantation is 450℃~550℃, which can be determined according to actual process conditions such as implantation depth requirements and lattice damage control targets.

[0106] Specifically, please refer to Figures 5 to 6 Step S4 is executed, in which ion implantation is performed in the epitaxial layer located at the bottom of the first shielding region 4 to form the second shielding region 5. The top of the second shielding region 5 is connected to the bottom of the first shielding region 4, the implantation depth of the second shielding region 5 is greater than the implantation depth of the first shielding region, the doping concentration of the first shielding region 4 is less than the doping concentration of the second shielding region 5, and the first shielding region 4 and the second shielding region 5 have the same conductivity type. The bottom of the second shielding region 5 is spaced apart from the bottom of the epitaxial layer 2.

[0107] In one embodiment, such as Figure 5 As shown, ion implantation is performed in the epitaxial layer 2 located at the bottom of the first shielding region 4 to form the second shielding region 5, including:

[0108] The semiconductor substrate 1 is adjusted to tilt it at a preset angle, wherein the preset angle is set according to the crystal orientation of the epitaxial layer 2;

[0109] Based on a preset angle and a preset injection temperature, a second shielding area 5 is formed in the epitaxial layer 2 at the bottom of the first trench 3. The preset injection temperature ranges from 20°C to 30°C, and the preset angle ranges from 4°C to 8°C.

[0110] Specifically, the ion implantation direction is aligned with the lattice channel of the crystal orientation of the epitaxial layer 2. For example, the (0001) plane of 4H-SiC is offset by 4 degrees along a specific direction, which can trigger a significant channel effect. The scattering resistance encountered by ions when moving along the channel between lattice atoms is greatly reduced, thereby achieving a deeper penetration depth at a lower implantation energy. This angle design can ensure the effective excitation of the channel effect and reduce the increase of lattice defects caused by excessive crystal orientation offset, taking into account both implantation depth and lattice integrity. The semiconductor substrate 1 is adjusted to tilt at a preset angle by adjusting the support stage that supports the semiconductor substrate 1 so that the semiconductor substrate 1 placed on the support stage is tilted at a preset angle.

[0111] The second shielding region 5 has a second conductivity type, and the doping element of the second shielding region 5 is aluminum, with a doping concentration ranging from 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 By using high concentrations of doping with the opposite conductivity type to the epitaxial layer 2, the electric field at the bottom of the first trench 3 can be effectively compensated, thus playing a shielding role. The preset implantation temperature range is 20℃~30℃, which is room temperature. Therefore, by adjusting the preset tilt angle of the semiconductor substrate 1, the channel effect is triggered, and a deeper second shielding region 5 can be formed without relying on a high-energy implanter, significantly reducing the requirements for implantation equipment and manufacturing costs.

[0112] The injection depth of the second shielding region 5 needs to be controlled within a specific range, and its bottom should be spaced apart from the bottom of the epitaxial layer 2 (i.e., it should not penetrate the epitaxial layer 2) to avoid damaging the pressure-resistant structure at the bottom of the epitaxial layer 2, while ensuring effective shielding of the electric field in the corner area at the bottom of the first trench 3, and protecting the gate oxide layer 81 from excessive electric field stress.

[0113] By first forming a first shielding region 4 and then a second shielding region 5, and by connecting the bottom of the first shielding region 4 with the top of the second shielding region 5, the connection process between the two is simplified, and a better structural continuity can be achieved. On the one hand, this can significantly improve the electric field modulation capability at the bottom of the trench and strengthen the synergistic effect of the shielding regions. On the other hand, it can effectively reduce the interface transition and defects of different doped regions, improve the local electric field homogenization level and the stability of the conductive path, so that the structure can further improve the device's withstand voltage capability, reduce leakage current, and enhance the overall working stability.

[0114] It should be noted that the ion implantation process of both the first shielding region 4 and the second shielding region 5 uses the previously formed patterned first hard mask layer 23 as a mask, without the need to prepare a new mask structure, which can simplify the process and reduce manufacturing costs.

[0115] In one embodiment, such as Figure 6 As shown, after ion implantation is performed in the epitaxial layer 2 located at the bottom of the first shielding region 4 to form the second shielding region 5, the process further includes:

[0116] The first hard mask layer 23 is removed. The first hard mask layer 23 can be removed by wet etching or other etching methods suitable for the mask material, so as to avoid affecting the subsequent etching process of the first trench 3.

[0117] In one embodiment, after ion implantation is performed on the epitaxial layer 2 located at the bottom of the first shielding region 4 to form the second shielding region 5, the method further includes:

[0118] High-temperature ion activation is performed. This mainly involves high-temperature ion activation of the epitaxial layer 2, the first shielding region 4, the second shielding region 5, the well region 21, and the source region 22, which are doped with ions, to activate the doped ions therein.

[0119] The high-temperature ion activation includes forming a protective layer (not shown) covering the exposed surface of the epitaxial layer 2. The protective layer includes a carbon film, which has excellent high-temperature resistance and chemical stability. It can effectively protect the surface of the epitaxial layer 2 and the trench structure from atmospheric corrosion or physical damage during the high-temperature activation process, while inhibiting the sublimation and decomposition of the silicon carbide material surface.

[0120] Under the protective layer, a high-temperature annealing process is performed to activate the doped ions. The high-temperature annealing temperature is 1750℃ and the time is 30 minutes. This allows the implanted ions to gain sufficient energy to escape from the interstitial positions of the crystal lattice and enter the substitutional positions of the silicon carbide crystal lattice, thereby achieving electroactive activation. This ensures that each doped region has the designed conductivity and carrier concentration. The annealing process is carried out in an argon atmosphere, which serves as an inert protective gas to prevent the device surface from reacting with oxygen, water vapor, etc. at high temperatures, and to reduce impurity contamination.

[0121] Through the above-mentioned high-temperature activation process, the doped region formed by previous ion implantation can be transformed from an inactive state to an electrically active state, ensuring that the well region 21 can effectively form a channel, the source region 22 can achieve a low-resistance ohmic contact, and the first shielding region 4 and the second shielding region 5 can perform electric field compensation functions, laying the foundation for the subsequent electrical performance of the device.

[0122] In one embodiment, after high-temperature ion activation, the method further includes: forming a sacrificial oxide layer (not shown) on the exposed surface of the epitaxial layer 2 away from the semiconductor substrate 1; the method of forming the sacrificial oxide layer includes thermal oxidation or other suitable methods, and the thickness of the sacrificial oxide layer can be controlled in the range of tens to hundreds of angstroms according to the degree of surface damage. The role of the sacrificial oxide layer is to adsorb and wrap the surface defects generated during high-temperature activation and trench etching, reduce the interface state density, and provide a high-quality substrate surface for the subsequent formation of the filling structure layer 6.

[0123] Removal of the sacrificial oxide layer. Methods for removing the sacrificial oxide layer include wet etching or other suitable methods.

[0124] Specifically, please refer to Figures 7 to 9 In step S5, a filling structure layer 6 is formed in the first trench 3. The filling structure layer 6 includes a first dielectric layer 61 and a second dielectric layer 62 stacked together. The first dielectric layer 61 covers the inner wall of the first trench 3, and the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3. The second dielectric layer 62 is a semiconductor material and the band gap of the second dielectric layer 62 is not less than the band gap of the epitaxial layer 2.

[0125] In one embodiment, such as Figures 7 to 9 As shown, a filling structure layer 6 is formed within the first trench 3, comprising:

[0126] A first dielectric material layer 611 is formed, covering the inner wall of the first trench 3 and located on the side of the epitaxial layer 2 away from the semiconductor substrate 1; wherein the method for forming the first dielectric material layer 611 includes chemical vapor deposition, thermal oxidation or other suitable methods;

[0127] A second dielectric material layer 621 is formed to fill the first trench 3 and cover the first dielectric material layer 611; the method for forming the second dielectric material layer 621 includes chemical vapor deposition, thermal oxidation or other suitable methods.

[0128] The first dielectric material layer 611 and the second dielectric material layer 621 located on the side of the epitaxial layer 2 away from the semiconductor substrate 1 are removed to obtain a first dielectric layer 61 and a second dielectric layer 62. The first dielectric layer 61 covers the sidewalls of the first trench 3, and the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3. The first dielectric layer 61 and the second dielectric layer 62 form a filled structure layer 6. The method for removing the first dielectric material layer 611 and the second dielectric material layer 621 located on the side of the epitaxial layer 2 away from the semiconductor substrate 1 includes chemical mechanical polishing, wet etching, dry etching, or other suitable methods.

[0129] In one embodiment, the material of the first dielectric layer 61 includes silicon dioxide, silicon nitride, or other suitable materials; the material of the second dielectric layer 62 includes silicon carbide, gallium nitride, gallium oxide, diamond, or other suitable semiconductor materials with a wide bandgap.

[0130] By forming a filling structure layer 6 within the first trench 3, the filling structure layer 6 includes a first dielectric layer 61 and a second dielectric layer 62 stacked together. The first dielectric layer 61 covers the inner wall of the first trench 3, and the second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3. The second dielectric layer 62 is a semiconductor material, and the bandgap width of the second dielectric layer 62 is not less than the bandgap width of the epitaxial layer 2. This structure enables more precise and efficient modulation of the electric field in the trench region, especially at the bottom corner of the second trench 7. Utilizing the potential modulation characteristics of wide bandgap semiconductor materials, the electric field inside the device can be distributed more uniformly and flattened in both the lateral and longitudinal directions, effectively suppressing local electric field peaks at the bottom of the trench. This significantly reduces the maximum electric field stress borne by the gate oxide layer, improving the long-term reliability and overall withstand voltage level of the gate oxide layer. Meanwhile, the filling structure layer 6 has high thermal conductivity and structural stability, which can effectively reduce the thermal resistance of the trench area, improve the heat dissipation capacity of the device, increase the power density, reduce the accumulation of thermal stress during operation, and enable the device to have higher mechanical robustness and service life under harsh conditions such as high temperature and high power cycling.

[0131] Specifically, when the material of the second dielectric layer 62 is silicon carbide, it is consistent with the material of the epitaxial layer 2, which can maximize the reduction of lattice mismatch and interface energy between the two, reduce the interface defect density, and at the same time, with the help of the excellent thermal stability and mechanical strength of silicon carbide, the thermal shock resistance and structural integrity of the filled structure layer 6 are further improved, avoiding interlayer delamination or cracking under high temperature conditions. When the material of the second dielectric layer 62 is gallium nitride, its wider bandgap and higher breakdown electric field strength can further enhance the electric field shielding effect of the trench region, especially suitable for high voltage and high frequency applications. At the same time, the good carrier mobility of gallium nitride can help optimize the charge transport efficiency of the device's conductive path, improving the withstand voltage performance while balancing the device's switching speed and conduction loss. When the second dielectric layer 62 is gallium oxide, its bandgap is wide. The strength far exceeds that of the epitaxial layer 2, which can form an extremely strong electric field constraint and shielding effect in the trench area, greatly reducing the electric field concentration phenomenon at the corners of the trench, especially suitable for high-voltage scenarios such as ultra-high voltage power transmission and transformation and high-voltage power distribution; when the material of the second dielectric layer 62 is diamond, it can achieve the ultimate shielding of the electric field in the trench area, completely solving the electric field distortion and leakage current problems in high-voltage scenarios, and is suitable for ultra-high voltage and extreme high-frequency device requirements. At the same time, diamond has ultra-high thermal conductivity, several times that of silicon carbide, which can quickly dissipate the heat generated by charge transport in the trench area, avoid device performance degradation caused by local overheating, greatly improve the thermal attenuation resistance of the filling structure layer 6, and the extremely strong mechanical strength of diamond can significantly enhance the wear resistance and impact resistance of the filling structure layer 6, effectively resist the mechanical stress during device fabrication and operation, and prevent microcracks from appearing between layers.

[0132] Specifically, please refer to Figures 10 to 11 Then, step S6 is executed to form a second groove 7 between two adjacent first grooves 3.

[0133] In one embodiment, such as Figures 10 to 11 As shown, a second groove 7 is formed between two adjacent first grooves 3, including:

[0134] A patterned first photoresist layer 24 is formed, wherein the first photoresist layer 24 masks the filling structure layer 6 and exposes the epitaxial layer 2 located between two adjacent first trenches 3; the patterned first photoresist layer 24 is formed by photolithography exposure and development process, and its pattern is consistent with the distribution and size of the second trenches 7 to be formed.

[0135] Based on the patterned first photoresist layer 24, the epitaxial layer 2 exposed between two adjacent first trenches 3 is etched to obtain the second trench 7. The method for etching the epitaxial layer 2 includes dry etching or other suitable methods.

[0136] The patterned first photoresist layer 24 is removed. The method for removing the first photoresist layer 24 includes dry etching, wet etching, or other suitable methods or a combination of both, to avoid residual photoresist affecting subsequent processes.

[0137] Specifically, please refer to Figures 12 to 16 Step S7 is executed to form a gate structure layer 8 in the second trench 7.

[0138] In one embodiment, such as Figures 12 to 13 As shown, a gate structure layer 8 is formed within the second trench 7, comprising:

[0139] A gate oxide layer 81 is formed covering the sidewalls of the second trench 7 and the side of the epitaxial layer 2 away from the semiconductor substrate 1; the material of the gate oxide layer 81 includes silicon dioxide or other suitable materials; the method of forming the gate oxide layer 81 includes thermal oxidation, chemical vapor deposition or other suitable methods to ensure that the gate oxide layer 81 has a uniform thickness, is dense and defect-free;

[0140] A gate oxide layer 81 is formed covering the sidewall of the second trench 7 and filling the second trench 7. The gate layer 82 is made of polysilicon or other suitable materials, and the gate layer 82 is formed by low-pressure chemical vapor deposition or other suitable methods. The deposition temperature of the gate layer 82 formed by low-pressure chemical vapor deposition is 620°C, the reaction gas is silane, and after deposition, the gate pattern is defined by photolithography exposure and development process, and then the excess gate material is removed by dry etching to obtain the target gate layer 82.

[0141] Remove the gate oxide layer 81 located on the side of the epitaxial layer 2 away from the semiconductor substrate 1.

[0142] In one embodiment, such as Figures 14 to 16 As shown, after forming the gate structure layer 8 within the second trench 7, the method further includes:

[0143] A first electrode layer 9 electrically connected to the first shielding region 4 and a second electrode layer electrically connected to the gate structure layer 8 are formed.

[0144] A third electrode layer is formed on the side of the semiconductor substrate 1 away from the epitaxial layer 2.

[0145] In one embodiment, forming a first electrode layer 9 electrically connected to the first shielding region 4 and a second electrode layer electrically connected to the gate structure layer 8 includes:

[0146] An interlayer dielectric layer 25 is formed on the side of the epitaxial layer 2 away from the semiconductor substrate 1. The method for forming the interlayer dielectric layer 25 includes chemical vapor deposition or other suitable methods, wherein the interlayer dielectric layer 25 has a double-layer structure, with the lower layer being silicon dioxide and the upper layer being phosphorus-doped silicon dioxide or boron- and phosphorus-doped silicon dioxide.

[0147] A first contact hole 251 and a second contact hole (not shown) are sequentially formed in the interlayer dielectric layer 25, wherein the bottom of the first contact hole 251 exposes the first shielding area 4, and the bottom of the second contact hole exposes the gate structure layer 8.

[0148] The first contact hole 251 and the second contact hole are sequentially formed within the interlayer dielectric layer 25, including:

[0149] The interlayer dielectric layer 25 is reflow planarized; the reflow planarization temperature of the interlayer dielectric layer 25 is 950℃, the time is 60 minutes, and it is carried out in a nitrogen atmosphere. High-temperature reflow can eliminate surface unevenness and provide a smooth process surface for subsequent contact hole etching and metal wiring.

[0150] A patterned fourth photoresist layer (not shown) is formed on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1.

[0151] Based on the patterned fourth photoresist layer, the interlayer dielectric layer 25 is etched sequentially to obtain the first contact hole 251 and the second contact hole. The method for etching the interlayer dielectric layer 25 includes dry etching or other suitable methods.

[0152] In addition, before forming the first contact hole 251 in the interlayer dielectric layer 25, the method further includes: forming a first ohmic contact layer 26 on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1;

[0153] A first ohmic contact layer 26 is formed on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1, including:

[0154] A first metal layer is formed on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1; the material of the first metal layer includes nickel or other suitable metal materials, and the method of forming the first metal layer includes physical vapor deposition or other suitable methods;

[0155] The metal layer is subjected to a first annealing treatment. The first metal layer reacts with the silicon element in the epitaxial layer 2 at a high temperature to form metal silicide. The temperature of the first annealing treatment is 750℃, the annealing time is 5min, and it is carried out in a nitrogen atmosphere.

[0156] Remove the unreacted first metal layer by wet etching;

[0157] The metal silicide is subjected to a second annealing treatment to form the first ohmic contact layer 26. The second annealing treatment is carried out at a temperature of 950°C and an annealing time of 3 min under a nitrogen atmosphere.

[0158] An electrode material layer is formed to fill the first contact hole 251 and the second contact hole and is located on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1; the electrode material layer is made of at least one of titanium, titanium nitride, and aluminum, and the method for forming the electrode material layer includes physical vapor deposition or other suitable methods;

[0159] The electrode material layer located on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1 is etched to separate the electrode material layer electrically connected to the second shielding region 5 and the electrode material layer electrically connected to the gate structure layer 8. The etched electrode material layer electrically connected to the first shielding region 4 is used as the first electrode layer 9, and the electrode material layer electrically connected to the gate structure layer 8 is used as the second electrode layer.

[0160] Etching is performed on the electrode material layer located on the side of the interlayer dielectric layer 25 away from the semiconductor substrate 1, including:

[0161] A patterned fifth photoresist layer (not shown) is formed on the side of the electrode material layer away from the semiconductor substrate 1.

[0162] Based on the patterned fifth photoresist layer, the electrode material layer is etched. The etching method for the electrode material layer includes dry etching or other suitable methods.

[0163] It should be noted that at this time, the first electrode layer 9 is also electrically connected to the source region 22. That is, the first electrode layer 9 is electrically connected to both the source region 22 and the first shielding region 4. This simplifies the process, achieves equipotential between the source region 22 and the first shielding region 4, strengthens the synergistic effect of electric field modulation, further reduces leakage current, improves withstand voltage stability, and also reduces the number of contact holes and metal wiring, shortens the process cycle, and reduces process costs and device failure risk.

[0164] In one embodiment, after forming a first electrode layer 9 electrically connected to the first shielding region 4 and a second electrode layer electrically connected to the gate structure layer 8, the method further includes:

[0165] A passivation layer (not shown) is formed covering the first electrode layer 9 and the second electrode layer. The passivation layer has a multi-layer structure to prevent oxidation of the electrode layers. Exemplarily, the passivation layer includes an insulating passivation layer and a flexible passivation layer stacked sequentially. The insulating passivation layer is made of silicon nitride or other suitable materials. The method for forming the insulating passivation layer includes plasma chemical vapor deposition or other suitable methods. It should be noted that, in order to avoid affecting the function of other areas of the trench-type power device, the insulating passivation layer only covers the area of ​​the first electrode layer 9 and the second electrode layer. Therefore, it also includes a step of dry etching the insulating passivation layer based on a patterned photoresist layer. The flexible passivation layer is made of polyimide or other suitable materials. The flexible passivation layer is formed by processes such as coating, exposure, development, and curing.

[0166] In one embodiment, a third electrode layer is formed on the side of the semiconductor substrate 1 away from the epitaxial layer 2, comprising:

[0167] The side of the semiconductor substrate 1 away from the epitaxial layer 2 is thinned; the method of thinning the semiconductor substrate 1 includes mechanical polishing, chemical mechanical polishing, dry etching or other suitable methods, so as to reduce the on-resistance and improve the heat dissipation performance and power density of the device.

[0168] A third electrode layer (not shown) is formed on the surface of the thinned semiconductor substrate 1. The material for forming the third electrode layer includes at least one of titanium, titanium nitride, aluminum, gold, and silver. The method for forming the third electrode layer includes metal vapor deposition or other suitable methods.

[0169] Before forming the third electrode layer on the surface of the thinned semiconductor substrate 1, the process further includes:

[0170] A second ohmic contact layer is formed on the surface of the thinned semiconductor substrate 1. The method for forming the second ohmic contact layer includes:

[0171] A second metal layer is formed on the surface of the thinned semiconductor substrate 1. The material of the second metal layer includes nickel or other suitable metal materials, and the method for forming the second metal layer includes physical vapor deposition or other suitable methods.

[0172] The second metal layer is laser annealed.

[0173] In one embodiment, this application also provides a trench-type power device, which is fabricated using the trench-type power device fabrication method described above, comprising: a semiconductor substrate 1, an epitaxial layer 2, a first trench 3, a first shielding region 4, a second shielding region 5, a filling structure layer 6, a second trench 7, and a gate structure layer 8, wherein the epitaxial layer 2 is located on one side of the semiconductor substrate 1; the first trench 3 includes a plurality of trenches spaced apart, and the first trench 3 is located within the epitaxial layer 2; the first shielding region 4 is located in the epitaxial layer 2 on the sidewalls and bottom of the first trench 3, and the conductivity type of the first shielding region 4 is opposite to that of the epitaxial layer 2; the second shielding region 5 is located in the epitaxial layer 2 at the bottom of the first shielding region 4, and the top of the second shielding region 5 is connected to the bottom of the first shielding region 4, and the second shielding region 7 is connected to the bottom of the first shielding region 4. The implantation depth of the second shielding region 5 is greater than that of the first shielding region 4. The doping concentration of the first shielding region 4 is greater than that of the second shielding region 5. The first shielding region 4 and the second shielding region 5 have the same conductivity type. The bottom of the second shielding region 5 is spaced apart from the bottom of the epitaxial layer 2. The filling structure layer 6 is located in the first trench 3. The filling structure layer 6 includes a first dielectric layer 61 and a second dielectric layer 62 stacked together. The first dielectric layer 61 covers the inner wall of the first trench 3. The second dielectric layer 62 covers the first dielectric layer 61 and fills the first trench 3. The second dielectric layer 62 is a semiconductor material and the band gap of the second dielectric layer 62 is not less than the band gap of the epitaxial layer 2. The second trench 7 is located between two adjacent first trenches 3. The gate structure layer 8 is located in the second trench 7.

[0174] In one embodiment, the trench power device further includes a well region 21 and a source region 22, wherein the well region 21 is located on the upper surface of the epitaxial layer 2, and the source region 22 is located on the upper surface of the well region 21.

[0175] In one embodiment, the trench power device further includes a first electrode layer 9, a second electrode layer, an interlayer dielectric layer 25, a first ohmic contact layer 26, a passivation layer, a second ohmic contact layer, and a third electrode layer. The first electrode layer 9 is electrically connected to the first shielding region 4, and the second electrode layer is electrically connected to the gate structure layer 8. The interlayer dielectric layer 25 is located on the side of the epitaxial layer 2 away from the semiconductor substrate 1. The interlayer dielectric layer 25 has a first contact hole 251 and a second contact hole. The bottom of the first contact hole 251 exposes the second shielding region 5, and the bottom of the second contact hole exposes the gate structure layer 8. The first electrode layer 9 fills the first contact hole 251, and the second electrode layer fills the second contact hole. The first ohmic contact layer 26 is located on the side of the first shielding region 4 and the source region 22 away from the semiconductor substrate 1, and is located in the first contact hole 251. The passivation layer covers the first electrode layer 9 and the second electrode layer. The second ohmic contact layer and the third electrode layer are stacked on the side of the semiconductor substrate 1 away from the epitaxial layer 2.

[0176] It should be understood that, although Figure 1The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0177] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0178] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0179] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a trench-type power device, characterized in that, Includes the following steps: A semiconductor substrate is provided, and an epitaxial layer is formed on one side of the semiconductor substrate; Multiple spaced first trenches are formed within the epitaxial layer; Ion implantation is performed on the epitaxial layer located on the sidewalls and bottom of the first trench to form a first shielding region, the conductivity type of the first shielding region being opposite to that of the epitaxial layer; Ion implantation is performed in the epitaxial layer located at the bottom of the first shielding region to form a second shielding region, wherein the top of the second shielding region is connected to the bottom of the first shielding region, the implantation depth of the second shielding region is greater than the implantation depth of the first shielding region, the doping concentration of the first shielding region is greater than the doping concentration of the second shielding region, and the first shielding region and the second shielding region have the same conductivity type, and the bottom of the second shielding region is spaced apart from the bottom of the epitaxial layer. A filling structure layer is formed within the first trench. The filling structure layer includes a first dielectric layer and a second dielectric layer stacked together. The first dielectric layer covers the inner wall of the first trench, and the second dielectric layer covers the first dielectric layer and fills the first trench. The second dielectric layer is a semiconductor material, and the bandgap of the second dielectric layer is not less than the bandgap of the epitaxial layer. The material of the epitaxial layer includes silicon carbide. The material of the first dielectric layer includes silicon dioxide and silicon nitride. The material of the second dielectric layer includes silicon carbide, gallium nitride, gallium oxide, and diamond. A second trench is formed between two adjacent first trenches; A gate structure layer is formed within the second trench.

2. The method for fabricating a trench-type power device according to claim 1, characterized in that, The formation of a filling structure layer within the first trench includes: A first dielectric material layer is formed to cover the inner wall of the first trench and to be located on the side of the epitaxial layer away from the semiconductor substrate; A second dielectric material layer is formed to fill the first trench and cover the first dielectric material layer; The first dielectric material layer and the second dielectric material layer located on the side of the epitaxial layer away from the semiconductor substrate are removed to obtain the first dielectric layer and the second dielectric layer. The first dielectric layer covers the sidewall of the first trench, and the second dielectric layer covers the first dielectric layer and fills the first trench. The first dielectric layer and the second dielectric layer form the filling structure layer.

3. The method for fabricating a trench-type power device according to claim 1, characterized in that, The process of forming a second trench between two adjacent first trenches includes: A patterned first photoresist layer is formed, wherein the first photoresist layer masks the filling structure layer and exposes the epitaxial layer located between two adjacent first trenches; Based on the patterned first photoresist layer, the epitaxial layer exposed between two adjacent first trenches is etched to obtain the second trench; Remove the patterned first photoresist layer.

4. The method for fabricating a trench-type power device according to claim 1, characterized in that, The step of performing ion implantation in the epitaxial layer located at the bottom of the first shielding region to form a second shielding region includes: The semiconductor substrate is adjusted to tilt at a preset angle, wherein the preset angle is set according to the crystal orientation of the epitaxial layer; Based on the preset angle and using a preset injection temperature, a second shielding area is formed in the epitaxial layer at the bottom of the first trench. The preset injection temperature ranges from 20°C to 30°C, and the preset angle ranges from 4°C to 8°C.

5. The method for fabricating a trench-type power device according to claim 1, characterized in that, After forming the gate structure layer in the second trench, the method further includes: A first electrode layer electrically connected to the first shielding region and a second electrode layer electrically connected to the gate structure layer are formed; A third electrode layer is formed on the side of the semiconductor substrate away from the epitaxial layer.

6. The method for fabricating a trench-type power device according to claim 5, characterized in that, The formation of a first electrode layer electrically connected to the first shielding region and a second electrode layer electrically connected to the gate structure layer includes: An interlayer dielectric layer is formed on the side of the epitaxial layer away from the semiconductor substrate; A first contact hole and a second contact hole are sequentially formed in the interlayer dielectric layer, wherein the bottom of the first contact hole exposes the first shielding area, and the bottom of the second contact hole exposes the gate structure layer; An electrode material layer is formed that fills the first contact hole and the second contact hole and is located on the side of the interlayer dielectric layer away from the semiconductor substrate; The electrode material layer located on the side of the interlayer dielectric layer away from the semiconductor substrate is etched to separate the electrode material layer electrically connected to the first shielding region and the electrode material layer electrically connected to the gate structure layer. The etched electrode material layer electrically connected to the first shielding region serves as the first electrode layer, and the electrode material layer electrically connected to the gate structure layer serves as the second electrode layer.

7. The method for fabricating a trench-type power device according to claim 5, characterized in that, The formation of a third electrode layer on the side of the semiconductor substrate away from the epitaxial layer includes: The side of the semiconductor substrate away from the epitaxial layer is thinned. The third electrode layer is formed on the surface of the thinned semiconductor substrate.

8. The method for fabricating a trench-type power device according to claim 5, characterized in that, Before forming a plurality of spaced-apart first trenches within the epitaxial layer, the method further includes: Ion implantation is performed on the upper surface of the epitaxial layer to obtain a well region, wherein the conductivity type of the well region is opposite to that of the epitaxial layer, and the first trench penetrates the well region. Ion implantation is performed on the upper surface layer of the well region to obtain a source region, the source region having the opposite conductivity type to the well region, and the first electrode layer is electrically connected to the source region.

9. A trench-type power device, characterized in that, The trench-type power device is prepared by the method for preparing a trench-type power device as described in any one of claims 1 to 8.

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