Synchronous triggering multi-finger ESD protection device

Abstract

The invention relates to a synchronous trigger multi-finger ESD protection device. A semiconductor device includes a first row of doped wells formed in a semiconductor body, the first row of doped wells including: first conductive type wells arranged alternately with second conductive type wells in a first direction of the semiconductor body; a first contact pad and a second contact pad disposed over an upper surface of the semiconductor body; a primary electrical interconnect network electrically coupling a semiconductor device structure formed by a set of first and second conductive type wells from the first row of doped wells between the first contact pad and the second contact pad; and a secondary electrical interconnect network forming nodes independent of the primary electrical interconnect network and electrically connecting together each of the first conductivity type wells in the first row.

Description

Technical Field

[0001] This application relates to semiconductor devices, and more particularly to electrostatic discharge protection devices. Background Technology

[0002] Components such as transistors, diodes, resistors, electro-optic devices, precision thin-film resistors, and various integrated circuits are sensitive to electrostatic discharge (ESD). As electronics manufacturers tend to miniaturize devices and increase operating speeds, device susceptibility to ESD increases. To prevent damage to integrated circuits or electronic devices from pulses during assembly or operation, ESD protection devices are connected between the pins of integrated circuits or traces on printed circuit boards to prevent faulting or breakdown of the circuitry connected between pins or traces caused by ESD current pulses. ESD protection devices are configured to be non-conductive under normal operating levels and become conductive in the presence of an overvoltage from an ESD event to divert damaging current from sensitive components.

[0003] In lateral ESD devices, current capability and clamping performance depend on the width of the device structure, which is defined as the dimension perpendicular to the current in the semiconductor device structure. High current capability requires a large total width, typically in the range of hundreds to thousands of micrometers. Generally, wide lateral devices are divided into multiple fingers of the same basic device design to achieve a compact design. Individual fingers are connected in parallel between two terminals. Each finger may include an elongated doped region (such as a heavily doped shallow region and a doped well) configured to operate as, for example, a thyristor, a silicon controlled rectifier, or a bipolar junction transistor. A multi-finger fast recovery device may include a triggering device configured to sense conduction by switching the multi-finger fast recovery device from a non-conductive state to a self-contained conductive state (locked state). It is desirable to create multi-finger devices with synchronous triggering behavior, such that each device finger is synchronously triggered, or, if not synchronously triggered, the current conduction condition is distributed from an already conductive finger to one or more other fingers that may not yet be synchronously triggered. For example, by shifting the potential distribution of the doped region from the triggered finger to the untriggered finger, the untriggered finger can be brought into a conductive state after the initial triggering conditions of the triggering device have ceased. Summary of the Invention

[0004] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings.

[0005] According to an embodiment, a semiconductor device includes: a first row of doped wells formed in an upper surface of a semiconductor body, the first row including first conductivity type wells alternately arranged with second conductivity type wells in a first direction of the semiconductor body; a first contact pad and a second contact pad disposed above the upper surface of the semiconductor body; a primary electrical interconnect network electrically coupling the first conductivity type wells and the second conductivity type wells of the first row between the first contact pad and the second contact pad; and a secondary electrical interconnect network forming nodes independent of the primary electrical interconnect network and electrically connecting each of the first conductivity type wells in the first row together.

[0006] According to one embodiment, a semiconductor device includes: a device comprising a plurality of silicon controlled rectifier devices connected in parallel and electrically coupled to an anode terminal and a cathode terminal via a primary electrical interconnect network, each of the silicon controlled rectifier devices including a trigger device and a secondary electrical interconnect network, the trigger device being configured to create a trigger current that puts the device into a conduction mode, the secondary electrical interconnect network forming nodes independent of the primary electrical interconnect network and electrically connecting doped regions together, the doped regions being part of or coupled to the terminals of each of the trigger devices. Attached Figure Description

[0007] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals identify corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0008] Figure 1 The diagram illustrates a plan view layout of an ESD protection device according to an embodiment.

[0009] Figure 2A and 2B The illustration shows the embodiment of the invention. Figure 1 A cross-sectional view of the ESD protection device. Figure 2A The diagram shows a cross-sectional view of the ESD protection device along the plane outside the trigger region. Figure 2B The figure shows a cross-sectional view of the ESD protection device along the plane intersecting the trigger region.

[0010] Figure 3A and 3B The diagram illustrates a plan view layout of an ESD protection device according to an embodiment. Figure 3A The diagram shows the overall plan view of the device. Figure 3B The diagram shows a close-up plan view of the device near a single finger, including the secondary electrical interconnect network and the trigger region.

[0011] Figure 4A and 4BThe figure shows a cross-sectional view of the ESD protection device of FIG3 according to an embodiment. Figure 4A The diagram shows a cross-sectional view of the ESD protection device along the plane outside the trigger region. Figure 4B The figure shows a cross-sectional view of the ESD protection device along the plane intersecting the trigger region.

[0012] Figure 5A and 5B An ESD protection device according to an embodiment is schematically illustrated. Figure 5A The diagram illustrates a device without a secondary electrical interconnect network. Figure 5B The diagram illustrates a device with a secondary electrical interconnect network.

[0013] Figure 6 The diagram illustrates a plan view layout of an ESD protection device according to an embodiment.

[0014] Figure 7A , 7B Figure 7C illustrates a plan view layout of an ESD protection device according to an embodiment.

[0015] Figure 8A , 8B 8C, 8D, 8E and 8F schematically illustrate ESD protection devices according to embodiments. Detailed Implementation

[0016] This document discloses embodiments of an ESD protection device. The ESD protection device is a multi-finger ESD protection device comprising a row of p-type and n-type wells arranged alternately. The p-type and n-type wells form ESD protection device segments and a primary electrical interconnect network, which electrically couples these device segments in parallel to two contact pads. The ESD protection device includes a trigger region designed to place the ESD protection device in a conduction mode by sensing the current between the p-type and n-type wells. Advantageously, the ESD protection device includes a secondary electrical interconnect network electrically coupling together each of the same doped wells from the row (i.e., each of the p-type wells or each of the n-type wells). This secondary electrical interconnect network forms separate nodes from the primary electrical interconnect network, which serve only to maintain potential balance between the connected wells. This synchronizes the device's triggering behavior by mitigating localized variations in the well potential that relate to a state where one or more fingers are triggered while one or more of the remaining fingers are not triggered.

[0017] refer to Figure 1The image depicts an ESD protection device 100 according to an embodiment. The ESD protection device 100 is formed in the upper surface 102 of a semiconductor body 104. The semiconductor body 104 may include semiconductor materials from group IV element semiconductors, group IV-IV compound semiconductor materials, group III-V compound semiconductor materials, or group II-VI compound semiconductor materials, or may be composed of semiconductor materials from group IV element semiconductors, group IV-IV compound semiconductor materials, group III-V compound semiconductor materials, or group II-VI compound semiconductor materials. Examples of semiconductor materials from group IV element semiconductors particularly include silicon (Si) and germanium (Ge). Examples of group IV-IV compound semiconductor materials particularly include silicon carbide (SiC) and silicon germanium (SiGe). Examples of group III-V compound semiconductor materials particularly include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). Examples of II-VI compound semiconductor materials include, in particular, cadmium telluride (CdTe), cadmium mercury telluride (CdHgTe), and magnesium cadmium telluride (CdMgTe). In addition to the ESD protection device 100, the semiconductor body 104 may include other active devices, such as transistors, particularly power switching devices (e.g., MOSFETs, IGBTs, HEMTs, etc.). Alternatively, the ESD protection device 100 may be implemented as a discrete device configured to protect external components via external connections (e.g., bonded lead connections, PCB connections, etc.).

[0018] ESD protection device 100 includes a plurality of p-type wells 106 and n-type wells 108 formed in the upper surface 102 of semiconductor body 104. The p-type wells 106 and n-type wells 108 are arranged in rows, alternating with each other. As shown, ESD protection device 100 includes: a first row 109 of p-type wells 106 and n-type wells 108 on the left side of the figure; and a second row 111 of p-type wells 106 and n-type wells 108 on the right side of the figure. In these rows, the p-type wells 106 and n-type wells 108 alternate with each other along a first direction D1. According to an embodiment, ESD protection device 100 is configured such that a unit cell (e.g., comprising, for example, one of the p-type wells 106 and half of both of the n-type wells 108 on either side of the p-type well 106 (or vice versa)) has a fixed width, thus allowing for a plurality of unit cells arranged adjacent to each other at regular spacing. For example, each of these unit cells can have a regular width between 1.0 μm and 15.0 μm.

[0019] ESD protection device 100 includes a first shallow-doped region 124 and a second shallow-doped region 126 disposed within each of n-type wells 108. The first shallow-doped region 124 and the second shallow-doped region 126 have opposite conductivity types. The first shallow-doped region 124 is a p-type region forming a pn junction with the underlying n-type well 108, and the second shallow-doped region 126 is an n-type region with a higher doping degree than the underlying n-type well 108. Correspondingly, ESD protection device 100 includes a third shallow-doped region 128 and a fourth shallow-doped region 130 disposed within each of p-type wells 106. The third shallow-doped region 128 and the fourth shallow-doped region 130 have opposite conductivity types. The third shallow-doped region 128 is a p-type region with a higher doping degree than the underlying p-type well 106. The fourth shallow-doped region 130 is an n-type region forming a pn junction with the underlying p-type well 106.

[0020] According to an embodiment, the semiconductor body 104 has a density of not more than 10 15 dopant atoms / cm 3 The background dopant concentration, and more typically at 10 12 dopant atoms / cm 3 Up to 10 14 dopant atoms / cm 3 Within the range. The background dopant concentration of the semiconductor body 104 can be a net p-type or net n-type concentration, and can be selected to be opposite to the conductivity type of the wells connected to the first contact pad 116 and the second contact pad 118. The p-type well 106 and the n-type well 108 have a higher net dopant concentration than the background dopant concentration of the semiconductor body 104. For example, the n-type well 108 can have a net dopant concentration of at least 10. 15 dopant atoms / cm 3 The net n-type dopant concentration, and more conventionally at 10 17 dopant atoms / cm 3 Within the range. Similarly, the p-type well 106 can have at least 10 15 dopant atoms / cm 3 The net p-type dopant concentration, and more typically at 10 17 dopant atoms / cm 3 Within the range. The first shallow doped region 124, the second shallow doped region 126, the third shallow doped region 128, and the fourth shallow doped region 130 have a net dopant concentration higher than the dopant concentration below the n-type well 108 or p-type well 106 formed therein. For example, the first shallow doped region 124 and the third shallow doped region 128 may have a net dopant concentration of at least 10. 19 dopant atoms / cm 3 The net p-type dopant concentration, and more typically at 10 19 dopant atoms / cm3 Up to 10 21 dopant atoms / cm 3 Within the range, and the second shallow doped region 126 and the fourth shallow doped region 130 can have at least 10 19 dopant atoms / cm 3 The net n-type dopant concentration, and more conventionally at 10 19 dopant atoms / cm 3 Up to 10 21 dopant atoms / cm 3 Within the range.

[0021] The doped regions of the ESD protection device 100 described above can be formed using mask implantation technology. According to an embodiment, a p-type well 106 is formed by implanting a p-type dopant into the semiconductor body 104 in a first implantation process, and an n-type well 108 is formed by implanting an n-type dopant into the semiconductor body 104 in a second implantation process. For example, when the semiconductor body 104 is formed of silicon, the first implantation process may include implanting one or more of the following into the semiconductor body 104: B, BF, BF2, Al, etc., and the second implantation process may include implanting one or more of the following into the semiconductor body 104: P, As, Bi, etc. In this document, the terms "first" implantation process and "second" implantation process do not indicate a specific order. The first shallow doped region 124, the second shallow doped region 126, the third shallow doped region 128, and the fourth shallow doped region 130 can be formed by other implantation processes performed before or after the first and second implantation processes described above. For example, the first shallow-doped region 124 and the third shallow-doped region 128 can be formed by a third implantation process of implanting p-type dopant into the semiconductor body 104, and the second shallow-doped region 126 and the fourth shallow-doped region 130 can be formed by a fourth implantation process of implanting n-type dopant into the semiconductor body 104. In this document, the terms "third" and "fourth" implantation processes do not indicate a specific order. The implanted dopant atoms can be activated by an annealing step, which can be performed after each individual implantation process or simultaneously after all implantation processes.

[0022] ESD protection device 100 includes a first contact pad 116, a second contact pad 118, and a central interconnect structure 120. The first contact pad 116 is electrically connected to an n-type well 108 in a first row 109. The second contact pad 118 is electrically connected to an n-type well 108 in a second row 111. The central interconnect structure 120 is electrically connected to a p-type well 106 in the first row 109 and a p-type well 106 in the second row 111. The first contact pad 116, the second contact pad 118, and the central interconnect structure 120 can each be formed of a conductive material (e.g., copper, aluminum, nickel, or their alloys). Conductive channels 122 and 123 can also be formed of a conductive material (e.g., copper, aluminum, nickel, or their alloys) or highly doped polysilicon.

[0023] The ESD protection device 100 operates as follows. The ESD protection device 100 is a lateral device, meaning it is configured to conduct or block current flowing parallel to the upper surface 102 of the semiconductor body 104. In the conduction mode of the ESD protection device 100, current flows between the first contact pad 116 and the second contact pad 118. The group of n-wells 108 in the first row 109, p-wells 106 in the first row 109, p-wells 106 in the second row 111, and n-wells 108 in the second row 111 together form a PNPN structure between the first contact pad 116 and the second contact pad 118. At one voltage polarity, one of the first row 109 and the second row 111 operates in SCR mode, while the other operates as a forward-biased pin diode. At the opposite voltage polarity, the first row 109 and the second row 111 switch between SCR mode and pin diode mode. Because it has two devices arranged in an anti-tandem configuration, the ESD protection device 100 is symmetrical and bidirectional between the first contact pad 116 and the second contact pad 118. In other words, the ESD protection device 100 is a bidirectional device with two identical devices of opposite orientation connected in series with each other.

[0024] In the described embodiment, the ESD protection device 100 includes a trigger region 132 between one of the p-type wells 106 and one of the n-type wells 108. These trigger regions 132 operate as avalanche diodes, becoming conductive when an avalanche breakdown condition is reached. Once the device is conductive, current flows between the n-type well 108 and the p-type well 106 within the semiconductor body 104. This concept can be used to form a low-ohmic current path that diverts, for example, a sudden large current from an ESD event from another device connected to the ESD protection device 100. In other embodiments, the triggering mechanism of the ESD protection device 100 differs from that shown. For example, the ESD protection device 100 may be configured to sense n-well / p-well breakdown defined by the distance between the n-type well 108 and the p-type well 106 and the corresponding doping conditions. In another embodiment, the ESD protection device 100 can be configured such that the breakdown voltage of the n-well / p-well between the trigger regions 132 is lower than the breakdown voltage between the n-well 108 and p-well 106 outside the trigger regions. In another embodiment, the ESD protection device 100 includes an external triggering device that conducts trigger current to the n-well or p-well, coupled to a first contact pad 116 and a second contact pad 118, and conducts the trigger current if the potential difference between the first contact pad 116 and the second contact pad 118 exceeds a certain threshold. The external triggering network can be connected to a secondary electrical interconnect network 140 (described below) or to another interconnect network connected to at least one of the n-well 108 and p-well 106.

[0025] Primary electrical interconnect network 138. The primary electrical interconnect network 138 of the ESD protection device 100 refers to the electrical conductors of the group of p-type wells 106 and n-type wells 108 electrically coupled between the first contact pad 116 and the second contact pad 118 as a segment of the ESD protection device. In the conduction mode of the ESD protection device 100, operating current flows through the primary electrical interconnect network 138 between the first contact pad 116 and the second contact pad 118. Figure 1 In the ESD protection device 100, the primary electrical interconnect network 138 consists of a first conductive channel 122 extending over each of the n-type wells 108 and forming a low-ohmic connection with each of the first shallow doped region 124 and the second shallow doped region 126, a second conductive channel 123 extending over each of the p-type wells 106 and forming a low-ohmic connection with each of the third shallow doped region 128 and the fourth shallow doped region 130, a central interconnect structure 120, and an interconnect bus connecting the group of conductive channels 122, 123 to the first contact pad 116 and the second contact pad 118 and the central interconnect structure 120.

[0026] ESD protection device 100 may optionally include electrically isolated regions formed within semiconductor body 104 surrounding n-type well 108 and p-type well 106. For simplicity, these electrically isolated regions have been... Figure 1 The details are omitted but shown in Figures 3 and 4, and will be described in further detail below. These electrically isolated regions can lead to improved device performance by reducing the total device capacitance. An example of an ESD protection device with electrically isolated regions is described in Tylaite's U.S. Patent 11,776,996, the entire contents of which are described herein by reference. In one embodiment, ESD protection device 100 includes an isolation region, and the electrically isolated region is configured such that the isolation area around the p-type well is equal to the isolation area around the n-type well. In another embodiment, ESD protection device 100 includes an isolation region, and the electrically isolated region is configured such that the isolation area around the p-type well is larger than the isolation area around the n-type well, for example, as described in the Tylaite references mentioned above.

[0027] Referring to Figure 2, from Figure 1 The ESD protection device 100 is shown in a cross-sectional perspective view. Figure 2A It shows along Figure 1 The ESD protection device 100 is indicated by cross section 151, which extends in the first direction D1 and is located between one of the trigger regions 132. Figure 2B It shows along Figure 1 The ESD protection device 100 with indicated cross-section 161 extends in the first direction D1 and intersects one of the trigger regions 132. For example... Figure 2B As shown, the trigger region 132 includes a lightly doped partition 134 of the semiconductor body 104 between one of the p-type wells 106 and one of the n-type wells 108. This triggers the breakdown voltage V of the conductive avalanche diode structure of the ESD protection device 100. BR The width of the low-doped region 134 of the semiconductor body 104 between the p-type well 106 and the n-type well 108 is determined. As shown, there is an extension region 136 merging with the p-type well 106 and the n-type well 108, extending toward the adjacent doped well, thereby locally reducing the effective distance between the p-type well 106 and the n-type well 108 to define the width of the low-doped region 134. In this way, avalanche breakdown occurs locally where these trigger regions 132 are formed. In another embodiment, the distance between the p-type well 106 and the n-type well 108 can be locally reduced without providing an extension region locally at the surface. Separately or in combination, the trigger region 132 may include a path of low-doped semiconductor material inserted between electrically isolating material regions, for example, as described below. Figure 3BAs shown. Typically, the semiconductor material in the low-doped region 134 can have any doping concentration lower than that of the p-type well 106 and the n-type well 108. As shown, the low-doped region 134 corresponds to the intrinsic (i.e., unintentionally doped) material region from the semiconductor body 104. Alternatively, the low-doped region 134 can be provided by a lightly intentionally doped region.

[0028] Multi-finger ESD protection devices such as the ESD protection device 100 described above may be susceptible to non-uniform triggering behavior. As is apparent from the figures above, the ESD protection device 100 includes trigger regions 132 associated with multiple pairs of p-type wells 106 and n-type wells 108 in each of the first row 109 and the second row 111. Non-uniform triggering behavior occurs when the various conductive fingers of the ESD protection device are not triggered synchronously. Because factors in the triggering dynamics (such as statistical variations) are associated with removing the triggering condition (i.e., avalanche breakdown in the trigger region) once at least one finger is on, some of the trigger regions 132 do not remain in the avalanche breakdown state long enough for some of the n-type well / p-type well pairs to fail to transition from the blocking state to the conducting state. This problem is particularly problematic with higher trigger voltages and / or stress pulses with longer initial pulse side rise times. This problem can be self-reinforcing, as a faster trigger finger can reduce the voltage across the remaining fingers, thus reducing the likelihood of eventual triggering.

[0029] refer to Figure 3A Figure 3 illustrates an ESD protection device 100 according to one embodiment. The ESD protection device 100 of FIG. 3 includes a secondary electrical interconnect network 140 for each of the first row 109 and the second row 111. The secondary electrical interconnect network 140 electrically connects each of the p-type wells 106 in the respective rows 109, 111 together. The secondary electrical interconnect network 140 includes a plurality of third conductive channels 125 extending in a second direction of the semiconductor body. Each of the third conductive channels 125 from the secondary electrical interconnect network 140 forms a low-ohmic connection with one of the p-type wells 106. The secondary electrical interconnect network 140 additionally includes an interconnect bus 142 connected to each of the third conductive channels 125 and positioned outside the doped well row associated with the conductive channel 122. The interconnect bus 142 may extend in a second direction perpendicular to the first direction of the semiconductor body and thus intersect each of the third conductive channels 125 at an orthogonal angle. The secondary electrical interconnect network 140 may be formed of a conductive material (e.g., layers of copper, aluminum, nickel, and alloys thereof) or highly doped polysilicon. The secondary electrical interconnect network 140 may additionally include highly doped semiconductor material regions within the semiconductor body 104, which may replace the upper-layer interconnects.

[0030] The secondary electrical interconnect network 140 forms nodes independent of the primary electrical interconnect network 138. That is, the secondary electrical interconnect network 140 is not part of the wiring structure that accommodates the operating current flowing between the first contact pad 116 and the second contact pad 118 when the ESD protection device segment is in conductive mode. Instead, the third conductive channel 125 and the interconnect bus 142 form conductive paths that are not directly physically connected to the electrical conductors of the primary electrical interconnect network 138. An indirect connection exists between the primary electrical interconnect network 138 and the secondary electrical network 140 because they each have an ohmic contact with the p-type well 106. However, in the context of this specification, this is not a direct physical connection. As described above, the primary electrical interconnect network 138 of the ESD protection device 100 refers to the electrical conductors electrically coupling the p-type well 106 and the n-type well 108 between the first contact pad 116 and the second contact pad 118. For ease of explanation, only the conductive channels 122 and 123 of the primary electrical interconnect network 138 of the ESD protection device 100 in FIG3 are shown.

[0031] The secondary electrical interconnect network 140 balances the local potential in each of the connected p-wells 106. Therefore, once one finger has been triggered, and the other fingers will not trigger due to the cessation of the triggering condition, the resulting state of the potential distribution in the conducting finger is transferred to the untriggered fingers. This applies the triggering condition to the other untriggered fingers and forces them to also enter the conducting state.

[0032] According to another embodiment, the ESD protection device 100 is configured such that a secondary electrical interconnect network 140 electrically connects each of the n-wells 108 in the corresponding row together. In this embodiment, the ESD protection device 100 is the same as the device in FIG3, except that the secondary electrical interconnect network 140 is arranged such that a third conductive channel 125 extends over each of the n-wells 108 and forms an ohmic connection with each of the n-wells 108. This achieves the same potential equalization effect as described above, and thus mitigates uneven triggering behavior, which in turn ensures that each finger of the ESD protection device becomes conductive and that all operating currents are distributed in parallel.

[0033] refer to Figure 3BAn enlarged view of the ESD protection device near the trigger region 132 is shown. As shown, a third conductive channel 125 from the secondary electrical interconnect network 140 is arranged between one of a first conductive channel 122 from the primary electrical interconnect network 138 extending over one of the primary electrical interconnect networks 138 in the n-type well 108 and a second conductive channel 123 from the primary electrical interconnect network 138 extending over one of the primary electrical interconnect networks 138 in the p-type well 106. As shown, the ESD protection device 100 includes an extension region 136 of the p-type well 106 extending toward the n-type well 108 and serving to form the trigger region 132. In one embodiment, these extension regions 136 of the p-type well 106 are additionally used as well taps to form a direct connection with the secondary electrical interconnect network 140. The conductive channels 125 from the secondary electrical interconnect network 140 extend across the device to overlap with the extension regions 136 and facilitate a low-ohmic connection thereto. In an alternative configuration where the secondary electrical interconnect network 140 electrically connects the n-type wells 108 together, a similar arrangement can be used, wherein conductive channels 125 from the secondary electrical interconnect network 140 extend across extension regions 136 of the n-type wells 108.

[0034] A multilayer interconnect structure can be used to accommodate both a secondary electrical interconnect network 140 and a primary electrical interconnect network 138. A multilayer interconnect structure refers to a lead structure comprising multiple metallizations and via structures extending between these metallizations. For example, in one embodiment, the secondary electrical interconnect network 140 is a continuous structure formed in the lower metallization of a semiconductor device, and the primary electrical interconnect network 138 is at least partially formed in the upper metallization of the semiconductor device, which is longitudinally separated from the lower metallization. In this embodiment, a first conductive channel 122 forming a low-ohmic connection with each of the first shallow doped region 124 and the second shallow doped region 126, and a second conductive channel 123 forming a low-ohmic connection with each of the third shallow doped region 128 and the fourth shallow doped region 130, can be contacted via structures connected to the traces of the upper metallization covering the secondary electrical interconnect network 140.

[0035] Referring to Figure 4, a cross-sectional view of the ESD protection device shown in Figure 3 is presented. (As...) Figure 4A As shown, the third conductive channel 125 from the secondary electrical interconnect network 140 does not form any connection with the semiconductor body where the extension region 136 does not exist. Figure 4B As shown, a third conductive channel 125 from the secondary electrical interconnect network 140 overlaps with an extension region 136 of the p-type well 106, and low-ohmic contacts to the p-type well 106 are formed at these locations. ESD protection devices may include a thin barrier layer on the upper surface 102 of the semiconductor body 104, which may be patterned to include openings for direct connection.

[0036] like Figure 4B As shown, the ESD protection device 100 includes a fifth shallow-doped region 144 placed within an extension region 136 of a p-type well 106. These fifth shallow-doped regions 144 are p-type regions with a higher dopant concentration than the lower part of the p-type well 106. The fifth shallow-doped regions 144 facilitate a low-ohmic connection from the secondary electrical interconnect network 140 to the third conductive channel 125. The fifth shallow-doped regions 144 can be formed using techniques similar to those used for the first shallow-doped regions 124 and the third shallow-doped regions 128 described above, and / or have a similar dopant concentration. In an alternative configuration where the secondary electrical interconnect network 140 electrically connects the n-type wells 108 together, a similar arrangement can be used, where the fifth shallow-doped regions 144 correspond to the n-type regions formed within the extension region 136 of the n-type well 108. In this case, the fifth shallow doped region 144 can be formed by a technique similar to that of the second shallow doped region 126 and the fourth shallow doped region 130 described above, and / or have a dopant concentration similar to that of the second shallow doped region 126 and the fourth shallow doped region 130 described above.

[0037] Referring to FIG5, an ESD protection device 100 is schematically depicted according to an embodiment. Each ESD protection device 100 includes a rectifier device comprising a plurality of thyristor rectifier devices 202 connected in parallel between an anode terminal 141 and a cathode terminal via a primary electrical interconnect network 138. The thyristor rectifier devices 202 correspond to a set of p-type wells 106 and n-type wells 108 and associated first shallow doped regions 124, second shallow doped regions 126, third shallow doped regions 128, and fourth shallow doped regions 130, which are connected between first contact pads 116 and second contact pads 118 via the primary electrical interconnect network 138. The ESD protection device 100 shown in FIG5 can be schematically represented for reference. Figure 1 -2 One of the two bidirectional devices of the ESD protection device 100 described herein, for example, wherein the central interconnection structure 120 corresponds to the anode terminal 141 or the cathode terminal 143.

[0038] exist Figure 5AIn this embodiment, the device does not have the secondary electrical interconnect network 140 as described above. Because the branches (finger) of the device are composed of separate n-doped wells and p-doped wells, this multi-finger device is susceptible to non-uniform triggering behavior. This allows for the establishment of a potential distribution in each of the n-doped wells corresponding to the conduction state, independent of the other n-doped wells in the multi-finger device, and allows for the establishment of a potential distribution in each of the p-doped wells corresponding to the conduction state, independent of the other p-doped wells in the multi-finger device. In other words, in this embodiment, the regions in the gate terminal or the n-doped well or p-doped well where the gate terminal for controlled conduction to establish the SCR can be placed float independently of each other.

[0039] exist Figure 5B In this embodiment, the device includes a secondary electrical interconnect network 140 as described above. The secondary electrical interconnect network 140 forms separate electrical connections between p-doped wells (i.e., p-type wells 106 forming portions of the anode region of each triggering device) that form the anode region. Accordingly, the device is less susceptible to non-uniform triggering behavior when the local potential in the p-doped well of a conducting finger is transferred to the corresponding location in the p-doped well of another finger in the device. In the absence of one or more fingers being triggered, the transfer of local potential in the triggered finger will impose a triggering condition on the untriggered finger. In other words, in this embodiment, all regions in the gate terminal or p-doped well where controlled conduction for establishing an SCR can be placed are electrically coupled to each other, such that the local potential in the gate region of one or more conducting partitions / fingers / branches is transferred to one or more non-conducting partitions / fingers / branches.

[0040] In another embodiment, the secondary electrical interconnect network 140 may form separate electrical connections between the doped wells (i.e., the n-type well 108 forming the portion of the avalanche diode) that form the cathode region of each triggering device. In this case, similar mitigation of non-uniform triggering behavior can be achieved.

[0041] refer to Figure 6 An alternative layout of the ESD protection device 100 according to an embodiment is shown. The connection between the secondary electrical interconnect network 140 and the p-type well 106 is modified compared to the embodiment of FIG3. In this case, the third conductive channel 123 is omitted from the secondary electrical interconnect network 140. Instead, the secondary electrical interconnect network 140 includes an interconnect bus 142, which is placed at the lateral center of one of the rows 109, 111 of the doped wells. This interconnect bus 142 extends directly above the extension region 136 and forms a direct connection to the p-type well 106.

[0042] Referring to Figure 7, an alternative layout of the ESD protection device 100 according to an embodiment is shown. Figure 7AIn one embodiment, the ESD protection device 100 includes dedicated well taps 157 outside the trigger region 132. These dedicated well taps 157 are in direct contact with the secondary electrical interconnect network 140. Figure 7B In one embodiment, the ESD protection device 100 includes bridge spans 159 extending between extension regions 136. These bridge spans 159 form separate locations for connecting a secondary electrical interconnect network 140. Figure 7C In one embodiment, the ESD protection device 100 includes a continuous shallowly doped region 163 that extends laterally across each of the trigger regions 132 and forms a low-ohmic contact with the p-type well 106. The continuous shallowly doped region 163 replaces the third conductive channel 123 in the preceding embodiments. A secondary electrical interconnect network 140 contacts the continuous shallowly doped region 163 at either end of the p-type well 106 via an interconnect bus 142. In each embodiment, the secondary electrical interconnect network 140 forms a direct connection with each of the p-type wells 106 to equalize the potential between the fingers. A similar concept can be used for connection with each n-type well 108.

[0043] Referring to FIG8, various embodiments of the ESD protection device 200 according to an example are shown. In each of these embodiments, the secondary electrical interconnect network 140 as described above can be used to equalize the potential of the doped wells and synchronize the triggering methods in the same manner as described above. To the extent consistent with various device concepts, any of the previously described layout configurations of the secondary electrical interconnect network 140 and the associated well design for connecting the secondary electrical interconnect network 140 to each of the doped wells can be used in conjunction with the embodiments shown in FIG8. Each of the embodiments in FIG8 is related to the reference Figure 1 The difference between the ESD protection devices 100 described in -2 is that these ESD protection devices 200 are not configured as bidirectional thyristor rectifier devices. Figure 8A A first example of an ESD protection device 200 is shown, configured as an NPN bipolar device with a short-circuited shallow n+-doped emitter and p+-doped base contact region. The figure also shows a schematic representation of the equivalent circuit diagram, including a distributed resistor inside the p-well base region and a diode representing avalanche breakdown between the n-doped collector and the p-doped base region. Figure 8B An alternative embodiment without an n-well in the collector region is illustrated. Figure 8C The illustration is similar to Figure 8A The device additionally includes a p+ base tap to sense a local potential drop and distribute the local potential of the conducting finger to the blocking finger via a secondary electrical interconnection network, which can be configured as the aforementioned secondary electrical interconnection network 140. Figure 8D , 8E And the 8F diagram Figure 8A , 8BThe PNP equivalent of 8C.

[0044] In addition to the ESD protection device 100 described above, the concepts described herein, particularly providing a secondary electrical network to mitigate uneven triggering, can be incorporated into a variety of different ESD protection devices. For example, these ESD protection devices 100 include unidirectional devices and pin diodes, as well as bipolar junction transistor devices and silicon controlled rectifier devices with a floating gate. In one particular example, the second shallow doped region 126 and the fourth shallow doped region 130 can be omitted from the device. In another particular example, the first shallow doped region 124 and / or the fourth shallow doped region 130 can be omitted from the device.

[0045] Although this disclosure is not limited thereto, the following numbered embodiments illustrate one or more aspects of this disclosure.

[0046] Example 1. A semiconductor device comprising: a first row of doped wells formed in an upper surface of a semiconductor body, the first row including first conductivity type wells arranged alternately with second conductivity type wells in a first direction of the semiconductor body; a first contact pad and a second contact pad disposed above the upper surface of the semiconductor body; a primary electrical interconnect network electrically coupling the first conductivity type wells and the second conductivity type wells of the first row between the first contact pads and the second contact pads; and a secondary electrical interconnect network forming nodes independent of the primary electrical interconnect network and electrically connecting each of the first conductivity type wells in the first row together.

[0047] Example 2. The semiconductor device of claim 1, wherein the secondary electrical interconnect network includes a plurality of conductive channels, wherein each of the first conductivity type wells forms a low-ohmic connection with one of the conductive channels.

[0048] Example 3. The semiconductor device according to Example 2, wherein the secondary electrical interconnect network further includes an interconnect bus connected to each of the conductive channels from the secondary electrical interconnect network.

[0049] Example 4. A semiconductor device according to Example 3, wherein an interconnect bus extends in a first direction of the semiconductor body.

[0050] Example 5. A semiconductor device according to Example 3, wherein the secondary electrical interconnect network is a continuous structure formed in the lower metallization of the semiconductor device, and wherein the primary electrical interconnect network is at least partially formed in the upper metallization of the semiconductor device, the upper metallization being longitudinally separated from the lower metallization.

[0051] Example 6. A semiconductor device according to Example 2, wherein a conductive channel from a secondary electrical interconnect network is arranged between a first conductive channel from a primary electrical interconnect network and a second conductive channel from a primary electrical interconnect network, wherein the first extends over and is electrically coupled to a first conductivity type well, and the second extends over and is electrically coupled to a second conductivity type well.

[0052] Example 7. A semiconductor device according to Example 2, wherein each of the first conductivity type wells in the first row includes a plurality of extension regions extending toward one of the second conductivity type wells in the first row, and wherein conductive channels extend across and overlap with the extension regions, and a plurality of low-ohm connections are formed via the extension regions.

[0053] Example 8. The semiconductor device according to Example 7, wherein each of the extended regions includes a first conductivity type shallowly doped region intersecting with one of the conductive channels, wherein the first conductivity type shallowly doped region is more doped than the lower portion of the first conductivity type well.

[0054] Example 9. A semiconductor device according to Example 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

[0055] Example 10. A semiconductor device according to Example 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

[0056] Example 11. The semiconductor device according to Example 1 further includes a first shallow-doped region and a second shallow-doped region disposed in each of the first conductivity type wells, and a third shallow-doped region and a fourth shallow-doped region disposed in each of the second conductivity type wells, wherein the first shallow-doped region and the third shallow-doped region are p-type regions, and wherein the second shallow-doped region and the fourth shallow-doped region are n-type regions.

[0057] Example 12. The semiconductor device according to Example 1 further includes: a second row of doped wells formed in the upper surface of the semiconductor body, the second row including first conductivity type wells arranged alternately with second conductivity type wells in a first direction of the semiconductor body; a trigger region configured to sense a current between one of the first conductivity type wells and one of the second conductivity type wells from the second row, wherein a primary electrical interconnect network electrically couples a rectifier device formed by a set of first conductivity type wells and second conductivity type wells from the second row between a first contact pad and a second contact pad, and wherein the semiconductor device further includes an additional secondary electrical interconnect network that forms separate nodes independent of the primary electrical interconnect network and electrically connects each of the first conductivity type wells in the second row together.

[0058] Example 13. The semiconductor device according to Example 1 further includes a trigger region configured to sense a current between one of the first conductivity type wells and one of the second conductivity type wells from the first row of doped wells.

[0059] Example 14. The semiconductor device according to Example 1 further includes: a second row of doped wells formed in the upper surface of the semiconductor body, the second row of doped wells including first conductivity type wells, the first conductivity type wells and second conductivity type wells being alternately arranged in a first direction of the semiconductor body; wherein a primary electrical interconnect network electrically couples a semiconductor device segment between a first contact pad and a second contact pad, the semiconductor device segment being formed by a group of first conductivity type wells and second conductivity type wells from the second doped wells, and wherein the semiconductor device further includes an additional secondary electrical interconnect network forming separate nodes independent of the primary electrical interconnect network and independent of the secondary electrical interconnect network of the first row of doped wells, and electrically connecting each of the first conductivity type wells in the second row of doped wells together.

[0060] Example 15. A semiconductor device comprising: a plurality of silicon controlled rectifier devices connected in parallel and electrically coupled to an anode terminal and a cathode terminal via a primary electrical interconnect network, each of the silicon controlled rectifier devices including a trigger device configured to create a trigger current that puts the device into a conduction mode; and a secondary electrical interconnect network forming nodes independent of the primary electrical interconnect network and electrically connecting doped regions together, the doped regions being part of or connected to the terminals of each of the trigger devices.

[0061] Example 16. A semiconductor device according to Example 15, wherein at least one triggering device is configured as an avalanche diode, and wherein a secondary electrical interconnect network electrically connects each of the anodes of the avalanche diode together.

[0062] Example 17. A semiconductor device according to Example 14, wherein at least one triggering device is configured as an avalanche diode, and wherein a secondary electrical interconnect network electrically connects each of the cathodes of the avalanche diode together.

[0063] For ease of description, spatial relative terms such as "under," "below," "lower," "over," and "upper" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device and different orientations than those depicted in the figures. Furthermore, terms such as "first" and "second" are also used to describe various elements, areas, sections, etc., and are not intended to be limiting. Similar terms refer to similar elements throughout the specification.

[0064] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms that indicate the presence of the stated element or feature, but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0065] In view of the above changes and scope of application, it should be understood that the present invention is not limited to the above description or the accompanying drawings.

Claims

1. A semiconductor device, comprising: The first row of doped wells is formed in the upper surface of the semiconductor body, and the first row of doped wells includes first conductivity type wells arranged alternately with second conductivity type wells in a first direction of the semiconductor body. First contact pad and second contact pad, the first contact pad and the second contact pad are placed above the upper surface of the semiconductor body; A primary electrical interconnect network electrically couples a first conductivity type well and a second conductivity type well from the first row doped wells between the first contact pad and the second contact pad. A secondary electrical interconnect network forms nodes independent of the primary electrical interconnect network and electrically connects each of the first conductivity type wells in the first row of doped wells together.

2. The semiconductor device of claim 1, wherein the secondary electrical interconnect network comprises a plurality of conductive channels, wherein each of the first conductivity type wells forms a low-ohmic connection with one of the conductive channels.

3. The semiconductor device of claim 2, wherein the secondary electrical interconnect network further comprises an interconnect bus connected to each of the conductive channels from the secondary electrical interconnect network.

4. The semiconductor device of claim 3, wherein the interconnect bus extends in the first direction of the semiconductor body.

5. The semiconductor device of claim 3, wherein the secondary electrical interconnect network is a continuous structure formed in the lower metallization of the semiconductor device, and wherein the primary electrical interconnect network is at least partially formed in the upper metallization of the semiconductor device, the upper metallization being longitudinally separated from the lower metallization.

6. The semiconductor device of claim 2, wherein the conductive channel from the secondary electrical interconnect network is arranged between a first conductive channel from the primary electrical interconnect network and a second conductive channel from the primary electrical interconnect network, the first extending over and electrically coupled to one of the first conductivity type wells, and the second extending over and electrically coupled to one of the second conductivity type wells.

7. The semiconductor device of claim 2, wherein each of the first conductivity type wells in the first row of doped wells includes a plurality of extension regions extending toward one of the second conductivity type wells in the first row of doped wells, and wherein the conductive channel extends across and overlaps with the extension regions, and forms the plurality of the low-ohm connections via the extension regions.

8. The semiconductor device of claim 7, wherein each of the extended regions includes a first conductivity type lightly doped region, the first conductivity type lightly doped region intersecting with one of the conductive channels, wherein the first conductivity type lightly doped region has a higher doping degree than the lower portion of the first conductivity type well.

9. The semiconductor device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

10. The semiconductor device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

11. The semiconductor device of claim 1, further comprising a first shallow-doped region and a second shallow-doped region disposed in each of the first conductivity type wells, and a third shallow-doped region and a fourth shallow-doped region disposed in each of the second conductivity type wells, wherein the first shallow-doped region and the third shallow-doped region are p-type regions, and wherein the second shallow-doped region and the fourth shallow-doped region are n-type regions.

12. The semiconductor device according to claim 1, further comprising: A trigger region configured to sense current between one of the first conductivity type wells and one of the second conductivity type wells in the first row of doped wells.

13. The semiconductor device according to claim 1, further comprising: A second row of doped wells is formed in the upper surface of the semiconductor body. The second row of doped wells includes wells of a first conductivity type, which are alternately arranged with the second conductivity type wells in the first direction of the semiconductor body. The primary electrical interconnect network electrically couples between the first contact pad and the second contact pad a semiconductor device segment formed by the group of first conductivity type wells and second conductivity type wells from the second row of doped wells, and The semiconductor device further includes an additional secondary electrical interconnect network that forms separate nodes independent of the primary electrical interconnect network and independent of the secondary electrical interconnect network of the first row of doped wells, and electrically connects each of the first conductivity type wells in the second row of doped wells together.

14. A semiconductor device, comprising: A plurality of silicon controlled rectifier devices are connected in parallel and electrically coupled to an anode terminal and a cathode terminal via a primary electrical interconnect network. Each of the silicon controlled rectifier devices includes at least one trigger device configured to create a trigger current that puts the device into a conduction mode. as well as A secondary electrical interconnect network forms nodes independent of the primary electrical interconnect network and electrically connects doped regions together, wherein the doped regions are part of or coupled to the terminals of each of the trigger devices.

15. The semiconductor device of claim 14, wherein the at least one triggering device is configured as an avalanche diode, and wherein the secondary electrical interconnect network electrically connects each of the anodes of the avalanche diode together.

16. The semiconductor device of claim 14, wherein the at least one triggering device is configured as an avalanche diode, and wherein the secondary electrical interconnect network electrically connects each of the cathodes of the avalanche diode together.

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