Image sensor and manufacturing method thereof

Abstract

The invention provides an image sensor and a manufacturing method thereof, and the method comprises the steps: providing a substrate which comprises a pixel region and a logic region, and forming a groove for accommodating a vertical transmission gate in the pixel region; and forming a first polycrystalline silicon layer covering the upper surface of the substrate and the side wall and the bottom surface of the groove. After a first polycrystalline silicon layer is formed, N-type ion doping is carried out on the first polycrystalline silicon layer located on the side wall and the bottom face of a groove, and doping pre-embedding is formed; and forming a second polycrystalline silicon layer, filling the groove with the second polycrystalline silicon layer, and forming a polycrystalline silicon layer by the first polycrystalline silicon layer and the second polycrystalline silicon layer. The polycrystalline silicon layers are formed twice, and since N-type ion doping is performed on the first polycrystalline silicon layer, doping pre-embedding is formed; therefore, good doping in the vertical transmission gate polycrystalline silicon layer can be realized without introducing an extra high-temperature diffusion process, so that the electrical efficiency of the vertical transmission gate is ensured; and meanwhile, the influence of a high-temperature process on a logic device outside a pixel region is avoided.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, specifically relating to an image sensor and its manufacturing method. Background Technology

[0002] With the development of image sensors, pixel size is becoming smaller and smaller while maintaining high full-well capacity. Traditional horizontal transmission gates are limited by size and cannot maintain high full-well capacity in small pixel designs. Vertical transmission gates, on the other hand, can achieve deeper charge storage in a smaller pixel space, thereby improving photoelectric conversion efficiency and signal transmission capability.

[0003] like Figure 1 As shown, in the previous process, polysilicon was filled into the trench of substrate 01 in one go to form the vertical transport gate 02; then, polysilicon ion doping was performed. Since the depth of the vertical transport gate 02 is several times the thickness of the polysilicon on the upper surface of substrate 01, and ion implantation is not allowed to penetrate the polysilicon on the upper surface outside the vertical transport gate 02, ion implantation alone cannot reach the bottom of the vertical transport gate 02. Therefore, it is necessary to increase high-temperature diffusion to diffuse impurities in the surface polysilicon to the bottom of the vertical transport gate 02. However, this method introduces an additional high-temperature process, which will seriously affect logic devices outside the pixel area, especially core devices. Furthermore, the concentration of diffused impurities gradually decreases with the depth of the vertical transport gate 02, resulting in poor concentration uniformity and a decrease in the electrical efficiency of the vertical transport gate 02. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating an image sensor, which involves forming a polysilicon layer in two stages. Since the first polysilicon layer has already been doped with N-type ions to form a doped pre-embedded layer, it is not necessary to introduce an additional high-temperature diffusion process to achieve good doping inside the polysilicon layer of the vertical transmission gate, thereby ensuring the electrical efficiency of the vertical transmission gate. At the same time, it avoids the impact of the high-temperature process on logic devices outside the pixel area.

[0005] This invention provides a method for manufacturing an image sensor, comprising: S1. A substrate is provided, the substrate including a pixel region and a logic region, and a trench for accommodating a vertical transmission gate is formed in the pixel region; S2. A gate oxide layer and a first polysilicon layer are sequentially formed to cover the upper surface of the substrate and the sidewalls and bottom surface of the trench; S3. The first polysilicon layer located on the sidewalls and bottom of the trench is doped with N-type ions to form a doped pre-embedded layer; S4. A second polysilicon layer is formed, which fills the trench and covers the upper surface of the substrate; the first polysilicon layer and the second polysilicon layer constitute a polysilicon layer. S5. Doping the polycrystalline silicon layer; S6. Etch the polysilicon layer, retaining the polysilicon layer in and above the trench to form the vertical transmission gate, and retaining a portion of the polysilicon layer above the logic region to form the transistor gate.

[0006] Furthermore, in step S1, a first deep well region containing a photodiode is formed in the pixel region, and a second well region is formed in the logic region. The first deep well region and the second well region are isolated by a shallow trench.

[0007] Furthermore, step S6 specifically includes: forming a photoresist layer on the substrate, wherein the photoresist layer only covers the portion of the polysilicon layer above the trench and the portion above the NMOS region of the logic region; Using the second photoresist layer as a mask, the polysilicon layer is etched, and the remaining polysilicon layer forms the vertical transmission gate and the transistor gate.

[0008] Furthermore, after step S6, the method further includes: step S7, forming a first sidewall located on both sides of the vertical transmission gate and a second sidewall located on both sides of the transistor gate.

[0009] Furthermore, after step S7, the method further includes: step S8, forming an N-type heavily doped region by performing N-type ion heavy doping on the floating diffusion region of the pixel region and the P-wells on both sides of the transistor gate of the logic region to form an N-type heavily doped region.

[0010] The present invention also provides an image sensor, comprising: A substrate, the substrate including a pixel region and a logic region, wherein a trench is formed in the pixel region; A polysilicon layer, a portion of which fills the trench and forms a vertical transmission gate of a predetermined thickness above the trench; another portion of the polysilicon layer is located above the logic region and forms a transistor gate; The polysilicon layer is composed of a first polysilicon layer and a second polysilicon layer stacked together; the first polysilicon layer covers the sidewalls, bottom surface, and logic region of the trench; the first polysilicon layer located on the sidewalls and bottom surface of the trench is doped with N-type ions to form a doped pre-embedded layer; The second polysilicon layer fills the trench and forms a predetermined thickness above the trench, and the second polysilicon layer also covers the first polysilicon layer located in the logic region; The polycrystalline silicon layer is doped with N-type ions.

[0011] Furthermore, gate oxide layers are formed between the vertical transmission gate and the trench, and between the transistor gate and the substrate.

[0012] Furthermore, a first sidewall is formed on both sides of the vertical transmission gate, and a second sidewall is formed on both sides of the transistor gate.

[0013] Furthermore, N-type heavily doped regions are formed in the floating diffusion portion of the pixel region and in the P-wells on both sides of the transistor gate of the logic region.

[0014] Furthermore, a photodiode is formed in the pixel region of the substrate, and a transmission transistor is disposed between the photodiode and the floating diffusion portion. The gate of the transmission transistor is the vertical transmission gate. The vertical transmission gate is T-shaped, with the vertical portion of the T-shape filling the trench and the horizontal portion of the T-shape parallel to the upper surface of the substrate.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a method for fabricating an image sensor, comprising: S1, providing a substrate, the substrate including a pixel region and a logic region, and forming a trench in the pixel region for accommodating a vertical transmission gate; S2, sequentially forming a gate oxide layer and a first polysilicon layer covering the upper surface of the substrate and the sidewalls and bottom surface of the trench; S3, performing N-type ion doping on the first polysilicon layer located on the sidewalls and bottom surface of the trench to form a doped pre-embedded layer; S4, forming a second polysilicon layer, the second polysilicon layer filling the trench and covering the upper surface of the substrate; the first polysilicon layer and the second polysilicon layer constitute a polysilicon layer; S5, doping the polysilicon layer; S6, etching the polysilicon layer to form a vertical transmission gate and a transistor gate.

[0016] In this invention, after forming the first polysilicon layer, N-type ion doping is performed on the sidewalls and bottom of the trench to form a doped pre-embedded layer. Then, a second polysilicon layer is formed, filling the trench. The first and second polysilicon layers constitute the polysilicon layer. By forming the polysilicon layer in two stages, and because the first polysilicon layer has already been N-type doped to form a doped pre-embedded layer, no additional high-temperature diffusion process is needed to achieve good doping within the vertical transmission gate polysilicon layer, thus ensuring the electrical efficiency of the vertical transmission gate. Simultaneously, the impact of high-temperature processes on logic devices outside the pixel area is avoided. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an image sensor.

[0018] Figure 2 This is a schematic diagram of a method for manufacturing an image sensor according to the present invention.

[0019] Figure 3 This is a schematic diagram showing the formation of grooves in the method for manufacturing the image sensor of the present invention.

[0020] Figure 4This is a schematic diagram of the image sensor fabrication method of the present invention after the gate oxide layer has been formed.

[0021] Figure 5 This is a schematic diagram showing the formation of the first polycrystalline silicon layer in the method for manufacturing the image sensor of the present invention.

[0022] Figure 6 This is a schematic diagram of the first polycrystalline silicon layer after doping and pre-embedding in the method for manufacturing the image sensor of the present invention.

[0023] Figure 7 This is a schematic diagram showing the polycrystalline silicon layer after it has been formed in the method for manufacturing the image sensor of the present invention.

[0024] Figure 8 This is a schematic diagram of the polycrystalline silicon layer after doping in the method for manufacturing the image sensor of the present invention.

[0025] Figure 9 This is a schematic diagram of the second photoresist formed in the method for manufacturing the image sensor of the present invention.

[0026] Figure 10 This is a schematic diagram showing the vertical transmission gate and transistor gate formed in the method for manufacturing the image sensor of the present invention.

[0027] Figure 11 This is a schematic diagram showing the formation of the first and second sidewalls in the method for manufacturing the image sensor of the present invention.

[0028] Figure 12 This is a schematic diagram of the N-type heavily doped region formed in the method for manufacturing the image sensor of the present invention.

[0029] Figure 13 This is a graph comparing the diffusion impurity concentration and depth of the vertical transmission gate in this invention and the previous version.

[0030] The accompanying figure is labeled as follows: 01-Substrate; 02-Vertical transport gate; 10-Substrate; 20-Trench; 30-Gate oxide layer; 40-First polysilicon layer; 50-First photoresist; 60-Polysilicon layer; 70-Second photoresist; 80-Vertical transmission gate; 81-First sidewall; 90-Transistor gate; 91-Second sidewall. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0032] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0033] This invention provides a method for manufacturing an image sensor, such as... Figure 2 As shown, it includes: S1. A substrate is provided, the substrate including a pixel region and a logic region, and a trench for accommodating a vertical transmission gate is formed in the pixel region. S2, A gate oxide layer and a first polysilicon layer are sequentially formed to cover the upper surface of the substrate and the sidewalls and bottom surface of the trench; S3. The first polysilicon layer located on the sidewalls and bottom of the trench is doped with N-type ions to form a doped pre-embedded layer; S4. A second polysilicon layer is formed, which fills the trench and covers the upper surface of the substrate; the first polysilicon layer and the second polysilicon layer constitute a polysilicon layer. S5. Doping the polycrystalline silicon layer; S6. Etch the polysilicon layer, retaining the polysilicon layer in and above the trench to form the vertical transmission gate, and retaining part of the polysilicon layer above the logic region to form the transistor gate.

[0034] The following describes in detail the steps of the method for manufacturing the image sensor according to an embodiment of the present invention, with reference to the accompanying drawings.

[0035] Step S1, as follows Figure 3 As shown, a substrate 10 is provided, which may be, for example, a P-type semiconductor substrate. The substrate 10 includes a pixel region P and a logic region L. A trench 20 for accommodating a vertical transmission gate is formed within the pixel region P. A first deep well region containing a photodiode PD is formed within the pixel region P, and a second well region PW is formed within the logic region L. The first deep well region and the second well region PW are separated by a shallow trench isolation (STI). Specifically, the trench 20 for accommodating the vertical transmission gate is etched within the first deep well region, and then the initially deposited oxide layer and hard mask layer on the surface of the substrate 20 are removed.

[0036] An image sensor is formed on a substrate 10, which can be any suitable substrate known in the art, such as at least one of the following materials: silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, indium arsenide, gallium arsenide, indium phosphide, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator, and germanium-on-insulator, or it can be a double-sided polished silicon wafer, or a ceramic substrate such as alumina, quartz, or glass substrate. In this embodiment, the substrate 10 is, for example, a silicon wafer. Depending on the distribution range within the surface of the substrate 10, the image sensor can include a pixel area and a peripheral circuit area, wherein the pixel area can include multiple pixels arranged in an array. The peripheral circuit area can specifically be divided into areas for horizontal driving circuits, vertical driving circuits, column signal processing circuits, and control circuits, etc.

[0037] Step S2, as follows Figure 4 and Figure 5 As shown, a gate oxide layer 30 and a first polysilicon layer 40 are sequentially formed covering the upper surface of the substrate 10 and the sidewalls and bottom surface of the trench.

[0038] Step S3, as follows Figure 6 As shown, a first photoresist layer 50 exposing the pixel region P is formed on the substrate 10. The first polysilicon layer 40 located in the pixel region is N-type ion doped to form a doped pre-embedded structure on the sidewalls and bottom surface of the trench; then the first photoresist layer 50 is removed.

[0039] Step S4, as follows Figure 7 As shown, a second polysilicon layer is formed, which fills the trench and covers the upper surface of the substrate; the first polysilicon layer 40 and the second polysilicon layer constitute polysilicon layer 60. The second polysilicon layer completes the total thickness required for forming the polysilicon layer 60 for the vertical transmission gate.

[0040] Step S5, as follows Figure 8 As shown, the polycrystalline silicon layer 60 is doped.

[0041] Step S6, as follows Figure 9 and Figure 10 As shown, the polysilicon layer is etched, retaining the polysilicon layer in and above the trench to form the vertical transmission gate 80, and retaining a portion of the polysilicon layer above the logic region to form the transistor gate 90. Specifically, a second photoresist layer 70 is formed on the substrate 10, the second photoresist layer 70 only covering the portion of the polysilicon layer above the trench and the portion above the NMOS region of the logic region; using the second photoresist layer as a mask, the polysilicon layer is etched, and the remaining polysilicon layer forms the vertical transmission gate 80 and the transistor gate 90.

[0042] Step S7, as follows Figure 11 As shown, a first sidewall 81 is formed on both sides of the vertical transmission gate 80 and a second sidewall 91 is formed on both sides of the transistor gate 90.

[0043] Step S8, as follows Figure 12 As shown, an N-type heavily doped region N+ is formed. N-type ions are heavily doped into the floating diffusion region FD of the pixel region P and the P-wells on both sides of the transistor gate 90 of the logic region L to form the N-type heavily doped region N+.

[0044] Figure 13 This is a graph comparing the diffusion impurity concentration and depth of the vertical transmission gate in this invention and the previous version. Figure 13 The horizontal axis represents the depth h of the vertical transmission gate, and the vertical axis represents the diffusion impurity concentration n of the vertical transmission gate. Figure 13 It can be seen that before the improvement, the diffusion impurity concentration n of the vertical transmission gate gradually decreased with the increase of the vertical transmission gate depth h, and the uniformity of the diffusion impurity concentration n was poor, resulting in a decrease in the electrical efficiency of the vertical transmission gate. After the improvement of the present invention, the uniformity of the diffusion impurity concentration n is good, and the diffusion impurity concentration n of the vertical transmission gate does not change with the vertical transmission gate depth h, maintaining a relatively stable horizontal line.

[0045] The present invention also provides an image sensor, such as Figure 12 As shown, it includes: Substrate 10, the substrate includes a pixel region P and a logic region L, and a trench is formed in the pixel region P; A polysilicon layer, a portion of which fills the trench and forms a predetermined thickness above the trench to form a vertical transmission gate 80; another portion of the polysilicon layer is located above the logic region to form a transistor gate 90. The polysilicon layer is composed of a first polysilicon layer and a second polysilicon layer stacked together; the first polysilicon layer covers the sidewalls, bottom surface, and logic region of the trench; the first polysilicon layer located on the sidewalls and bottom surface of the trench is doped with N-type ions to form a doped pre-embedded layer; The second polysilicon layer fills the trench and forms a predetermined thickness above the trench. The second polysilicon layer also covers the first polysilicon layer located in the logic region. The polycrystalline silicon layer is doped with N-type ions.

[0046] Specifically, gate oxide layers are formed between the vertical transmission gate 80 and the trench, and between the transistor gate 90 and the substrate 10. First sidewalls 81 are formed on both sides of the vertical transmission gate 80, and second sidewalls 91 are formed on both sides of the transistor gate 90. N-type heavily doped regions N+ are formed in the floating diffusion region FD of the pixel region P and the P-wells on both sides of the transistor gate 90 of the logic region L.

[0047] A photodiode PD is formed in the pixel region P of the substrate 10, and the photodiode has a carrier accumulation region. A floating diffuser FD is disposed in the substrate 10, extending upward to the upper surface of the substrate 10. A transfer transistor is disposed between the photodiode and the floating diffuser, and the transfer transistor is used to transfer carriers from the carrier accumulation region to the floating diffuser. The gate of the transfer transistor is the vertical transfer gate 80, which extends downward from the substrate 10 to the carrier accumulation region in the substrate 10. The vertical transfer gate 80 is T-shaped, with the vertical portion of the T-shape filling the trench and the horizontal portion of the T-shape parallel to the upper surface of the substrate 10.

[0048] In summary, the present invention provides a method for fabricating an image sensor, comprising: S1, providing a substrate, the substrate including a pixel region and a logic region, and forming a trench in the pixel region for accommodating a vertical transmission gate; S2, sequentially forming a gate oxide layer and a first polysilicon layer covering the upper surface of the substrate and the sidewalls and bottom surface of the trench; S3, performing N-type ion doping on the first polysilicon layer located on the sidewalls and bottom surface of the trench to form a doped pre-embedded layer; S4, forming a second polysilicon layer, the second polysilicon layer filling the trench and covering the upper surface of the substrate; the first polysilicon layer and the second polysilicon layer constitute a polysilicon layer; S5, doping the polysilicon layer; S6, etching the polysilicon layer to form a vertical transmission gate and a transistor gate.

[0049] In this invention, after forming the first polysilicon layer, N-type ion doping is performed on the sidewalls and bottom of the trench to form a doped pre-embedded layer. Then, a second polysilicon layer is formed, filling the trench. The first and second polysilicon layers constitute the polysilicon layer. By forming the polysilicon layer in two stages, and because the first polysilicon layer has already been N-type doped to form a doped pre-embedded layer, no additional high-temperature diffusion process is needed to achieve good doping within the vertical transmission gate polysilicon layer, thus ensuring the electrical efficiency of the vertical transmission gate. Simultaneously, the impact of high-temperature processes on logic devices outside the pixel area is avoided.

[0050] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0051] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing an image sensor, characterized in that, include: S1. A substrate is provided, the substrate including a pixel region and a logic region, and a trench for accommodating a vertical transmission gate is formed in the pixel region; S2. A gate oxide layer and a first polysilicon layer are sequentially formed to cover the upper surface of the substrate and the sidewalls and bottom surface of the trench; S3. The first polysilicon layer located on the sidewalls and bottom of the trench is doped with N-type ions to form a doped pre-embedded layer; S4. A second polysilicon layer is formed, which fills the trench and covers the upper surface of the substrate; the first polysilicon layer and the second polysilicon layer constitute a polysilicon layer. S5. Doping the polycrystalline silicon layer; S6. Etch the polysilicon layer, retaining the polysilicon layer in and above the trench to form the vertical transmission gate, and retaining a portion of the polysilicon layer above the logic region to form the transistor gate.

2. The method for manufacturing an image sensor as described in claim 1, characterized in that, In step S1, a first deep well region containing a photodiode is formed in the pixel region, and a second well region is formed in the logic region. The first deep well region and the second well region are isolated by a shallow trench.

3. The method for manufacturing an image sensor as described in claim 1, characterized in that, Step S6 specifically includes: forming a photoresist layer on the substrate, wherein the photoresist layer only covers the portion of the polysilicon layer above the trench and the portion above the NMOS region of the logic region; Using the second photoresist layer as a mask, the polysilicon layer is etched, and the remaining polysilicon layer forms the vertical transmission gate and the transistor gate.

4. The method for manufacturing an image sensor as described in claim 3, characterized in that, Step S6 is followed by step S7, which involves forming a first sidewall located on both sides of the vertical transmission gate and a second sidewall located on both sides of the transistor gate.

5. The method for manufacturing an image sensor as described in claim 4, characterized in that, Step S7 is followed by step S8, which involves forming an N-type heavily doped region by performing N-type ion heavy doping on the floating diffusion region of the pixel region and the P-wells on both sides of the transistor gate of the logic region to form an N-type heavily doped region.

6. An image sensor, characterized in that, include: A substrate, the substrate including a pixel region and a logic region, wherein a trench is formed in the pixel region; A polysilicon layer, a portion of which fills the trench and forms a vertical transmission gate of a predetermined thickness above the trench; another portion of the polysilicon layer is located above the logic region and forms a transistor gate; The polysilicon layer is composed of a first polysilicon layer and a second polysilicon layer stacked together; the first polysilicon layer covers the sidewalls, bottom surface, and logic region of the trench; the first polysilicon layer located on the sidewalls and bottom surface of the trench is doped with N-type ions to form a doped pre-embedded layer; The second polysilicon layer fills the trench and forms a predetermined thickness above the trench, and the second polysilicon layer also covers the first polysilicon layer located in the logic region; The polycrystalline silicon layer is doped with N-type ions.

7. The image sensor as described in claim 6, characterized in that, A gate oxide layer is formed between the vertical transmission gate and the trench, and between the transistor gate and the substrate.

8. The image sensor as described in claim 6, characterized in that, A first sidewall is formed on both sides of the vertical transmission gate, and a second sidewall is formed on both sides of the transistor gate.

9. The image sensor as claimed in claim 6, characterized in that, N-type heavily doped regions are formed in the floating diffusion portion of the pixel region and in the P-wells on both sides of the transistor gate of the logic region.

10. The image sensor as claimed in claim 9, characterized in that, A photodiode is formed in the pixel area of ​​the substrate, and a transmission transistor is disposed between the photodiode and the floating diffusion portion. The gate of the transmission transistor is the vertical transmission gate. The vertical transmission gate is T-shaped, with the vertical portion of the T-shape filling the trench and the horizontal portion of the T-shape parallel to the upper surface of the substrate.

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