Heat dissipation power generation integrated device structure, preparation method and chip structure

Abstract

This invention provides an integrated heat dissipation and power generation device structure, fabrication method, and chip structure. A bottom electrode, a thermoelectric layer, and a top electrode are sequentially formed on a flexible substrate. Two pre-reserved thermoelectric unit output terminals on the thermoelectric layer form a series circuit through the bottom and top electrodes, thus forming a flexible thin-film array thermoelectric structure. The fabrication method, employing a miniaturized unit design, effectively reduces volume waste. The use of a flexible substrate solves the problem of rigid electrodes easily breaking under bending and uneven thermal expansion, enhancing the device's durability and stability. The thermoelectric layer material of this integrated heat dissipation and power generation device structure can absorb and dissipate heat, and can reuse thermal energy to achieve thermoelectric power generation using the material's own thermoelectric properties. It achieves dual functions of thermal management and energy conversion using a single material, optimizing thermoelectric conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a heat dissipation and power generation integrated device structure, preparation method and chip structure. Background Technology

[0002] In recent years, with the development of integrated circuits and the continuous increase in computing density, a large amount of energy is dissipated as waste heat during operation. This waste heat not only leads to low energy utilization but also causes chip performance degradation and reliability risks due to excessively high local temperatures. Therefore, highly integrated technologies that combine waste heat recovery and active thermal management have a wide range of applications. By directly converting waste heat into electrical energy through thermoelectric conversion mechanisms, local energy supply can be provided for low-power on-chip units; at the same time, the electrical signals generated in this process can map the thermal distribution characteristics, providing a new dimension for system status monitoring. This integrated heat dissipation-power generation architecture has dual value in breaking through the energy consumption bottleneck of high-computing-power chips.

[0003] Current integrated circuit waste heat recovery technology faces multiple structural bottlenecks. At the thermodynamic level, the non-uniform distribution of high-density heat flux on the chip surface makes it difficult for traditional planar thermoelectric thin films to establish an effective longitudinal temperature difference, which greatly affects the conversion efficiency of thermoelectric conversion devices. In terms of physical structure, thermoelectric conversion structures use a large number of rigid metal electrodes, and the electrodes are relatively thin. When bending or uneven thermal expansion occurs, they are prone to breakage, which affects the reliability of thermoelectric conversion devices. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a heat dissipation and power generation integrated device structure, preparation method and chip structure, to solve the problems in the prior art where planar thermoelectric thin films are difficult to adapt to the non-uniform heat flow distribution on the chip surface, thus affecting the thermoelectric conversion efficiency, and rigid electrodes are prone to breakage when bent or thermally expanded, leading to the failure of thermoelectric conversion devices.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating an integrated heat dissipation and power generation device structure, the method comprising:

[0006] S1 provides a flexible substrate;

[0007] S2, forming a bottom electrode on the flexible substrate, the bottom electrode comprising a plurality of bottom electrode units arranged in an array;

[0008] S3, forming a thermoelectric unit pair on each of the bottom electrode units, the thermoelectric unit pair including P-type thermoelectric units and N-type thermoelectric units arranged at intervals, and all the thermoelectric unit pairs constitute a thermoelectric layer;

[0009] S4, forming a top-layer electrode on the structure in which the thermoelectric unit pairs are formed, the top-layer electrode comprising:

[0010] A plurality of first top-layer electrode units; arranged along the short side of the thermoelectric unit pair and disposed on both sides of the obtained structure, with adjacent P-type thermoelectric units located on both sides of the obtained structure connected in series or adjacent N-type thermoelectric units located on both sides of the obtained structure connected in series.

[0011] Several second top-layer electrode units; arranged along the long side of the thermoelectric unit pair, with adjacent P-type thermoelectric units and N-type thermoelectric units connected in series;

[0012] The first top electrode unit located on one side is not connected to the two P-type thermoelectric units or the two N-type thermoelectric units located at the end of that side, so that the two P-type thermoelectric units or the two N-type thermoelectric units form a series circuit through the bottom electrode and the top electrode.

[0013] Optionally, in step S3, the P-type thermoelectric unit is formed by magnetron sputtering, and the material of the P-type thermoelectric unit is WSe2; the N-type thermoelectric unit is formed by magnetron sputtering, and the material of the N-type thermoelectric unit is Bi2Te3.

[0014] Optionally, in step S2, the bottom electrode is formed using a magnetron sputtering process, and the material of the bottom electrode includes Pt; in step S4, the top electrode is formed using a magnetron sputtering process, and the material of the top electrode includes Pt.

[0015] Optionally, before step S2, the flexible substrate is further subjected to ultrasonic cleaning with acetone and ethanol in sequence, and then dried with high-purity nitrogen.

[0016] The present invention also provides a heat dissipation and power generation integrated device structure, which is prepared by the preparation method of the heat dissipation and power generation integrated device structure described in any one of the above claims, wherein the device structure includes:

[0017] Flexible substrate;

[0018] The bottom electrode located on the flexible substrate includes a plurality of bottom electrode units arranged in an array.

[0019] Thermoelectric layer; comprising thermoelectric unit pairs located on each of the bottom electrode units, the thermoelectric unit pairs comprising P-type thermoelectric units and N-type thermoelectric units spaced apart;

[0020] The top electrode comprises several first top electrode units and several second top electrode units. All first top electrode units are arranged along the short side of the thermoelectric unit pair and disposed on both sides of the structure, connected in series with adjacent P-type thermoelectric units located on the side of the structure or adjacent N-type thermoelectric units located on the side of the structure. The second top electrode units are arranged along the long side of the thermoelectric unit pair, connected in series with adjacent P-type and N-type thermoelectric units. The first top electrode units on one side of the structure are not connected to the two P-type or two N-type thermoelectric units located at that end, so that a series circuit is formed between the two P-type or two N-type thermoelectric units through the bottom electrode and the top electrode.

[0021] Optionally, the flexible substrate may be made of PDMS.

[0022] Optionally, the bottom electrode is made of Pt, and the top electrode is made of Pt.

[0023] Optionally, the material of the P-type thermoelectric unit is WSe2, and the material of the N-type thermoelectric unit is Bi2Te3.

[0024] Optionally, the vertical projection of the P-type thermoelectric unit, the N-type thermoelectric unit, and the interval between the P-type thermoelectric unit and the N-type thermoelectric unit coincides with the bottom electrode unit. The overall planar dimensions of the thermoelectric layer are the same as the overall planar dimensions of the bottom electrode. The planar dimensions of the first top electrode unit and the second top electrode unit are both the same as the planar dimensions of the bottom electrode unit. The spacing between the bottom electrode units, the spacing between the N-type thermoelectric units, the spacing between the P-type thermoelectric units, the spacing between the N-type thermoelectric units and the P-type thermoelectric units, the spacing between the first top electrode unit, the spacing between the second top electrode unit, and the spacing between the first top electrode unit and the second top electrode unit are all equal.

[0025] The present invention also provides a chip structure, the chip structure comprising:

[0026] Heat source area;

[0027] The heat dissipation and power generation integrated device structure as described above, located on the surface of the heat source region.

[0028] As described above, the integrated heat dissipation and power generation device structure, fabrication method, and chip structure of the present invention have the following beneficial effects: By sequentially forming a bottom electrode, a thermoelectric layer, and a top electrode on a flexible substrate, and connecting the two thermoelectric unit output terminals reserved on the thermoelectric layer through the bottom electrode and the top electrode to form a series circuit, a flexible thin-film array thermoelectric structure is formed. The fabrication method employs a flexible thin-film array structure with a miniaturized unit design, whose thickness and size can be precisely matched to semiconductor manufacturing processes, thereby producing a thermoelectric thin film of suitable size and effectively reducing volume waste. In addition, the use of a flexible substrate solves the problem of rigid electrodes easily breaking when bent or experiencing uneven thermal expansion in the prior art, thus avoiding the failure of the integrated heat dissipation and power generation device caused by this, enhancing the durability and stability of the device, and expanding its application range. Furthermore, the thermoelectric layer material of this integrated heat dissipation and power generation device structure can absorb and dissipate heat, and can utilize the thermoelectric properties of the material itself to reuse thermal energy based on the Seebeck effect to achieve thermoelectric power generation. Using a single material, it achieves the dual functions of thermal management and energy conversion, realizing the integration of heat dissipation and power generation functions, and optimizing thermoelectric conversion efficiency. Therefore, this device structure has the advantages of small size, easy integration, adaptability to non-uniform heat flow distribution on chip surface and high heat dissipation efficiency per unit volume, and has important application value and significance for chip heat dissipation and waste heat recovery.

[0029] The P-type thermoelectric unit can be made of WSe2, and the N-type thermoelectric unit can be made of Bi2Te3. The use of the topological insulator material Bi2Te3 not only improves heat dissipation efficiency but also achieves efficient thermoelectric power generation through the Seebeck effect. This is because the thermoelectric units formed on the bottom electrode unit are arranged in an array structure. When a temperature difference exists, holes in the P-type thermoelectric unit and electrons in the N-type thermoelectric unit migrate from the high-temperature end to the low-temperature end, generating electrical energy through a series circuit formed by the bottom and top electrodes. Furthermore, due to the topological insulator properties of Bi2Te3, its surface has conductive topologically protected states. When the chip heats up and radiates to a suitable infrared band, the topological band gap on the surface of the Bi2Te3 material layer of the N-type thermoelectric unit opens, allowing the absorbed heat to dissipate in the form of light or phonon vibrations, thus achieving efficient heat dissipation. The large band gap and high thermoelectric figure of merit (ZT value) of Bi2Te3 material give it excellent thermoelectric performance near room temperature, further enhancing the efficiency of thermoelectric power generation. Attached Figure Description

[0030] Figure 1 The diagram shows a process flow diagram of the fabrication method of the integrated heat dissipation and power generation device structure of the present invention.

[0031] Figure 2 The diagram shows a planar structure of the flexible substrate and the bottom electrode located on the flexible substrate according to the present invention.

[0032] Figure 3 The diagram shown is a planar structural schematic of the thermoelectric layer of the present invention.

[0033] Figure 4 The diagram shows a planar structure of the top electrode of the present invention.

[0034] Figure 5 The diagram shown is a planar structural schematic of the integrated heat dissipation and power generation device of the present invention.

[0035] Figure 6 The diagram shown is a schematic of the integrated heat dissipation and power generation device structure of the present invention.

[0036] Figure 7 The diagram shows the heat dissipation test results of the chip structure and the bare chip structure of this invention.

[0037] Figure 8 The figure shows the current-voltage characteristic curves of the integrated heat dissipation and power generation device structure under different temperature differences according to the present invention.

[0038] Figure 9 The graph shows the power-current characteristic curves of the integrated heat dissipation and power generation device structure under different temperature differences according to the present invention.

[0039] Component labeling explanation: 1 Integrated heat dissipation and power generation device structure, 11 Flexible substrate, 12 Bottom electrode, 121 Bottom electrode unit, 13 Thermoelectric layer, 131 Thermoelectric unit pair, 132 N-type thermoelectric unit, 133 P-type thermoelectric unit, 14 Top electrode, 141 First top electrode unit, 142 Second top electrode unit, 2 Chip structure, 3 Bare chip structure, Steps S1~S4. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] This embodiment provides a method for fabricating an integrated heat dissipation and power generation device structure, such as... Figure 1 As shown, the preparation method includes:

[0043] S1 provides a flexible substrate;

[0044] S2, forming a bottom electrode on the flexible substrate, the bottom electrode comprising a plurality of bottom electrode units arranged in an array;

[0045] S3, forming a thermoelectric unit pair on each of the bottom electrode units, the thermoelectric unit pair including P-type thermoelectric units and N-type thermoelectric units arranged at intervals, and all the thermoelectric unit pairs constitute a thermoelectric layer;

[0046] S4, forming a top-layer electrode on the structure in which the thermoelectric unit pairs are formed, the top-layer electrode comprising:

[0047] A plurality of first top-layer electrode units; arranged along the short side of the thermoelectric unit pair and disposed on both sides of the obtained structure, with adjacent P-type thermoelectric units located on both sides of the obtained structure connected in series or adjacent N-type thermoelectric units located on both sides of the obtained structure connected in series.

[0048] Several second top-layer electrode units; arranged along the long side of the thermoelectric unit pair, with adjacent P-type thermoelectric units and N-type thermoelectric units connected in series;

[0049] The first top electrode unit located on one side is not connected to the two P-type thermoelectric units or the two N-type thermoelectric units located at the end of that side, so that the two P-type thermoelectric units or the two N-type thermoelectric units form a series circuit through the bottom electrode and the top electrode.

[0050] The fabrication method of the integrated heat dissipation and power generation device structure in this embodiment involves sequentially forming a bottom electrode, a thermoelectric layer, and a top electrode on a flexible substrate. Two pre-reserved thermoelectric unit output terminals on the thermoelectric layer form a series circuit through the bottom and top electrodes, thereby forming a flexible thin-film array thermoelectric structure. This method employs a flexible thin-film array structure with a miniaturized unit design. Its thickness and size can precisely match semiconductor manufacturing processes, thus producing appropriately sized thermoelectric films and effectively reducing volume waste. Furthermore, the use of a flexible substrate solves the problem of rigid electrodes easily breaking under bending and uneven thermal expansion in existing technologies, thereby avoiding failure of the integrated heat dissipation and power generation device, enhancing the device's durability and stability, and expanding its application range. Moreover, the thermoelectric layer material of this integrated heat dissipation and power generation device structure can absorb and dissipate heat, and can utilize the material's own thermoelectric properties to reuse thermal energy based on the Seebeck effect to achieve thermoelectric power generation. Using a single material, it achieves dual functions of thermal management and energy conversion, realizing the integration of heat dissipation and power generation functions and optimizing thermoelectric conversion efficiency. Therefore, this device structure has the advantages of small size, easy integration, adaptability to non-uniform heat flow distribution on chip surface and high heat dissipation efficiency per unit volume, and has important application value and significance for chip heat dissipation and waste heat recovery.

[0051] The fabrication method of the integrated heat dissipation and power generation device structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0052] like Figure 2 As shown, step S1 is performed first, providing a flexible substrate 11.

[0053] As an example, the material of the flexible substrate 11 includes, but is not limited to, polydimethylsiloxane (PDMS).

[0054] like Figure 2 As shown, step S2 is then performed to form a bottom electrode 12 on the flexible substrate 11. The bottom electrode 12 includes a plurality of bottom electrode units 121 arranged in an array.

[0055] Specifically, the method for preparing the bottom electrode 12 and the material of the bottom electrode 12 can be selected according to the actual thermoelectric conversion capability requirements or process requirements. Preferably, in step S2 of this embodiment, the bottom electrode 12 is formed by magnetron sputtering to avoid the risk of thermal damage caused by high-temperature processes and to provide a waste heat recovery solution for high-density integrated circuits. The material of the bottom electrode 12 includes, but is not limited to, platinum (Pt).

[0056] like Figure 3As shown, step S3 is then performed, in which thermoelectric unit pairs 131 are formed on each of the bottom electrode units 121. Each thermoelectric unit pair 131 includes P-type thermoelectric units 133 and N-type thermoelectric units 132 arranged at intervals. All of the thermoelectric unit pairs 131 constitute a thermoelectric layer 13.

[0057] Specifically, the method for preparing the P-type thermoelectric unit 133, the method for preparing the N-type thermoelectric unit 132, the material of the N-type thermoelectric unit 132, and the material of the P-type thermoelectric unit 133 can be selected according to the actual thermoelectric conversion capability requirements or process requirements. Preferably, in step S3 of this embodiment, the P-type thermoelectric unit 133 is formed by magnetron sputtering, and the material of the P-type thermoelectric unit 133 is WSe2; the N-type thermoelectric unit 132 is formed by magnetron sputtering, and the material of the N-type thermoelectric unit 132 is bismuth telluride (Bi2Te3). Magnetron sputtering can avoid the risk of thermal damage caused by high-temperature processes and provide a waste heat recovery solution for high-density integrated circuits. The use of the topological insulator material Bi2Te3 not only improves heat dissipation efficiency but also achieves efficient thermoelectric power generation through the Seebeck effect. This is because the thermoelectric units 131 formed on the bottom electrode unit 121 are arranged in an array structure. When a temperature difference exists, the holes in the P-type thermoelectric units 133 and the electrons in the N-type thermoelectric units 132 migrate from the high-temperature end to the low-temperature end, generating electrical energy through the series circuit formed by the bottom electrode 12 and the subsequently formed top electrode 14. In addition, due to the topological insulator properties of Bi2Te3 material, its surface has conductive topological protection states. When the chip heats up and radiates to a suitable infrared band, the topological band gap on the surface of the Bi2Te3 material layer of the N-type thermoelectric unit 132 will open, allowing the absorbed heat to be dissipated in the form of light or phonon vibration, thereby achieving efficient heat dissipation. The large band gap and high thermoelectric figure of merit (ZT value) of Bi2Te3 material give it excellent thermoelectric performance near room temperature, further enhancing the efficiency of thermoelectric power generation.

[0058] like Figure 4 As shown, step S4 is then performed, in which a top electrode 14 is formed on the structure where the thermoelectric unit pair 131 is formed. The top electrode 14 includes:

[0059] A plurality of first top-layer electrode units 141 are arranged along the short side of the thermoelectric unit pair 131 and disposed on both sides of the obtained structure, and the adjacent P-type thermoelectric units 133 or the adjacent N-type thermoelectric units 132 located on both sides of the obtained structure are connected in series.

[0060] Several second top-layer electrode units 142 are arranged along the long side of the thermoelectric unit pair 131, and adjacent P-type thermoelectric units 133 and N-type thermoelectric units 132 are connected in series.

[0061] The first top electrode unit 141 located on one side is not connected to the two P-type thermoelectric units 133 or the two N-type thermoelectric units 132 located at the end of that side, so that the two P-type thermoelectric units 133 or the two N-type thermoelectric units 132 form a series circuit through the bottom electrode 12 and the top electrode 14.

[0062] Thus, as Figure 5 and Figure 6 As shown, the integrated heat dissipation and power generation device structure 1 was prepared.

[0063] Specifically, the method for preparing the top electrode 14 and the material of the top electrode 14 can be selected according to the actual thermoelectric conversion capacity requirements or process requirements. Preferably, in step S2 of this embodiment, the top electrode 14 is formed by magnetron sputtering to avoid the risk of thermal damage caused by high-temperature processes and to provide a waste heat recovery solution for high-density integrated circuits. The material of the top electrode 14 includes, but is not limited to, Pt.

[0064] The fabrication method of the integrated heat dissipation and power generation device structure in this embodiment mainly uses magnetron sputtering technology. Magnetron sputtering is a high-speed, low-temperature sputtering technology. In diode sputtering, a closed magnetic field parallel to the target surface is added. With the help of the orthogonal electromagnetic field formed on the target surface, secondary electrons are bound to a specific area on the target surface to enhance ionization efficiency, increase ion density and energy, thereby realizing a high-speed sputtering process. It has the advantages of simple equipment, easy control, large coating area and strong adhesion.

[0065] As a specific example, when forming the bottom electrode 12, the P-type thermoelectric unit 133, the N-type thermoelectric unit 132, and the top electrode 14 using magnetron sputtering, before step S2, the process includes sequentially ultrasonically cleaning the flexible substrate 11 with acetone and ethanol to remove organic contaminants, followed by drying with high-purity nitrogen. Before magnetron sputtering deposition, the magnetron sputtering process parameters need to be set. For example, the RF power supply is set to 40W, the temperature of the flexible substrate 11 is kept constant at 80°C, the deposition time is preset to 20 min, and a molecular pump is started to pump the magnetron sputtering chamber to 10°C. - 6 Torr-level ultra-high vacuum was then introduced, followed by the introduction of high-purity argon gas and the adjustment of the pressure to 0.5 Pa to 2 Pa, and then the corresponding film layers were deposited in sequence.

[0066] This embodiment also provides a heat dissipation and power generation integrated device structure 1, such as Figures 2 to 6 As shown, the device structure includes:

[0067] Flexible substrate 11;

[0068] The bottom electrode 12 located on the flexible substrate 11 includes a plurality of bottom electrode units 121 arranged in an array.

[0069] Thermoelectric layer 13 includes thermoelectric unit pairs 131 located on each of the bottom electrode units 121, the thermoelectric unit pairs 131 including P-type thermoelectric units 133 and N-type thermoelectric units 132 arranged at intervals;

[0070] The top electrode 14 includes a plurality of first top electrode units 141 and a plurality of second top electrode units 142. All first top electrode units 141 are arranged along the short side of the thermoelectric unit pair 131 and disposed on both sides of the structure, connected in series with adjacent P-type thermoelectric units 133 or adjacent N-type thermoelectric units 132 located on the side of the structure. The second top electrode units 142 are arranged along the long side of the thermoelectric unit pair 131, connected in series with adjacent P-type thermoelectric units 133 and N-type thermoelectric units 132. The first top electrode units 141 on one side of the structure are not connected to the two P-type thermoelectric units 133 or the two N-type thermoelectric units 132 located at that end, so that a series circuit is formed between the two P-type thermoelectric units 133 or between the two N-type thermoelectric units 132 through the bottom electrode 12 and the top electrode 14.

[0071] The integrated heat dissipation and power generation device structure 1 described above can be prepared using the preparation method of the integrated heat dissipation and power generation device structure described above, but it is not limited to this method. Other suitable preparation methods are also possible, and the beneficial effects they can achieve can be found in the specific description of the preparation method, which will not be repeated here.

[0072] As an example, the material of the flexible substrate 11 includes, but is not limited to, PDMS.

[0073] As an example, the material of the bottom electrode 12 includes, but is not limited to, Pt, and the material of the top electrode 14 includes, but is not limited to, Pt.

[0074] As a preferred example, the material of the P-type thermoelectric unit 133 is WSe2, and the material of the N-type thermoelectric unit 132 is Bi2Te3. The use of the topological insulator material Bi2Te3 not only improves heat dissipation efficiency but also achieves efficient thermoelectric power generation through the Seebeck effect. This is because the thermoelectric units 131 formed on the bottom electrode unit 121 are arrayed. When a temperature difference exists, holes in the P-type thermoelectric units 133 and electrons in the N-type thermoelectric units 132 migrate from the high-temperature end to the low-temperature end, generating electrical energy through the series circuit formed by the bottom electrode 12 and the top electrode 14. In addition, due to the topological insulator properties of Bi2Te3 material, its surface has conductive topological protection states. When the chip heats up and radiates to a suitable infrared band, the topological band gap on the surface of the Bi2Te3 material layer of the N-type thermoelectric unit 132 opens, allowing the absorbed heat to be dissipated in the form of light or phonon vibration, thereby achieving efficient heat dissipation. The large band gap and high thermoelectric figure of merit (ZT value) of Bi2Te3 material give it excellent thermoelectric performance near room temperature, further enhancing the efficiency of thermoelectric power generation.

[0075] As an example, the projection of the P-type thermoelectric unit 133, the N-type thermoelectric unit 132, and the interval between the P-type thermoelectric unit 133 and the N-type thermoelectric unit 132 in the vertical direction coincides with the bottom electrode unit 121. The overall planar dimensions of the thermoelectric layer 13 are the same as the overall planar dimensions of the bottom electrode 12. The planar dimensions of the first top electrode unit 141 and the second top electrode unit 142 are both the same as the planar dimensions of the bottom electrode unit 121. The spacing of the bottom electrode units 121, the spacing of the N-type thermoelectric units 132, the spacing of the P-type thermoelectric units 133, the spacing between the N-type thermoelectric units 132 and the P-type thermoelectric units 133, the spacing of the first top electrode unit 141, the spacing of the second top electrode unit 142, and the spacing between the first top electrode unit 141 and the second top electrode unit 142 are all equal.

[0076] As a further specific example, such as Figures 2 to 6 As shown, the flexible substrate 11 has dimensions of 30mm*20mm.

[0077] The bottom electrode unit 121 has a size of 4.3mm*1.9mm. The bottom electrode unit 121 is arranged in an array of 6 columns along the long side of the flexible substrate 11 and 8 rows along the short side of the flexible substrate 11, and the spacing between the bottom electrode units 121 is 0.5mm.

[0078] The planar dimensions of the P-type thermoelectric unit 133 are 1.9mm*1.9mm, and the planar dimensions of the N-type thermoelectric unit 132 are 1.9mm*1.9mm. The distance between the P-type thermoelectric unit 133 and the N-type thermoelectric unit 132 along the long side of the flexible substrate 11 is 0.5mm. The distance between the P-type thermoelectric unit 133 and the N-type thermoelectric unit 132 along the short side of the flexible substrate 11 is 0.5mm.

[0079] The first top electrode unit 141 has a planar dimension of 4.3mm*1.9mm, and the second top electrode unit 142 has a planar dimension of 4.3mm*1.9mm. The resulting structure has 3 and 4 first top electrode units 141 on each side of the short side, respectively. The spacing between the first top electrode units 141, the spacing between the second top electrode units 142, and the spacing between the first top electrode units 141 and the second top electrode units 142 are all 0.5mm. The first top electrode unit 141 on one side of the resulting structure is not connected to the two N-type thermoelectric units 132 located at the end of that side. The two N-type thermoelectric units 132 form a series circuit through the bottom electrode 12 and the top electrode 14.

[0080] This embodiment also provides a chip structure 2, which includes:

[0081] Heat source area;

[0082] The heat dissipation and power generation integrated device structure 1 described above is located on the surface of the heat source region.

[0083] like Figure 7 As shown, the surface temperature of the structure was read using a UNI-T UTi320E thermal imager. The left image shows the chip structure 2 with the integrated heat dissipation and power generation device structure 1, and the right image shows the bare chip structure 3 without the integrated heat dissipation and power generation device structure 1, which was fabricated using the same process. By placing the chip structure 2 and the bare chip structure 3 on a 50°C constant temperature heating stage and comparing the surface temperatures read using a UNI-T UTi320E thermal imager, the surface temperature of the chip structure 2 was 42.6°C (ambient temperature 37.6°C), and the surface temperature of the bare chip structure 3 was 47.7°C (ambient temperature 36.9°C). This demonstrates that the integrated heat dissipation and power generation device structure 1 provided in this embodiment has relatively good heat dissipation capabilities.

[0084] like Figure 8 and Figure 9As shown, the chip structure 2 was placed on a constant temperature heating platform at 50°C, 60°C, 70°C, and 80°C, and the surface temperature of the chip structure 2 was measured to be 43.5°C, 49°C, 56°C, and 62°C, respectively. Simultaneously, an ITECH IT2805 source meter was used to scan the current at the output terminals of the two N-type thermoelectric units 132 in the thermoelectric layer 13 that were not connected to the top electrode 14, and the power generation under different conditions was measured. Figure 8 The figure shows the volt-ampere characteristic curves of the integrated heat dissipation and power generation device structure 1 under different temperature differences (6.5°C, 11°C, 14°C, 18°C), as shown. Figure 9 The figure shows the power-current characteristic curves of the integrated heat dissipation and power generation device structure 1 under different temperature differences (6.5°C, 11°C, 14°C, 18°C). The experimental results of the two sets of experiments show that the integrated heat dissipation and power generation device structure 1 of this embodiment has good heat dissipation effect. Near the normal operating temperature of the chip structure 2, the integrated heat dissipation and power generation device structure 1 can achieve picowatt-level power generation. With appropriate amplification circuit, it can be used for some integrated micro sensors and has certain application prospects.

[0085] In summary, the integrated heat dissipation and power generation device structure, fabrication method, and chip structure of this invention form a flexible thin-film array thermoelectric structure by sequentially forming a bottom electrode, a thermoelectric layer, and a top electrode on a flexible substrate. A series circuit is formed between the two thermoelectric unit output terminals pre-reserved on the thermoelectric layer via the bottom and top electrodes. The fabrication method employs a flexible thin-film array structure with a miniaturized unit design. Its thickness and size can precisely match semiconductor manufacturing processes, thus producing a thermoelectric thin film of suitable size and effectively reducing volume waste. Furthermore, the use of a flexible substrate solves the problem of rigid electrodes easily breaking under bending and uneven thermal expansion in existing technologies, thereby avoiding failure of the integrated heat dissipation and power generation device, enhancing the device's durability and stability, and expanding its application range. Moreover, the thermoelectric layer material of this integrated heat dissipation and power generation device structure can absorb and dissipate heat, and can utilize the material's own thermoelectric properties to reuse thermal energy based on the Seebeck effect to achieve thermoelectric power generation. Using a single material, it achieves dual functions of thermal management and energy conversion, realizing the integration of heat dissipation and power generation functions and optimizing thermoelectric conversion efficiency. Therefore, this device structure has the advantages of small size, easy integration, adaptability to non-uniform heat flow distribution on the chip surface, and high heat dissipation efficiency per unit volume, which has important application value and significance for chip heat dissipation and waste heat recovery. Thus, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a heat dissipation and power generation integrated device structure, used for chip surface thermal management and waste heat recovery, characterized in that, The preparation method includes: S1 provides a flexible substrate; S2, A bottom electrode is formed on the flexible substrate using a magnetron sputtering process. The bottom electrode includes a plurality of bottom electrode units arranged in an array. S3, forming thermoelectric unit pairs on each of the bottom electrode units, the thermoelectric unit pairs including P-type thermoelectric units and N-type thermoelectric units spaced apart, all of the thermoelectric unit pairs constituting a thermoelectric layer; the P-type thermoelectric units are formed by magnetron sputtering, the material of the P-type thermoelectric units being WSe2; the N-type thermoelectric units are formed by magnetron sputtering, the material of the N-type thermoelectric units being Bi2Te3; wherein, the Bi2Te3 material of the N-type thermoelectric units has topological insulator properties, used to open the surface topological band gap to dissipate heat energy when absorbing heat, and at the same time generate electrical energy based on the Seebeck effect; S4, a top electrode is formed on the structure in which the thermoelectric unit pairs are formed using a magnetron sputtering process, the top electrode comprising: A plurality of first top-layer electrode units; arranged along the short side of the thermoelectric unit pair and disposed on both sides of the obtained structure, with adjacent P-type thermoelectric units located on both sides of the obtained structure connected in series or adjacent N-type thermoelectric units located on both sides of the obtained structure connected in series. Several second top-layer electrode units; arranged along the long side of the thermoelectric unit pair, with adjacent P-type thermoelectric units and N-type thermoelectric units connected in series; The first top electrode unit located on one side is not connected to the two P-type thermoelectric units or the two N-type thermoelectric units located at the end of that side, so that the two P-type thermoelectric units or the two N-type thermoelectric units form a series circuit through the bottom electrode and the top electrode, and the two P-type thermoelectric units or the two N-type thermoelectric units serve as the output terminal of the series circuit, and the output terminal is located at the same end of the structure.

2. The method for fabricating the integrated heat dissipation and power generation device structure according to claim 1, characterized in that: In step S2, the bottom electrode is formed using a magnetron sputtering process, and the material of the bottom electrode includes Pt; in step S4, the top electrode is formed using a magnetron sputtering process, and the material of the top electrode includes Pt.

3. The method for fabricating the integrated heat dissipation and power generation device structure according to claim 1, characterized in that: Before step S2, the process includes sequentially ultrasonically cleaning the flexible substrate with acetone and ethanol, and then drying it with high-purity nitrogen.

4. A heat dissipation and power generation integrated device structure for chip surface thermal management and waste heat recovery, characterized in that, The device structure is prepared by the method described in any one of claims 1 to 3, wherein the device structure comprises: Flexible substrate; The bottom electrode located on the flexible substrate includes a plurality of bottom electrode units arranged in an array. Thermoelectric layer; comprising thermoelectric unit pairs located on each of the bottom electrode units, the thermoelectric unit pairs comprising P-type thermoelectric units and N-type thermoelectric units spaced apart; the material of the P-type thermoelectric units is WSe2, and the material of the N-type thermoelectric units is Bi2Te3; wherein, the Bi2Te3 material of the N-type thermoelectric units has topological insulator properties, used to open the surface topological band gap to dissipate heat energy when absorbing heat, and at the same time generate electrical energy based on the Seebeck effect; The top electrode comprises several first top electrode units and several second top electrode units. All first top electrode units are arranged along the short side of the thermoelectric unit pair and disposed on both sides of the structure, connected in series with adjacent P-type thermoelectric units located on the side of the structure or adjacent N-type thermoelectric units located on the side of the structure. The second top electrode units are arranged along the long side of the thermoelectric unit pair, connected in series with adjacent P-type and N-type thermoelectric units. The first top electrode units on one side of the structure are not connected to the two P-type or two N-type thermoelectric units located at that end, so that a series circuit is formed between the two P-type or two N-type thermoelectric units through the bottom electrode and the top electrode. The two P-type or two N-type thermoelectric units serve as the output terminals of the series circuit, and the output terminals are located at the same end of the structure.

5. The integrated heat dissipation and power generation device structure according to claim 4, characterized in that: The flexible substrate is made of PDMS.

6. The integrated heat dissipation and power generation device structure according to claim 4, characterized in that: The bottom electrode is made of Pt, and the top electrode is made of Pt.

7. The integrated heat dissipation and power generation device structure according to claim 4, characterized in that: The vertical projection of the P-type thermoelectric unit, the N-type thermoelectric unit, and the interval between the P-type thermoelectric unit and the N-type thermoelectric unit coincides with the bottom electrode unit. The overall planar dimensions of the thermoelectric layer are the same as the overall planar dimensions of the bottom electrode. The planar dimensions of the first top electrode unit and the second top electrode unit are both the same as the planar dimensions of the bottom electrode unit. The spacing between the bottom electrode units, the spacing between the N-type thermoelectric units, the spacing between the P-type thermoelectric units, the spacing between the N-type thermoelectric units and the P-type thermoelectric units, the spacing between the first top electrode unit, the spacing between the second top electrode unit, and the spacing between the first top electrode unit and the second top electrode unit are all equal.

8. A chip structure, characterized in that, The chip structure includes: Heat source area; The integrated heat dissipation and power generation device structure as described in any one of claims 4 to 7 is located on the surface of the heat source region.

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