Chip and manufacturing method thereof, chip packaging structure and electronic equipment
By introducing a dielectric layer and a getter layer into the chip substrate structure, the problem of metal diffusion during through-silicon via interconnection is solved, thereby improving the stability of active devices.
Patent Information
- Application Number
- CN202410881783.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-02
- Publication Date
- 2026-01-13
AI Technical Summary
During the interconnection process between through-silicon vias (TSVs) and other substrates or chips, metal contamination introduced by back-side grinding of the silicon substrate can cause metal to diffuse into active devices, leading to electrical abnormalities or failures.
Introducing a dielectric layer and a getter layer into the substrate structure of the chip, the dielectric layer blocks metal diffusion, and the getter layer adsorbs and prevents metal from diffusing to the active device area. Through-silicon vias (TSVs) are fabricated using first-through-hole, middle-through-hole, or post-through-hole processes.
It effectively prevents metal from diffusing into active devices, reduces the probability of electrical abnormalities or failures, and improves product stability.
Smart Images
Figure CN121335524A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its manufacturing method, chip packaging structure, and electronic device. Background Technology
[0002] Through silicon via (TSV) is a vertical interconnect technology that penetrates through a wafer. In advanced packaging products, TSV is required to achieve 2.5D / 3D (dimensional) stacking of chips.
[0003] refer to Figure 1 As shown, in order to achieve interconnection between TSVs and other substrates or chips, the back side of the silicon (Si) substrate of the chip needs to be polished to expose the TSVs. However, during the polishing process of the back side of the Si substrate, metal contamination (such as copper, Cu) is introduced, and the introduced metal diffuses along the Si substrate to the active devices during subsequent thermal processes, causing electrical abnormalities or failures. Summary of the Invention
[0004] This application provides a chip and its manufacturing method, chip packaging structure, and electronic device that can block metal contamination introduced from the back side of a substrate (such as a Si substrate).
[0005] This application provides a chip including a substrate structure, active devices, and through-silicon vias (TSVs). The substrate structure includes a first substrate, a second substrate, and a dielectric layer. The dielectric layer is located between the first and second substrates and can block metal diffusion. The active devices are disposed on the side of the first substrate away from the dielectric layer, and the second substrate has a gettering layer on the side closest to the dielectric layer. The through-silicon vias (TSVs) penetrate the first substrate, the dielectric layer, the gettering layer, and extend into the second substrate.
[0006] When the chip provided in this application is packaged, even if metal contamination (such as Cu) is introduced on the back side of the second substrate during the grinding process, the dielectric layer and getter layer in the substrate structure can intercept the introduced metal and prevent the metal from diffusing to the area of the active device, thereby reducing the probability of electrical abnormalities or failures of the active device and improving the stability of the product.
[0007] In some possible implementations, the dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
[0008] In some possible implementations, the dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is closer to the first substrate than the second dielectric layer, and a bonding interface exists between the first and second dielectric layers. In this case, the dielectric layer is formed by bonding the first and second dielectric layers together.
[0009] In some possible implementations, the first dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
[0010] In some possible implementations, the second dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
[0011] In some possible implementations, the first dielectric layer and the second dielectric layer have the same material. For example, both the first dielectric layer and the second dielectric layer can be made of nitride-doped silicon carbide (NDC).
[0012] In some possible implementations, the second substrate is a silicon substrate, and the getter layer is a silicon damage layer on the surface of the silicon substrate. This silicon damage layer can be introduced by mechanically polishing the back side of the silicon substrate to introduce lattice damage, or by ion implantation into the back side of the silicon substrate to introduce lattice damage.
[0013] In some possible implementations, through-silicon vias (TSVs) can be fabricated using a vialast process, in which case the TSV penetrates through a second substrate.
[0014] In some possible implementations, through-silicon vias (TSVs) can be fabricated using via-first and via-middle processes, in which case the TSVs do not penetrate the back side of the second substrate.
[0015] In some possible implementations, the active device includes a field-effect transistor.
[0016] This application also provides a method for fabricating a chip, which may include: forming a first dielectric layer on the back side of a first substrate; forming a getter layer on the front side of a second substrate, and then forming a second dielectric layer on the getter layer; bonding the first substrate and the second substrate through the first dielectric layer and the second dielectric layer to form a substrate structure; fabricating an active device on the front side of the first substrate and fabricating through-silicon vias (TSVs); wherein the TSVs penetrate the first substrate, the first dielectric layer, the second dielectric layer, the getter layer, and extend into the second substrate.
[0017] Using this fabrication method, a first substrate and a second substrate are bonded together through a first dielectric layer and a second dielectric layer to form a substrate structure. This allows a dielectric layer to be formed between the first substrate and the second substrate. This dielectric layer can intercept introduced metal and prevent the metal from diffusing into the active device area. At the same time, the getter layer located on the surface of the second substrate can also intercept introduced metal and prevent the metal from diffusing into the active device area, thereby reducing the probability of electrical abnormalities or failures of the active device and improving the stability of the product.
[0018] In some possible implementations, the above-mentioned fabrication of through-silicon vias may include: using via-first and via-middle processes to fabricate through-silicon vias from the front side of the first substrate; wherein the through-silicon via penetrates the first substrate, the first dielectric layer, the second dielectric layer, the getter layer and extends into the second substrate, but does not penetrate the second substrate.
[0019] In some possible implementations, the above-described fabrication of through-silicon vias may include: using a via last process to fabricate the through-silicon via from the back side of the second substrate; wherein the through-silicon via penetrates the second substrate, the second dielectric layer, the getter layer, the first dielectric layer, and the first substrate.
[0020] This application also provides a chip packaging structure, which includes a chip, a substrate structure, active devices, and through-silicon vias (TSVs). The substrate structure includes a first substrate, a second substrate, and a dielectric layer. The dielectric layer is located between the first and second substrates and is capable of blocking metal. The active devices are disposed on the side of the first substrate away from the dielectric layer, and the second substrate has a getter layer on the side closer to the dielectric layer. The TSVs penetrate the substrate structure.
[0021] The chip used in this packaging structure has a dielectric layer and a getter layer in the substrate structure. The dielectric layer and getter layer can intercept introduced metal and prevent the metal from diffusing into the area of active devices, thereby reducing the probability of electrical abnormalities or failures of active devices and improving product stability.
[0022] In some possible implementations, the dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
[0023] In some possible implementations, the dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is closer to the first substrate than the second dielectric layer, and a bonding interface exists between the first and second dielectric layers. In this case, the dielectric layer is formed by bonding the first and second dielectric layers together.
[0024] In some possible implementations, the first dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
[0025] In some possible implementations, the second dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
[0026] In some possible implementations, the first dielectric layer and the second dielectric layer have the same material.
[0027] In some possible implementations, the second substrate is a silicon substrate, and the getter layer is a silicon damage layer on the surface of the silicon substrate. This silicon damage layer can be introduced by mechanically polishing the back side of the silicon substrate to introduce lattice damage, or by ion implantation into the back side of the silicon substrate to introduce lattice damage, which can adsorb and block the metal.
[0028] In some possible implementations, the aforementioned active device includes a field-effect transistor.
[0029] This application also provides an electronic device, which includes a circuit board and a chip package structure as provided in any of the aforementioned possible implementations, wherein the circuit board and the chip package structure are electrically connected. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the structure of a chip provided in the prior art;
[0031] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;
[0032] Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;
[0033] Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;
[0034] Figure 5 A flowchart illustrating a chip fabrication method provided in this application embodiment;
[0035] Figure 6 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0036] Figure 7 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0037] Figure 8 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0038] Figure 9A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0039] Figure 10 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0040] Figure 11 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0041] Figure 12 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0042] Figure 13 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;
[0043] Figure 14 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;
[0044] Figure 15 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application. Detailed Implementation
[0045] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0046] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can indicate three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, and "more" refers to two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium, or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, including a series of steps or units. Methods, systems, products, or equipment are not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or equipment. Terms such as “up,” “down,” “left,” and “right” are used only with respect to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.
[0047] This application provides an electronic device with a chip packaging structure. The chip packaging structure adopts a novel chip structure with TSV and active devices. The chip adds one or more dielectric layers (also known as diffusion barrier layers) in the substrate to block metal. Through the dielectric layer, metal contamination on the back of the substrate can be intercepted, preventing the metal on the back of the substrate from diffusing to the area of the active devices, thereby reducing the probability of electrical abnormalities or failures of the active devices and improving the stability of the product.
[0048] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product, such as consumer electronics, home electronics, vehicle electronics, financial terminal products, communication electronics, etc.
[0049] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, storage devices, radar, base stations, and other communication equipment.
[0050] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip packaging structure, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.
[0051] The novel chip provided in this application can be applied to any chip with TSV and active devices.
[0052] For example, in some possible implementations, the chip provided in the embodiments of this application may be a functional chip with TSV and active devices, such as a memory chip, a logic chip, a microprocessor, etc., and this application does not limit it.
[0053] For example, in some possible implementations, the chip provided in the embodiments of this application may be an active silicon interposer with TSV and active devices.
[0054] Furthermore, the novel chip provided in this application can be applied to advanced packaging structures such as 2.5D and 3D, and this application does not impose any restrictions on this.
[0055] The chip packaging structure provided in this application can be applied to fields such as artificial intelligence, networks and data centers, high-performance computing, and graphics processors, and this application does not limit it in this regard.
[0056] The following provides a detailed description of the novel chip and chip packaging structure provided in the embodiments of this application.
[0057] Figure 2This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of this application.
[0058] Indicative, such as Figure 2 , Figure 3 As shown, this application embodiment provides a chip D, which includes a substrate structure 1, an active device a, and a through-silicon via (TSV). The substrate structure 1 includes a first substrate 10, a second substrate 20, and a dielectric layer 11. The dielectric layer 11 is disposed between the first substrate 10 and the second substrate 20. This dielectric layer 11 can also be referred to as a diffusion barrier layer, which can intercept and block metal.
[0059] As illustrated, the dielectric layer 11 may include one or more materials such as nitride-doped silicon carbide (NDC) and silicon dioxide (SiO2), but is not limited to these.
[0060] The first substrate 10 and the second substrate 20 mentioned above can be silicon substrates, but are not limited to this. In the embodiments of this application, the example is that both the first substrate 10 and the second substrate 20 are silicon substrates.
[0061] Continue to refer to Figure 2 , Figure 3 The active device a is disposed on the front side of the first substrate 10 (i.e., the side away from the dielectric layer 11). Indicatively, the active device a may include a field-effect transistor, but is not limited to this. Of course, a metal trace layer is also disposed on the active device a, and metal connection pads may be fabricated on the surface of the metal trace layer to achieve connections with other devices.
[0062] As illustrated, an active device a is fabricated on the front side of the first substrate 10 using a front end of line (FEOL) process, and then a metal trace layer is fabricated using a back end of line (BEOL) process.
[0063] Continue to refer to Figure 2 , Figure 3 A gettering layer 21 is provided on the front side of the second substrate 20 (the side closest to the dielectric layer 11). The gettering layer 21 can adsorb and block metal, thereby intercepting metal contamination on the back side of the second substrate 20 and preventing the metal on the back side of the second substrate 20 from diffusing.
[0064] This application does not impose any restrictions on the configuration of the getter layer 21.
[0065] Indicatively, in some possible implementations, the getter layer 21 may be a silicon damage layer formed on the front side of the second substrate 20 (i.e., the surface near the first substrate 10), that is, introducing lattice defects into the silicon substrate (20), which can prevent metal diffusion through lattice damage.
[0066] This application does not limit the fabrication method of the aforementioned silicon damage layer; in practice, it can be fabricated as needed.
[0067] For example, in some possible implementations, the aforementioned silicon damage layer (21) may be a lattice damage (or defect) introduced by mechanical polishing on the surface of the silicon substrate (20), which can adsorb and block metals.
[0068] For example, in some possible implementations, the aforementioned silicon damage layer (21) can be a lattice defect introduced by ion implantation on the surface of the silicon substrate (20). The dopant ions can be one or more of phosphorus P+, arsenic As+, argon Ar+, helium He+, etc., but are not limited to these. In this case, lattice damage introduced by ion implantation can block metal diffusion, thereby achieving the effect of capturing metal contamination.
[0069] The aforementioned through-silicon vias (TSVs) can be fabricated using via-first, via-middle, or via-last processes. This application does not impose any restrictions on these processes, and they can be configured as needed in practice.
[0070] For example, refer to Figure 2 As shown, in the viafirst and viamiddle processes, a through-silicon via (TSV) is fabricated from the front side of the first substrate 10 (i.e., the side away from the dielectric layer 11). In this case, the TSV penetrates the first substrate 10, the dielectric layer 11, the getter layer 21 and extends downward into the second substrate 20, but does not penetrate the second substrate 20.
[0071] For example, refer to Figure 3 As shown, in the via last, a through silicon via (TSV) is fabricated from the back side of the second substrate 20 (i.e., the side away from the dielectric layer 11). In this case, the TSV penetrates the entire substrate structure 1, that is, the TSV penetrates the first substrate 10, the dielectric layer 11, the getter layer 21, and the second substrate 20.
[0072] refer to Figure 4As shown, during the packaging of the chip, the back side of the second substrate 20 needs to be polished to expose the through-silicon vias (TSVs), thereby ensuring electrical connection between the TSVs and other devices (such as chips or substrates). After the polishing process, the dielectric layer 11 and the getter layer 21 remain in the substrate structure 1. In this way, even if the polishing process introduces metal contamination (such as Cu) onto the back side of the second substrate 20, the dielectric layer 11 and the getter layer 21 can intercept the introduced metal (such as Cu) and prevent it from diffusing to the region of the active device a, thereby reducing the probability of electrical abnormalities or failures in the active device and improving product stability.
[0073] This application does not impose any restrictions on the arrangement of the dielectric layer 11 in the substrate structure 1; in practice, it can be fabricated as needed.
[0074] As shown in the illustration, among some possible implementation methods, see reference. Figure 4 As shown, the dielectric layer 11 may include a first dielectric layer b1 and a second dielectric layer b2, and has a bonding interface M between the first dielectric layer b1 and the second dielectric layer b2; that is, the dielectric layer 11 may be formed by bonding the first dielectric layer b1 and the second dielectric layer b2, and the specific details can be found in the subsequent fabrication method section.
[0075] The first dielectric layer b1 and the second dielectric layer b2 mentioned above can be made of insulating dielectric materials with high bonding strength and diffusion blocking properties. In practice, they can be set as needed, and this application does not impose any restrictions on them.
[0076] As illustrated, the first dielectric layer b1 may be one or more of materials such as nitride-doped silicon carbide (NDC) and silicon dioxide (SiO2), but is not limited to these.
[0077] As illustrated, the second dielectric layer b2 can be one or more of materials such as nitride-doped silicon carbide (NDC) and silicon dioxide (SiO2), but is not limited to these.
[0078] It should be understood that the first dielectric layer b1 and the second dielectric layer b2 can be made of the same material or different materials, as long as the actual requirements can be met.
[0079] As illustrated, in some possible implementations, both the first dielectric layer b1 and the second dielectric layer b2 can be nitride-doped silicon carbide (NDC). The chip structure provided in the embodiments of this application will be further described below in conjunction with the fabrication method.
[0080] As illustrated, this application embodiment provides a method for manufacturing a chip, such as... Figure 5 As shown, the method for manufacturing chip D may include:
[0081] Step 01, Reference Figure 6 As shown, a first dielectric layer b1 is formed on the back side of the first substrate 10.
[0082] As shown in the illustration, among some possible implementation methods, see reference. Figure 6 As shown, a silicon substrate (10) is provided, and a first dielectric layer b1 is formed on the back side of the silicon substrate (10) using nitride-doped silicon carbide (NDC).
[0083] Step 02, Reference Figure 7 As shown, a getter layer 21 is first formed on the front side of the second substrate 20, and then a second dielectric layer b2 is formed on the getter layer 21.
[0084] As shown in the illustration, among some possible implementation methods, see reference. Figure 7 As shown, a silicon substrate (20) is provided, and the surface of the silicon substrate (20) is mechanically polished, ion implanted, etc. to form a getter layer 21 (i.e., a silicon damage layer); then a second dielectric layer b2 is formed on the getter layer 21 using nitride-doped silicon carbide (NDC).
[0085] Step 03, Reference Figure 8 As shown, the first substrate 10 and the second substrate 20 are bonded together through the first dielectric layer b1 and the second dielectric layer b2 to form the substrate structure 1.
[0086] For illustrative purposes only, please refer to the following: Figure 8 As shown, in some possible implementations, a first dielectric layer b1 on the back side of the first substrate 10 is bonded to a second dielectric layer b2 on the front side of the second substrate 20 to form a substrate structure 1. In this case, the first dielectric layer b1 and the second dielectric layer b2 are bonded to form a dielectric layer 11, and a bonding interface exists between the first dielectric layer b1 and the second dielectric layer b2.
[0087] Step 04, Reference Figure 9 , Figure 10 or Figure 11 As shown, an active device is fabricated on the front side of the first substrate 10, and a through silicon via (TSV) is fabricated therein; wherein the TSV penetrates the first substrate 10, the first dielectric layer b1, the second dielectric layer b2, the getter layer 21 and extends into the second substrate 20.
[0088] The aforementioned through-silicon vias (TSVs) can be fabricated using a via-first process, a via-middle process, or a via-last process.
[0089] This illustration shows the case where a via-first process is used for through-silicon vias (TSVs).
[0090] Step 04 above may include: reference Figure 9As shown in (a), a via-first process is used to fabricate a through-silicon via (TSV) from the front side of the first substrate 10. This TSV penetrates the first substrate 10, the first dielectric layer b1, the second dielectric layer b2, the getter layer 21, and extends into the second substrate 20, but may not penetrate the second substrate 20. Then, refer to... Figure 9 As shown in (b), an active device a, which may include a field-effect transistor, can be fabricated on the front side of the first substrate 10 using a front-end process (FEOL). Then, referring to... Figure 9 As shown in (b), the metal trace layer can be fabricated using a back-end process (BEOL).
[0091] This illustration shows the case where a through-silicon via (TSV) is constructed using a via-middle process:
[0092] Step 04 above may include: reference Figure 10 As shown in (a), an active device a, which may include a field-effect transistor, can be fabricated on the front side of the first substrate 10 using a front-end process (FEOL). Then, a through-silicon via (TSV) is fabricated from the front side of the first substrate 10 using a via-middle process. The TSV penetrates the first substrate 10, the first dielectric layer b1, the second dielectric layer b2, the getter layer 21, and extends into the second substrate 20, but may not penetrate the second substrate 20. Finally, a metal trace layer can be fabricated on the front side of the first substrate 10 using a back-end process (BEOL).
[0093] This illustration shows the case where a via (trace last) process is used for through-silicon vias (TSVs):
[0094] Step 04 above may include: reference Figure 11 As shown in (a), an active device a, which may include a field-effect transistor, can be fabricated on the front side of the first substrate 10 using a front-end process (FEOL); then one or more metal wiring layers are fabricated using a back-end process (BEOL). Afterwards, refer to... Figure 11 As shown in (b), a grinding process, such as chemical mechanical polishing (CMP), can be used to grind the back side of the second substrate 20 to thin it. Then, refer to... Figure 11 As shown in (c), a via-silicon via (TSV) is fabricated from the back side of the second substrate 20 using a via last process. The TSV passes through the second substrate 20, the getter layer 21, the second dielectric layer b2, the first dielectric layer b1, and the first substrate 10.
[0095] It should be understood that the sequence number of each of the above-mentioned production processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0096] For example, regarding steps 01 and 02: in some possible implementations, the first dielectric layer b1 can be formed first through step 01, and then the second dielectric layer b2 can be formed through step 02. In other possible implementations, the second dielectric layer b2 can be formed first through step 02, and then the first dielectric layer b1 can be formed through step 01.
[0097] For example, regarding steps 03 and 04:
[0098] In some possible implementations, after forming the substrate structure 1 in step 03, the active device a and the through-silicon via (TSV) can be fabricated in step 04. For details, please refer to [reference needed]. Figure 9 , Figure 10 , Figure 11 And the corresponding explanation.
[0099] In some other possible implementations, the active device a can be fabricated first in step 04, then the substrate structure 1 can be fabricated in steps 01, 02 and 03, and then a through-silicon via (TSV) can be fabricated in step 04 using a via-middle process or a via-last process.
[0100] This illustration uses a viamiddle process as an example. (Reference) Figure 12 As shown in (a), the active device a can be fabricated on the front side of the first substrate 10 using a front-end process (FEOL) in step 04. Then, referring to... Figure 12 As shown in (b), a carrier plate C1 can be attached to the side of the active device a, and the back side of the first substrate 10 can be thinned. Then, refer to... Figure 12 As shown in (c), a first dielectric layer b1 can be formed on the back side of the first substrate 10 in step 01, a getter layer 21 and a second dielectric layer b2 can be formed on the front side of the second substrate 20 in step 02, and the first substrate 10 and the second substrate 20 can be bonded together through the first dielectric layer b1 and the second dielectric layer b2 in step 03 to form substrate structure 1. Then, refer to... Figure 12 As shown in (d), a through-silicon via (TSV) is fabricated from the front side of the first substrate 10 using a via-middle process in step 04. Then, refer to... Figure 12 As shown in (e), one or more metal trace layers can be fabricated using a post-processing (BEOL) step. Specific details for each step can be found in the preceding related content.
[0101] As an illustration, let's take the vialast process as an example. Figure 13 As shown in (a), the active device a can be fabricated on the front side of the first substrate 10 using a front-end process (FEOL) in step 04; then, one or more metal wiring layers can be fabricated using a back-end process (BEOL). Afterwards, refer to... Figure 13 As shown in (b), a carrier plate C1 can be attached to one side of the metal trace layer, and the back side of the first substrate 10 can be thinned. Then, refer to... Figure 13 As shown in (c), a first dielectric layer b1 can be formed on the back side of the first substrate 10 in step 01, a getter layer 21 and a second dielectric layer b2 can be formed on the front side of the second substrate 20 in step 02, and the first substrate 10 and the second substrate 20 can be bonded together through the first dielectric layer b1 and the second dielectric layer b2 in step 03 to form substrate structure 1. Then, refer to... Figure 13 As shown in (d), a via-silicon via (TSV) is fabricated from the back side of the second substrate 20 using a via last process. Specific details of each step can be found in the aforementioned related content.
[0102] For other related content in the above manufacturing method, please refer to the corresponding parts in the aforementioned structural embodiments, which will not be repeated here; for other settings in the aforementioned structural embodiments, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.
[0103] When packaging chip D after its fabrication is complete, refer to... Figure 4 As shown, during the packaging process, the back side of chip D needs to be ground to expose the through-silicon via (TSV) to facilitate electrical connections between chip D and other devices, such as chips or substrates.
[0104] The chip provided in this application embodiment can be applied to any packaging structure, and this application does not impose any restrictions on it.
[0105] For illustrative purposes only, please refer to the following: Figure 14 As shown, some chip packaging structures may include a first chip D1 and a second chip D2 disposed on a substrate. The second chip D2 is stacked on the first chip D1. The first chip D1 has a through-silicon via (TSV). The second chip D2 is connected to the substrate through the first chip D1 and the TSV. Both the first chip D1 and the second chip D2 can be functional chips. For example, the first chip D1 can be a memory chip, and the second chip D2 can be a logic chip, but this is not a limitation. In this case, the novel chip provided in this application embodiment can be applied to the first chip D1.
[0106] For illustrative purposes only, please refer to the following: Figure 15As shown, in some chip packaging structures, multiple chips (D1, D2, D3, D4, D5) are stacked and mounted on a substrate. Each of the stacked chips (D1, D2, D3, D4, D5) may contain a Transmission Screen (TSV), and the chips can be interconnected via TSVs. All chips (D1, D2, D3, D4, D5) can be functional chips. For example, the first chip D1 can be a logic chip, and the second chip D2, third chip D3, fourth chip D4, and fifth chip D5 can be memory chips, but this is not a limitation. In this case, the novel chip provided in this application embodiment can be applied to one or more of the first chip D1, second chip D2, third chip D3, fourth chip D4, and fifth chip D5; in practice, the configuration can be adjusted as needed.
[0107] The above embodiments are all illustrated with the example of a substrate structure 1 having a dielectric layer 11. However, this application is not limited to this. Depending on the actual needs, the substrate structure 1 may have two or more dielectric layers 11. For example, the substrate structure 1 may be formed by bonding three or more substrates, with a dielectric layer 11 between two adjacent substrates.
[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A chip, characterized in that, Including substrate structure, active devices, and through-silicon vias: The substrate structure includes: a first substrate, a second substrate, and a dielectric layer; The dielectric layer is located between the first substrate and the second substrate, and the dielectric layer can block metal diffusion; The active device is disposed on the side of the first substrate away from the dielectric layer, and the second substrate has a getter layer on the side close to the dielectric layer; the through-silicon via penetrates the first substrate, the dielectric layer, the getter layer and extends into the second substrate.
2. The chip according to claim 1, characterized in that, The dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
3. The chip according to claim 1 or 2, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer; The first dielectric layer is closer to the first substrate than the second dielectric layer, and there is a bonding interface between the first dielectric layer and the second dielectric layer.
4. The chip according to claim 3, characterized in that, The first dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2); The second dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
5. The chip according to claim 3 or 4, characterized in that, The first dielectric layer and the second dielectric layer have the same material.
6. The chip according to any one of claims 1-5, characterized in that, The second substrate is a silicon substrate, and the getter layer is a silicon damage layer on the surface of the silicon substrate.
7. The chip according to any one of claims 1-6, characterized in that, The through-silicon via penetrates the second substrate; Alternatively, the through-silicon via does not penetrate the second substrate.
8. The chip according to any one of claims 1-7, characterized in that, The active device includes a field-effect transistor.
9. A method for manufacturing a chip, characterized in that, include: A first dielectric layer is formed on the back side of the first substrate; A getter layer is first formed on the front side of the second substrate, and then a second dielectric layer is formed on the getter layer; The first substrate and the second substrate are bonded together through the first dielectric layer and the second dielectric layer to form a substrate structure; An active device is fabricated on the front side of the first substrate, and a through-silicon via (TSV) is fabricated therein; wherein the TSV penetrates the first substrate, the first dielectric layer, the second dielectric layer, the getter layer, and extends into the second substrate.
10. The method for manufacturing a chip according to claim 9, characterized in that, The fabrication of through-silicon vias includes: A through-silicon via (TSV) is formed from the front side of the first substrate; wherein the TSV penetrates the first substrate, the first dielectric layer, the second dielectric layer, the getter layer, and extends into the second substrate; Alternatively, a through-silicon via (TSV) can be formed from the back side of the second substrate; wherein the TSV penetrates the second substrate, the second dielectric layer, the getter layer, the first dielectric layer, and the first substrate.
11. A chip packaging structure, characterized in that, Includes a chip; wherein the chip includes a substrate structure, active devices, and through-silicon vias: The substrate structure includes: a first substrate, a second substrate, and a dielectric layer; The dielectric layer is located between the first substrate and the second substrate, and the dielectric layer can block metal diffusion; The active device is disposed on the side of the first substrate away from the dielectric layer, and the second substrate has a getter layer on the side close to the dielectric layer; the through-silicon via penetrates the substrate structure.
12. The chip packaging structure according to claim 11, characterized in that, The dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
13. The chip packaging structure according to claim 11 or 12, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer; The first dielectric layer is closer to the first substrate than the second dielectric layer, and there is a bonding interface between the first dielectric layer and the second dielectric layer.
14. The chip packaging structure according to claim 12 or 13, characterized in that, The first dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2); The second dielectric layer includes at least one of nitride-doped silicon carbide (NDC) or silicon dioxide (SiO2).
15. The chip packaging structure according to claim 13 or 14, characterized in that, The first dielectric layer and the second dielectric layer have the same material.
16. The chip packaging structure according to any one of claims 11-15, characterized in that, The second substrate is a silicon substrate, and the getter layer is a silicon damage layer on the surface of the silicon substrate.
17. The chip packaging structure according to any one of claims 11-16, characterized in that, The active device includes a field-effect transistor.
18. An electronic device, characterized in that, It includes a circuit board and a chip package structure as described in any one of claims 11-17, wherein the circuit board is electrically connected to the chip package structure.