Integrated inductor including magnetic layer

Abstract

An inductive device includes a first set of conductive lines, a second set of conductive lines, and a conductive pillar connecting the first set of conductive lines to the second set of conductive lines to form an integrated inductor. The inductive device also includes one or more magnetic layers extending along the length of the integrated inductor and within the aperture of the integrated inductor.

Description

Cross-references to related applications

[0001] This application claims the benefit of priority to jointly owned U.S. nonprovisional patent application No. 18 / 343,595, filed June 28, 2023, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] Various characteristics are involved in inductive devices. Background Technology

[0003] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of active components. Passive integrated components have also been miniaturized, and the trend towards further miniaturization of such components continues. Passive inductors are often among the larger components in circuits, partly because the characteristic electrical properties of an inductor are related to its physical dimensions. For example, the inductance of an inductor is related to the orifice of its coil, and the current-carrying capacity is related to the size of the conductive elements in the coil. Due to these and other factors, there is a need for inductors with high current and high inductance, characterized by small form factors. Summary of the Invention

[0004] Various features are involved in integrated circuit devices.

[0005] One example provides an inductor device including a first set of conductive lines and a second set of conductive lines. The inductor device includes conductive posts that connect the first set of conductive lines to the second set of conductive lines to form an integrated inductor. The inductor device also includes one or more magnetic layers extending along the length of the integrated inductor and within an aperture of the integrated inductor.

[0006] Another example provides a device including an integrated device. The integrated device includes a first set of conductive lines and a second set of conductive lines. The integrated device includes conductive posts that connect the first set of conductive lines to the second set of conductive lines to form an integrated inductor. The integrated device also includes one or more magnetic layers that extend along the length of the integrated inductor and within the orifices of the integrated inductor.

[0007] Another example provides a method for manufacturing an inductor. The method includes forming a first set of conductive lines. The method includes forming one or more magnetic layers above the first set of conductive lines. The method includes forming conductive pillars connected to the first set of conductive lines. The method includes forming a second set of conductive lines connected to the conductive pillars above the one or more magnetic layers to form an integrated inductor. The one or more magnetic layers extend along the length of the integrated inductor and within the apertures of the integrated inductor. Attached Figure Description

[0008] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0009] FIG. 1 A schematic cross-sectional profile of a device including an exemplary integrated inductor is shown, the exemplary integrated inductor including multiple magnetic layers.

[0010] FIG. 2 A schematic cross-sectional profile of a device including an exemplary integrated inductor, which includes a magnetic layer, is illustrated.

[0011] FIG. 3 A schematic cross-sectional profile of a device including an exemplary integrated inductor, which includes a magnetic layer, is illustrated.

[0012] FIG. 4 A schematic cross-sectional profile of a device including an exemplary integrated inductor is shown, the exemplary integrated inductor including multiple magnetic layers.

[0013] FIG. 5 A schematic cross-sectional profile of a device including an exemplary integrated inductor is shown, the exemplary integrated inductor including multiple magnetic layers.

[0014] FIG. 6A A schematic top view of a device including an exemplary integrated inductor is shown, the exemplary integrated inductor including multiple magnetic layers.

[0015] FIG. 6B Examples FIG. 6A A schematic perspective view of the equipment.

[0016] FIG. 6C Examples FIG. 6A A schematic cross-sectional profile of a portion of the equipment.

[0017] FIG. 7A , FIG. 7B and FIG. 7C An exemplary process for manufacturing an exemplary integrated inductor comprising multiple magnetic layers is illustrated.

[0018] FIG. 8 An exemplary flowchart illustrating a method for manufacturing an exemplary integrated inductor including a magnetic layer is shown.

[0019] FIG. 9 Examples are shown of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0020] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0021] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For ease of reference herein, such features are generally introduced as “one or more” features and subsequently referred to in the singular or optional plural form (as indicated by “(multiple)”), unless the aspect relating to multiples of features is being described.

[0022] As used herein, the term "comprise" may be used interchangeably with "include". As used herein, "exemplary" indicates an example, specific implementation, and / or aspect, and should not be construed as restrictive or indicating a preference or preferred implementation. As used herein, ordinal terms used to modify elements (such as structures, components, operations, etc.) (e.g., "first", "second", "third", etc.) do not themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using ordinal terms). As used herein, the term "set" refers to one or more specific elements among specific elements, while the term "multiple" refers to multiple (e.g., two or more) specific elements.

[0023] In some figures, multiple instances of a particular type of feature are used. Although these features are physically and / or logically different, the same reference numerals are used for each feature, and these different instances are distinguished by adding letters to the reference numerals. Reference numerals are used without distinguishing letters when a feature is referenced herein as a group or a type of feature (e.g., when a specific feature among these features is not referenced). However, reference numerals are used with distinguishing letters when a specific feature among multiple features of the same type is mentioned herein. For example, see reference... FIG. 1The figure illustrates multiple magnetic layers 130, and these multiple magnetic layers are associated with reference numerals 130A and 130B. When referring to a specific layer among these magnetic layers (such as magnetic layer 130A), the distinguishing letter "A" is used. However, when referring to any one of these magnetic layers or referring to these magnetic layers as a group, the reference numeral 130 without a distinguishing letter is used.

[0024] Improvements in manufacturing technology and the demand for lower-cost, more powerful electronic devices have led to increasing complexity in ICs. More complex ICs typically have more complex interconnect schemes to enable interactions between IC devices. Due to the large number of interconnected devices in today's state-of-the-art mobile applications, the number of interconnect stages used in circuits has increased significantly.

[0025] Such interconnects include back-end process (BEOL) interconnect layers, which can refer to conductive interconnect layers used for electrical coupling to front-end process (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, where lower BEOL interconnect levels typically use thinner metal layers compared to higher BEOL interconnect levels. BEOL interconnect layers can be electrically coupled to intermediate process (MOL) interconnect layers, which interconnect to the IC's FEOL active devices.

[0026] As used herein, the term “layer” includes films and, unless otherwise stated, is not construed as indicating vertical or horizontal thickness. As used herein, the term “chiplet” can refer to an integrated circuit block, a functional circuit block, or other similar circuit blocks specifically designed to operate with one or more other chiplets to form a larger, more complex chiplet architecture.

[0027] Various aspects of this disclosure relate to integrated inductor devices that can be formed on a wafer surface using wafer-level processing. In some aspects, the integrated inductor device has a three-dimensional (3D) solenoid inductor design and includes one or more planar magnetic layers. The one or more magnetic layers are within the apertures of the inductor and extend along the length of the inductor.

[0028] Exemplary devices including integrated inductors including magnetic layers FIG. 1 A schematic cross-sectional profile view of a device 100 including an exemplary integrated inductor 102 on a substrate 110 is illustrated. The integrated inductor 102 is configured as a solenoid having a coil formed by a first set of conductive lines 116, a second set of conductive lines 126, and conductive posts 120 connecting the first set of conductive lines 116 to the second set of conductive lines 126. The integrated inductor 102 also includes one or more magnetic layers 130 within an aperture 160 of the integrated inductor 102.

[0029] Substrate 110 (e.g., wafer, die, chip, etc.) includes integrated active circuitry 144, such as multiple transistors and / or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. Integrated active circuitry 144 may be coupled to one or more electrical contacts at substrate surface 142 to achieve electrical communication with one or more components outside substrate 110. In a particular example, integrated active circuitry 144 corresponds to a power management integrated circuit (PMIC) and substrate 110 corresponds to a PMIC die or chip. Components of integrated active circuitry 144 may be formed in and / or on a semiconductor substrate. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finFETs, gate-all-around FETs, or mixtures of transistor types. In some implementations, front-end process (FEOL) technology may be used to fabricate integrated active circuitry 144 in and / or on a semiconductor substrate.

[0030] A first set of conductive lines 116 is located above surface 142 and includes a representative conductive line 116A, which is electrically connected to one or more conductive posts in the conductive posts 120 according to a solenoid winding configuration, such as a reference. FIG. 6A and FIG. 6B Further described. One or more of the first set of conductive lines 116 are coupled to one or more vias, such as vias 114A and 114B, which extend through the insulating layer 112 to the substrate 110. For example, via 114A can electrically connect conductive line 116A to active circuitry 144 and can serve as an input to integrated inductor 102. According to one aspect, via 114 is located in a first via layer (“V0”), and the first set of conductive lines 116 is located in a first redistribution layer (“RDL-1”).

[0031] The conductive pillar 120 includes conductive pillar 120A and conductive pillar 120B. In some embodiments, the conductive pillar 120 is formed of electroplated copper defined by photoresist and has a relatively large height and diameter (e.g., a “giant pillar”). In a particular example, each of the conductive pillars 120 has a height in the range of 75 micrometers to 110 micrometers and a diameter in the range of 75 to 110 micrometers, but in other examples, the conductive pillar 120 may have a larger or smaller height and / or a larger or smaller diameter. According to one aspect, the conductive pillar 120 is located in a third via layer (“V2”) and electrically connected to vias in a second via layer (“V1”), these vias extending through insulating layer 118 to conductive line 116.

[0032] The molding compound 122 at least partially encapsulates the conductive post 120 between the first set of conductive wires 116 and the second set of conductive wires 126. According to some aspects, the molding compound 122 comprises an epoxy resin material.

[0033] The second set of conductive lines 126 includes a representative conductive line 126A, which electrically connects conductive post 120A to conductive post 120B or another conductive post 120 (not shown), depending on the solenoid winding configuration, such as reference. FIG. 6A and FIG. 6B Further described. According to one aspect, conductive lines 126 are located in the second redistribution layer (“RDL-2”) and electrically connected to vias in the fourth via layer (“V3”), which extend through the insulating layer 124 to the conductive posts 120. According to one aspect, one or more conductive lines in conductive lines 126 are further coupled to one or more solder balls 140 (e.g., solder balls 140A and / or solder balls 140B) or other electrical contacts extending through the upper insulating layer 128.

[0034] In certain specific implementations, insulating layers 112, 118, 124, and 128 each comprise a polyimide material or other polymeric material. Although described as “insulating” layers, it should be understood that layers 112, 118, 124, and 128 can provide various functions; for example, layers 112, 118, 124, and 128 can serve as electrical isolation layers, passivation layers, or protective layers during sputtering or other manufacturing processes.

[0035] The aperture 160 is bounded by conductive pillars 120A, 120B, conductive lines 116A and 126A, and indicates the cross-sectional area of ​​the integrated inductor 102 that is perpendicular (e.g., normal) to the magnetic field lines passing through the interior of the integrated inductor 102. Because the inductance of the integrated inductor 102 is generally proportional to the size of the aperture 160 (and other factors), the inductance can be increased by increasing the size of the aperture 160. The inductance is further increased by the presence of one or more magnetic layers 130 located within the aperture 160 and extending along the length of the integrated inductor 102 (e.g., in…). FIG. 1 The orientation shown in the example extends in the direction of entering / exiting the paper (as described below).

[0036] As shown in the figure, FIG. 1 One or more magnetic layers 130 in the integrated inductor 102 include two magnetic layers 130A and 130B. Magnetic layer 130A is located in the lower portion of the aperture 160 and positioned above the first set of conductive lines 116. Magnetic layer 130A is located below the molding compound 122, and an insulating layer 118 is located between magnetic layer 130A and the first set of conductive lines 116. Magnetic layer 130B is located in the upper portion of the aperture 160 and positioned below the second set of conductive lines 126. Magnetic layer 130B is located above the molding compound 122, and an insulating layer 124 is located between magnetic layer 130B and the second set of conductive lines 126.

[0037] According to some specific embodiments, one or more magnetic layers 130 include one or more of CoZrTa, CoZrTaB, or FeCoB and can be formed via a sputtering deposition process. See reference... FIG. 7A and FIG. 7B As further described, one or more magnetic layers 130 can be formed using wafer-level processing techniques such as patterning, etching, and deposition techniques, which can be performed relatively quickly and have low cost and high reliability compared to conventional methods of providing high-inductance structures using wafer-level processes.

[0038] According to some specific embodiments, at least one of the input and output terminals of the integrated inductor 102 is coupled to solder balls 140. For example, in some configurations, the input terminal of the integrated inductor 102 is coupled to an active circuit 144 (e.g., a PMIC) on the substrate 110, and the output terminal of the integrated inductor 102 is coupled to solder balls 140. For illustration, the input terminal of the integrated inductor 102 may be located at a via 114A, which connects a conductive line 116A to the active circuit 144 at a first end of the integrated inductor 102. A 3D solenoid formed via the connection between conductive posts 120, conductive lines 116 and 126 provides a rectangular spiral current path through the integrated inductor 102, and the current path may terminate at solder balls 140A or 140B at the output terminal of the integrated inductor 102. In other configurations, both the input and output terminals of the integrated inductor 102 are coupled to the corresponding solder balls 140. For illustration, solder ball 140A can be connected to conductive line 126A at the input terminal of integrated inductor 102, and the current path through integrated inductor 102 can terminate at solder ball 140B at the output terminal of integrated inductor 102.

[0039] One strategy for providing high inductance at the wafer surface involves forming an inductor with a single linear conductive trace located above a flat magnetic layer and below a dome or shell of magnetic material. Using such methods, an inductor with dimensions of approximately 1 mm in length and 0.33 mm in width can have an inductance of approximately 6 nanohenries (nH) to 10 nH, which meets the area and inductance standards (e.g., 6 nH) for PMIC applications with switching frequencies of 100 MHz. However, the fabrication of the magnetic dome is a relatively lengthy and expensive process that may involve physical vapor deposition of multiple mask layers and thick dome material. In contrast, in a specific example, the integrated inductor 102 can provide approximately 11 nH within the same coverage area (1 mm × 0.33 mm) using a solenoid configuration surrounding planar magnetic layers 130A, 130B and fabricated using wafer-level processing techniques (e.g., planarization defined by sputtered photoresist). Compared to the fabrication of magnetic domes, wafer-level processing is relatively faster, less costly, and more reliable in the presence of mechanical stress. Therefore, the technical advantages of using the integrated inductor 102 with a solenoid configuration surrounding the planar magnetic layer 130 are shorter fabrication time, lower complexity with fewer mask layers, and higher reliability to achieve comparable or improved performance (e.g., high inductance) within the same coverage area.

[0040] although FIG. 1 The integrated inductor 102 depicted has two magnetic layers 130 within the aperture 160, but in other specific embodiments, the integrated inductor 102 includes a single magnetic layer 130, such as in the reference numeral. FIG. 2 and FIG. 3 Further described, or including more than two magnetic layers 130, such as reference FIG. 5 Further description.

[0041] although FIG. 1 An integrated inductor 102 is illustrated on surface 142 of substrate 110 (e.g., PMIC), but in other embodiments, the integrated inductor 102 is located within or on the package substrate, such as in reference numerals. FIG. 6B More detailed description.

[0042] FIG. 2 to FIG. 5 Each is illustrated with a schematic cross-sectional profile of a corresponding device including an exemplary integrated inductor. FIG. 2 to FIG. 5 The equipment includes the following as referenced above. FIG. 1 Many of the same components and features are described. These components and features are physically and operationally similar to those referenced above. FIG. 1 The same as described, and in FIG. 2 to FIG. 5 The same reference numerals are used for labeling.

[0043] FIG. 2Depicting including corresponding FIG. 1 An exemplary device 200 includes an integrated inductor 102 and an integrated inductor 202. The integrated inductor 202 includes a lower magnetic layer 130A and omits... FIG. 1 The upper magnetic layer is 130B. (See above for reference.) FIG. 1 In a specific example of the described integrated inductor 102, the integrated inductor 102 has a coverage area of ​​1 mm × 0.33 mm and an inductance of approximately 11 nH using two magnetic layers 130A and 130B. In contrast, a specific example of the integrated inductor 202 with a coverage area of ​​1 mm × 0.33 mm uses a single magnetic layer 130A in the aperture 160 and has an inductance of approximately 7.4 nH. Therefore, the lower magnetic layer 130A is included and omitted. FIG. 1 The technical advantage of the upper magnetic layer 130B is that the resulting integrated inductor 202 can be manufactured using fewer processing steps and less magnetic material than the integrated inductor 102, while still providing sufficient inductance (e.g., 7.4nH) to meet inductance standards (e.g., 6nH for 100MHz switching frequency PMIC applications).

[0044] FIG. 3 Depicting including corresponding FIG. 1 An exemplary device 300 includes an integrated inductor 102 and an integrated inductor 302. The integrated inductor 302 includes an upper magnetic layer 130B and omits... FIG. 1 The lower magnetic layer is 130A. FIG. 1 A specific example of the integrated inductor 102 has a coverage area of ​​1 mm × 0.33 mm and an inductance of approximately 11 nH using two magnetic layers 130A and 130B. In contrast, a specific example of the integrated inductor 302 with a coverage area of ​​1 mm × 0.33 mm uses a single magnetic layer 130B in the aperture 160 and has an inductance of approximately 7.2 nH. Therefore, the upper magnetic layer 130B is included and omitted. FIG. 1 The technical advantage of the lower magnetic layer 130A is that the resulting integrated inductor 302 can be manufactured using fewer processing steps and less magnetic material than the integrated inductor 102, while still providing sufficient inductance (e.g., 7.2nH) to meet inductance standards (e.g., 6nH for 100MHz switching frequency PMIC applications).

[0045] FIG. 4 Depicting including corresponding FIG. 1 An exemplary device 400 with an integrated inductor 102 and an integrated inductor 402. FIG. 1 Compared to the integrated inductor 102, the insulating layer 404 is located between the molding compound 122 and the insulating layer 124, and the magnetic layer 130B is located on the insulating layer 404.

[0046] Because the sputtering deposition of the magnetic layer 130B is an energy-intensive process that can eject epoxy resin material from the upper surface of the molding compound 122, the insulating layer 404 can be used to protect the molding compound 122 during manufacturing. For example, the insulating layer 404 may comprise a polyimide material that is more robust to sputtering deposition than the molding compound 122, which can reduce or eliminate the ejection of surface material during sputtering deposition. Therefore, the technical benefit of incorporating the insulating layer 404 is to reduce or eliminate ejected material that may contaminate the sputtering chamber during the deposition of the magnetic layer 130B.

[0047] FIG. 5 Depicting including corresponding FIG. 1 An exemplary integrated inductor 502 device 500 includes an integrated inductor 102, wherein one or more magnetic layers 130 comprise three magnetic layers within an aperture 160: a lower magnetic layer 130A, an upper magnetic layer 130B, and a third magnetic layer 130C. The integrated inductor 502 also includes... FIG. 4 An insulating layer 404 is positioned between the upper magnetic layer 130B and the molding compound 122.

[0048] An insulating layer 504 (such as a polyimide layer) is located between the insulating layer 118 and the molding compound 122, and a third magnetic layer 130C is located on the insulating layer 504. Although three magnetic layers 130 are depicted in the integrated inductor 502, in other embodiments, additional magnetic layers 130 may be included within the aperture 160. For example, one or more additional instances of the magnetic layers 130 on the insulating layer may be inserted above, below, or both of the third magnetic layer 130C.

[0049] Generally, the additional magnetic layer 130 provides increased inductance. Therefore, compared to having two magnetic layers 130... FIG. 1 Compared to the integrated inductor 102, the integrated inductor 502 with three magnetic layers 130 can have a higher inductance. Therefore, the technical advantage of including the third magnetic layer 130C is that the resulting integrated inductor 502 can provide higher inductance in the same coverage area as the integrated inductor 102.

[0050] Although FIG. 1 to FIG. 5 Each of these illustrates an example of an integrated inductor having a specific arrangement of an insulating layer, a magnetic layer, and a molding compound, but other embodiments may include one or more additional layers, one or fewer layers, or one or more different layers. For example, in some embodiments, one or more polyimide layers or other layers may be used to replace part (or all) of the molding compound 122. Furthermore, although FIG. 1 to FIG. 5An integrated inductor located on a wafer and used in conjunction with PMIC circuitry is illustrated as an example, but in other examples, such integrated inductors may alternatively be used in conjunction with: application processors, modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaA) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, and / or combinations thereof.

[0051] FIG. 6A A schematic top view of device 600 is depicted, and FIG. 6B A schematic perspective view of device 600 is depicted, which includes an integrated inductor 102 within or on a package substrate 604. FIG. 6C A schematic cross-sectional profile of a portion of an integrated inductor 102 is depicted. The integrated inductor 102 is configured as a seven-turn solenoid and includes a first row of seven conductive posts 120, comprising conductive posts 120A, 120C, 120E, 120G, 120I, 120K, and 120M. The integrated inductor 102 also includes a second row of seven conductive posts 120, comprising conductive post 120B. Magnetic layers 130A and 130B are located between the first and second rows of conductive posts and extend the length of the integrated inductor 102.

[0052] The second group of conductive wires 126 includes seven conductive wires 126A to 126G, which are arranged to electrically connect each of the conductive posts 120 in the first row to a corresponding conductive post 120 in the second row. For example, conductive wire 126A electrically connects conductive post 120A in the first row to conductive post 120B in the second row.

[0053] The first group of conductive lines 116 includes eight conductive lines 116A to 116H. Conductive line 116A electrically connects the inductor input terminal 610 (e.g., a contact pad and / or one of the solder balls 140A, 140B) to a conductive post 120A in the first row. Conductive lines 116B to 116G are arranged to electrically connect each of the conductive posts 120 in the second row to the next conductive post 120 in the first row. For example, conductive line 116B electrically connects the conductive post 120B in the second row to the next conductive post 120C in the first row. Conductive line 116H electrically connects the last conductive post 120 in the second row to the inductor output terminal 612 (e.g., a contact pad and / or another solder ball 140A, 140B).

[0054] Therefore, the current along the current path configured by the 3D solenoid of the integrated inductor 102 begins at the inductor input 610 and flows along conductor 116A, upwards to conductor 120A, along conductor 126A to conductor 120B, and downwards to conductor 120B to complete the first solenoid loop of the integrated inductor 102. The current flows in a similar manner along the remaining six solenoid loops formed via conductors 116A to 116H, conductors 126B to 126G, and conductor 120, and exits along conductor 116H to the inductor output 612.

[0055] In a specific implementation, device 600 corresponds to a test device, wherein the integrated inductor 102 is configured as a seven-turn solenoid, the solenoid being approximately 1 mm long (e.g., the distance from conductive line 126A to conductive line 126G is approximately 1 mm) and 0.33 mm wide (e.g., the distance from conductive post 120A to conductive post 120B is approximately 0.33 mm). With the height of the conductive post 120 and the thickness of the molding compound 122 in the range of approximately 75 micrometers to 100 micrometers, the conductive lines 116 and 126 each having a thickness of approximately 12 micrometers, and the magnetic layers 130A and 130B each having a thickness of approximately 4 micrometers, the previously referenced [feature / condition] can be achieved. FIG. 1 The inductance described is approximately 11nH.

[0056] Although device 600 is depicted as including integrated inductor 102, in other embodiments, device 600 may alternatively or additionally include one or more of integrated inductor 202, integrated inductor 302, integrated inductor 402 or integrated inductor 502.

[0057] Exemplary processes for fabricating integrated inductors including magnetic layers In some specific implementations, manufacturing an integrated inductor that includes one or more magnetic layers (e.g., any one of integrated inductors 102, 202, 302, 402, or 502) involves several processes. FIG. 7A to FIG. 7C Exemplary steps for providing or manufacturing an integrated inductor, which includes one or more magnetic layers, as shown in the reference. FIG. 1 to FIG. 6C As described by any of them. In some specific implementations, FIG. 7A to FIG. 7C The process can be used to provide FIG. 1 to FIG. 6C One or more of the following devices: 100, 200, 300, 400, 500 or 600 (e.g., provided during their manufacture).

[0058] It should be noted that the processes in Figures 10A to 10E may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of processes may be changed or modified. In some embodiments, one or more processes may be substituted or replaced without departing from the scope of this disclosure. In the description below, reference is made to various exemplary stages of the processes, which... FIG. 7A to FIG. 7C Numbered in the middle (using circled numbers).

[0059] FIG. 7A Stage 1 illustrates a state after a first layer 712 has been formed on a substrate 710, such as a wafer, and patterned to form openings 713A, 713B exposing the surface of the substrate 710. The openings 713 can be formed using patterning operations, etching processes, drilling operations, laser ablation operations, other targeted removal operations, or combinations thereof. In a particular embodiment, the substrate 710 is a PMIC wafer, and the first layer 712 is a first polyimide layer coated onto and patterned on the substrate 710. According to one aspect, the substrate 710 corresponds to... FIG. 1 The substrate 110, and the first layer 712 corresponds to the insulating layer 112.

[0060] Phase 2 illustrates the state after the formation of vias 714A, 714B of the first via layer (“V0”) and conductive lines 716 of the first redistribution layer. For example, vias 714A, 714B and conductive lines 716 can be formed by applying a metallic material (e.g., copper) into the openings 713A, 713B of the first layer 712 and onto the surface of the first layer 712. For illustration, one or more plating processes (e.g., electroplating) and one or more patterning processes can be used to apply the metallic material to form vias 714 and conductive lines 716. For example, a photoresist process can be performed to create a pattern to guide the structure and positioning of conductive lines 716, and a photoresist ashing or stripping operation can be performed after the formation of conductive lines 716 to remove the photoresist layer. Although not shown in the figures, such photoresist layers can be used during deposition and / or etching processes. Similarly, other processing steps, such as cleaning, planarization, etc., can be performed, which may also be omitted from the figures and / or description. According to one aspect, via 714 corresponds to... FIG. 1 The via 114, and the conductive line 716 corresponds to the conductive line 116.

[0061] Phase 3 illustrates the state after a second layer 718 has been formed over the conductive line 716 and the first layer 712, and a first magnetic layer 730A has been formed over the second layer 718. In a particular embodiment, the second layer 718 is a second polyimide layer coated onto the conductive line 716 and the first layer 712. The first magnetic layer 730A can be formed by applying photoresist to the surface of the second layer 718 and performing one or more sputtering deposition processes. In a particular embodiment, the first magnetic layer 730A includes one or more of CoZrTa, CoZrTaB, or FeCoB. According to one aspect, the second layer 718 corresponds to... FIG. 1 The insulating layer 118, and the first magnetic layer 730A corresponds to the magnetic layer 130A.

[0062] Phase 4 illustrates the state after the formation of vias 719A and 719B of the second via layer (“V1”) and pillars 720A and 720B of the third via layer (“V2”). In a particular embodiment, the vias 719 and pillars 720 are formed by forming openings in the second layer 718 to expose portions of the conductive lines 716, followed by one or more plating processes (e.g., electroplating). The openings in the second layer 718 can be formed using patterning operations, etching processes, drilling operations, laser ablation operations, other targeted removal operations, or combinations thereof. Prior to the plating process, a photoresist patterning process can be performed to guide the structure and positioning of the pillars 720, and a photoresist ashing or stripping operation can be performed after the formation of the pillars 720. In some embodiments, pillars 720 correspond to giant pillars, and the vias 719 and pillars 720 are formed of copper. According to one aspect, pillars 720 correspond to FIG. 1 Column 120.

[0063] FIG. 7B Stage 5 illustrates the state after applying molding compound 722 and back-grinding to form a generally flat top surface of molding compound 722 and pillar 720. In a particular example, a deposition process, spin coating process, or similar process may be used to apply molding compound 722, and molding compound 722 may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners. According to one aspect, molding compound 722 corresponds to FIG. 1 Molded compound 122.

[0064] Stage 6 illustrates the state after a third layer 723 has been formed on the upper surface of pillar 720 and over molding compound 722, and a second magnetic layer 730B has been formed on the third layer 723. In a particular embodiment, the third layer 723 is a third polyimide layer coated onto the upper surface of pillar 720 and over molding compound 722. The second magnetic layer 730B can be formed by forming a patterned photoresist layer on the surface of the third layer 723 and performing one or more sputtering deposition processes, followed by photoresist ashing or stripping operations. In a particular embodiment, the second magnetic layer 730B includes one or more of CoZrTa, CoZrTaB, or FeCoB. According to one aspect, the third layer 723 corresponds to FIG. 4 The insulating layer 404, and the second magnetic layer 730B corresponds to the magnetic layer 130B.

[0065] Phase 7 illustrates the state after a fourth layer 724 has been formed over the third layer 723 and the second magnetic layer 730B and has been patterned to form openings 725A, 725B exposing the upper surface of the pillar 720. In a particular embodiment, the fourth layer 724 is a polyimide layer coated onto the third layer 723 and the second magnetic layer 730B. The openings 725 can be formed using patterning operations, etching processes, drilling operations, laser ablation operations, other targeted removal operations, or combinations thereof. According to one aspect, the fourth layer 724 corresponds to... FIG. 1 Insulation layer 124.

[0066] FIG. 7C Stage 8 illustrates the state after the formation of vias 727A, 727B of the fourth via layer (“V3”) and the conductive line 726 of the second redistribution layer. For example, vias 727 and conductive lines 726 can be formed by applying a metallic material (e.g., copper) into the opening 725 and onto the surface of the fourth layer 724. For illustration, one or more plating processes (e.g., electroplating) and one or more patterning processes can be used to apply the metallic material to form vias 727 and conductive lines 726. According to one aspect, conductive line 726 corresponds to... FIG. 1 Conductive wire 126.

[0067] Phase 9 illustrates the state after a fifth layer 728 has been formed over the fourth layer 724 and the conductive line 726 and has been patterned to form openings 729A, 729B exposing portions of the upper surface of the conductive line 726. In a particular embodiment, the fifth layer 728 is a polyimide layer coated onto the exposed portions of the conductive line 726 and the fourth layer 724. The openings 729 can be formed using patterning operations, etching processes, drilling operations, laser ablation operations, other targeted removal operations, or combinations thereof. According to one aspect, the fifth layer 728 corresponds to... FIG. 1 Insulation layer 128.

[0068] Stage 10 illustrates the state after the solder balls 740A and 740B have been formed. For example, one or more plating processes and one or more patterning processes can be used to form the solder balls 740. In another example, the solder balls 740 can be inserted or placed in position. According to one aspect, the solder balls 740 correspond to... FIG. 1 140 solder balls.

[0069] The integrated inductor 702 is formed in FIG. 7C This is completed after stage 10. However, in some specific implementations, one or more of stages 1 to 10 may be modified or skipped, one or more stages may be added, or a combination thereof may be combined. For illustration, in the first example, stage 3 may be modified to omit the formation of the first magnetic layer 730A, such that the integrated inductor 702 does not include a lower magnetic layer, such as to generate FIG. 3 The integrated inductor 302.

[0070] In the second example, stage 6 can be skipped to omit the formation of the third layer 723 and the second magnetic layer 730B, such that the integrated inductor 702 does not include the upper magnetic layer, as to generate FIG. 2 The integrated inductor 202.

[0071] In the third example, stage 6 can be modified to omit the formation of the third layer 723, such that the second magnetic layer 730B is formed on the molding compound 722, for example to produce FIG. 1 The integrated inductor 102.

[0072] In the fourth example, one or more additional stages may be added between stage 3 and stage 4 to form one or more additional magnetic layers. Each of the additional stages may include forming an additional layer on the upper surface of the existing structure (e.g., by coating a polyimide layer onto the upper surface) and forming a magnetic layer on the additional layer in a manner similar to that described in forming the second layer 718 and the first magnetic layer 730A in stage 3. For illustration, adding such an additional stage after stage 3 may result in the integrated inductor 702 as... FIG. 5 The diagram depicts an integrated inductor 702 with a third magnetic layer 130C on an insulating layer 504, which can correspond to... FIG. 5 The integrated inductor 502.

[0073] Exemplary flowcharts of methods for fabricating integrated inductors including magnetic layers In some specific implementations, manufacturing an integrated inductor that includes one or more magnetic layers involves several processes. FIG. 8 An exemplary flowchart illustrating a method 800 for providing or manufacturing an integrated inductor comprising one or more magnetic layers is shown. In some specific embodiments, FIG. 8 Method 800 can be used to provide or manufactureFIG. 1 to FIG. 5 Any one of the integrated inductors 102, 202, 302, 402 or 502.

[0074] It should be noted that FIG. 8 Method 800 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated inductors. In some specific implementations, the order of processes may be changed or modified.

[0075] At block 802, method 800 includes forming a first set of conductive lines. For example, the first set of conductive lines may correspond to a first set of conductive lines 116 formed above surface 142 of any of devices 100, 200, 300, 400, 500, or 600. In some specific embodiments, FIG. 7A Phases 1 and 2 illustrate and describe an example of forming the first set of conductive lines above the surface of the wafer.

[0076] At block 804, method 800 includes forming one or more magnetic layers above the first set of conductive lines. In a particular embodiment, the one or more magnetic layers include one or more of CoZrTa, CoZrTaB, or FeCoB. For example, the one or more magnetic layers may correspond to one or more magnetic layers 130 of any of devices 100, 200, 300, 400, 500, or 600, and may include magnetic layer 130A of any of devices 100, 200, 400, 500, or 600, magnetic layer 130B of any of devices 100, 300, 400, 500, or 600, magnetic layer 130C of device 500, or any combination thereof. In some embodiments, FIG. 7A Phase 3 and FIG. 7B Stage 6 illustrates and describes an example of forming a magnetic layer above the first set of conductive lines.

[0077] At block 806, method 800 includes forming conductive posts connected to a first set of conductive wires. For example, the conductive posts may correspond to conductive posts 120 of any of devices 100, 200, 300, 400, 500, or 600. In some specific embodiments, FIG. 7A Phase 4 illustrates and describes an example of forming conductive posts connected to the first set of conductive wires.

[0078] At block 808, method 800 includes forming a second set of conductive lines connected to conductive posts over one or more magnetic layers to form an integrated inductor, wherein the one or more magnetic layers extend along the length of the integrated inductor and within the apertures of the integrated inductor. For example, the second set of conductive lines may correspond to a second set of conductive lines 126 formed over one or more magnetic layers 130 and connected to conductive posts 120 to form an integrated inductor of any of devices 100, 200, 300, 400, 500, or 600. In some specific embodiments, FIG. 7B Phase 7 and FIG. 7C Stage 8 illustrates and describes an example of forming a second set of conductive lines connected to conductive pillars above one or more magnetic layers.

[0079] Optionally, method 800 includes encapsulating the conductive pillar at least partially in a molding compound. For example, the molding compound may correspond to molding compound 122 of any of devices 100, 200, 300, 400, or 500, and FIG. 7B Phase 5 illustrates and describes an example of at least partially encapsulating conductive pillars within a molding compound. In some specific embodiments, method 800 further includes forming an insulating layer above a first set of conductive lines, wherein a magnetic layer of one or more magnetic layers is located above the insulating layer and below the molding compound. For example, the magnetic layer may correspond to magnetic layer 130A located above insulating layer 118 and below molding compound 122, and FIG. 7A Stage 3 illustrates and describes an example of forming an insulating layer and a magnetic layer above the first set of conductive lines and below the molding compound.

[0080] In other specific embodiments, method 800 includes forming a first insulating layer above a first set of conductive lines, wherein a first magnetic layer of one or more magnetic layers is located above the first insulating layer, and further forming a second insulating layer above the first insulating layer and the first magnetic layer, wherein the second magnetic layer of one or more magnetic layers is located above the second insulating layer and below the molding compound. For example, the first insulating layer may correspond to insulating layer 118, the first magnetic layer may correspond to magnetic layer 130A, the second insulating layer may correspond to insulating layer 504, and the second magnetic layer may correspond to... FIG. 5 The magnetic layer is 130C.

[0081] Optionally, a magnetic layer is formed over a molding compound, and an insulating layer is located above the magnetic layer and below the second set of conductive lines. For example, in devices 100, 300, 400, 500, or 600, a magnetic layer 130B is formed over a molding compound 122, and an insulating layer 124 is located above the magnetic layer 130B and below the second set of conductive lines 126. In some specific embodiments, FIG. 7BStage 7 illustrates and describes an example of forming a magnetic layer over the molding compound and forming an insulating layer over the magnetic layer and below the second set of conductive lines.

[0082] Optionally, the integrated inductor is formed on the surface of the power management integrated circuit (PMIC), and the input of the integrated inductor is coupled to the circuitry of the PMIC. For example, FIG. 1 The via 114A can couple the input of the integrated inductor 102 to the active circuit 144.

[0083] Exemplary electronic devices FIG. 9 Examples of various electronic devices that may include or be integrated with any of devices 100, 200, 300, 400, 500, or 600 are illustrated. For example, mobile phone device 902, laptop computer device 904, fixed-location terminal device 906, wearable device 908, or vehicle 910 (e.g., automotive or aerospace equipment) may include device 900. Device 900 may include, for example, any of devices 100, 200, 300, 400, 500, or 600 as described herein and / or any of integrated inductors 102, 202, 302, 402, or 502. FIG. 9 The devices 902, 904, 906, and 908 illustrated in the diagram, as well as vehicle 910, are merely exemplary. Other electronic devices may also feature device 900, including (but not limited to) a group of devices (e.g., electronic devices) that include mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0084] FIG. 1 to FIG. 9 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that in this disclosure… FIG. 1 to FIG. 9 The corresponding descriptions are not limited to dies and / or ICs. In some specific implementations, FIG. 1 to FIG. 9The descriptions and their corresponding information can be used to manufacture, form, provide, and / or produce equipment and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0085] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0086] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then object A and object C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning that an object can partially or completely enclose another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” the second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, the first component may be located above (e.g., above) a first surface of the second component, and the third component may be located above (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "first component over second component" can mean: (1) the first component is over the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​from about X to XX can refer to values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X".For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "Multiple" components can include all possible components or only some of all possible components. For example, if a device comprises ten components, the term "multiple components" can refer to all ten components or only some of those ten components.

[0087] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0088] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0089] Further embodiments are described below to facilitate understanding of this disclosure.

[0090] According to Embodiment 1, an inductor includes: a first set of conductive lines; a second set of conductive lines; conductive pillars connecting the first set of conductive lines to the second set of conductive lines to form an integrated inductor; and one or more magnetic layers extending along the length of the integrated inductor and within the apertures of the integrated inductor.

[0091] Example 2 includes the inductor device according to Example 1, wherein the integrated inductor is located within or on the package substrate.

[0092] Example 3 includes an inductor device according to Example 1 or Example 2, wherein the one or more magnetic layers include one or more of CoZrTa, CoZrTaB or FeCoB.

[0093] Example 4 includes an inductor according to any one of Examples 1 to 3, wherein the first set of conductive lines is located above the wafer surface, wherein a magnetic layer of one or more magnetic layers is located above the first set of conductive lines and below the second set of conductive lines, and the inductor further includes a molding compound located between the first set of conductive lines and the second set of conductive lines.

[0094] Example 5 includes the inductor device according to Example 4, wherein the molding compound comprises an epoxy resin material.

[0095] Example 6 includes the inductor device according to Example 4 or Example 5, and further includes an insulating layer located between the magnetic layer and the first set of conductive lines or the second set of conductive lines.

[0096] Example 7 includes the inductor device according to Example 6, wherein the insulating layer comprises a polyimide material.

[0097] Example 8 includes an inductor according to Example 6 or Example 7, wherein the insulating layer is located between the magnetic layer and the first set of conductive lines, and wherein the magnetic layer is located below the molding compound.

[0098] Example 9 includes an inductor according to Example 6 or Example 7, wherein the insulating layer is located between the magnetic layer and the second set of conductive lines, and wherein the magnetic layer is located above the molding compound.

[0099] Example 10 includes an inductor according to any one of Examples 1 to 9, wherein the one or more magnetic layers include two magnetic layers within the aperture.

[0100] Example 11 includes an inductor according to any one of Examples 1 to 9, wherein the one or more magnetic layers include three magnetic layers within the aperture.

[0101] Example 12 includes an inductor according to any one of Examples 1 to 11, wherein the first set of conductive lines is located in a first redistribution layer, and wherein the second set of conductive lines is located in a second redistribution layer.

[0102] Example 13 includes an inductor device according to any one of Examples 1 to 12, wherein the integrated inductor is formed on the surface of a power management integrated circuit (PMIC), and wherein the input terminal of the integrated inductor is coupled to the circuitry of the PMIC.

[0103] Example 14 includes an inductor according to any one of Examples 1 to 13, wherein at least one of the input terminal of the integrated inductor and the output terminal of the integrated inductor is coupled to a solder ball.

[0104] According to Embodiment 15, an apparatus includes an integrated device comprising: a first set of conductive lines; a second set of conductive lines; conductive posts connecting the first set of conductive lines to the second set of conductive lines to form an integrated inductor; and one or more magnetic layers extending along the length of the integrated inductor and within the apertures of the integrated inductor.

[0105] Example 16 includes the device according to Example 15, and further includes a packaging substrate, wherein the integrated inductor is located within or on the packaging substrate.

[0106] Example 17 includes the device according to Example 15 or Example 16, wherein the one or more magnetic layers include one or more of CoZrTa, CoZrTaB or FeCoB.

[0107] Example 18 includes the device according to any one of Examples 15 to 17, wherein the first set of conductive lines is located above the wafer surface, wherein a magnetic layer of one or more magnetic layers is located above the first set of conductive lines and below the second set of conductive lines, and the device further includes a molding compound located between the first set of conductive lines and the second set of conductive lines.

[0108] Example 19 includes the apparatus according to Example 18, wherein the molding compound comprises an epoxy resin material.

[0109] Example 20 includes the device according to Example 18 or Example 19, and further includes an insulating layer located between the magnetic layer and the first set of conductive lines or the second set of conductive lines.

[0110] Example 21 includes the device according to Example 20, wherein the insulating layer comprises a polyimide material.

[0111] Example 22 includes the device according to Example 20 or Example 21, wherein the insulating layer is located between the magnetic layer and the first set of conductive lines, and wherein the magnetic layer is located below the molding compound.

[0112] Example 23 includes the device according to Example 20 or Example 21, wherein the insulating layer is located between the magnetic layer and the second set of conductive lines, and wherein the magnetic layer is located above the molding compound.

[0113] Example 24 includes the device according to any one of Examples 15 to 23, wherein the one or more magnetic layers include a magnetic layer within the pore.

[0114] Example 25 includes the device according to any one of Examples 15 to 23, wherein the one or more magnetic layers comprise a plurality of magnetic layers within the pores.

[0115] Example 26 includes the device according to any one of Examples 15 to 23, wherein the one or more magnetic layers comprise two magnetic layers within the pore.

[0116] Example 27 includes the device according to any one of Examples 15 to 23, wherein the one or more magnetic layers comprise three magnetic layers within the pore.

[0117] Example 28 includes the device according to any one of Examples 15 to 27, wherein the first set of conductive lines is located in a first redistribution layer, and wherein the second set of conductive lines is located in a second redistribution layer.

[0118] Example 29 includes a device according to any one of Examples 15 to 28, wherein the integrated inductor is formed on the surface of a power management integrated circuit (PMIC), and wherein the input of the integrated inductor is coupled to the circuitry of the PMIC.

[0119] Example 30 includes the device according to any one of Examples 15 to 29, wherein at least one of the input terminal of the integrated inductor and the output terminal of the integrated inductor is coupled to a solder ball.

[0120] According to Embodiment 31, a method of manufacturing an inductor includes: forming a first set of conductive lines; forming one or more magnetic layers above the first set of conductive lines; forming conductive pillars connected to the first set of conductive lines; and forming a second set of conductive lines connected to the conductive pillars above the one or more magnetic layers to form an integrated inductor, wherein the one or more magnetic layers extend along the length of the integrated inductor and within the apertures of the integrated inductor.

[0121] Example 32 includes the method according to Example 31, wherein the one or more magnetic layers include one or more of CoZrTa, CoZrTaB or FeCoB.

[0122] Example 33 includes the method according to Example 31 or Example 32, wherein the first set of conductive lines is located above the wafer surface.

[0123] Example 34 includes the method according to any one of Examples 31 to 33, and further includes encapsulating the conductive pillar at least partially in a molding compound.

[0124] Example 35 includes the method according to Example 34, wherein the molding compound comprises an epoxy resin material.

[0125] Example 36 includes the method according to Example 34 or Example 35, and further includes forming an insulating layer above the first set of conductive lines, wherein the magnetic layer of the one or more magnetic layers is located above the insulating layer and below the molding compound.

[0126] Example 37 includes the method described in Example 36, wherein the insulating layer comprises a polyimide material.

[0127] Example 38 includes the method according to Example 34 or Example 35, and further includes forming a first insulating layer above the first set of conductive lines, wherein a first magnetic layer of one or more magnetic layers is located above the first insulating layer; and forming a second insulating layer above the first insulating layer and the first magnetic layer, wherein a second magnetic layer of one or more magnetic layers is located above the second insulating layer and below the molding compound.

[0128] Example 39 includes the method according to any one of Examples 34 to 38, wherein the magnetic layer is located above the molding compound, and wherein the insulating layer is located above the magnetic layer and below the second set of conductive lines.

[0129] Example 40 includes the method according to any one of Examples 31 to 39, wherein the integrated inductor is formed on the surface of a power management integrated circuit (PMIC), and wherein the input terminal of the integrated inductor is coupled to the circuitry of the PMIC.

[0130] Example 41 includes the method according to any one of Examples 31 to 40, wherein the integrated inductor is located within or on the package substrate.

[0131] Example 42 includes the method according to any one of Examples 31 to 41, wherein the first set of conductive lines is located in a first redistribution layer, and wherein the second set of conductive lines is located in a second redistribution layer.

[0132] Example 43 includes the method according to any one of Examples 31 to 42, wherein at least one of the input terminal of the integrated inductor and the output terminal of the integrated inductor is coupled to a solder ball.

[0133] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An inductor device, the inductor device comprising: First group of conductive wires; The second set of conductive wires; A conductive post that connects the first set of conductive lines to the second set of conductive lines to form an integrated inductor; and One or more magnetic layers extend along the length of the integrated inductor and within the apertures of the integrated inductor.

2. The inductor according to claim 1, wherein the integrated inductor is located within or on the package substrate.

3. The inductor according to claim 1, wherein the one or more magnetic layers comprise one or more of CoZrTa, CoZrTaB, or FeCoB.

4. The inductor of claim 1, wherein the first set of conductive lines is located above the wafer surface, wherein the magnetic layer of the one or more magnetic layers is located above the first set of conductive lines and below the second set of conductive lines, and the inductor further comprises a molding compound located between the first set of conductive lines and the second set of conductive lines.

5. The inductor according to claim 4, wherein the molding compound comprises an epoxy resin material.

6. The inductor according to claim 4, wherein the inductor further comprises an insulating layer located between the magnetic layer and the first group of conductive lines or the second group of conductive lines.

7. The inductor of claim 6, wherein the insulating layer comprises a polyimide material.

8. The inductor of claim 6, wherein the insulating layer is located between the magnetic layer and the first set of conductive lines, and wherein the magnetic layer is located below the molding compound.

9. The inductor of claim 6, wherein the insulating layer is located between the magnetic layer and the second set of conductive lines, and wherein the magnetic layer is located above the molding compound.

10. The inductor of claim 1, wherein the one or more magnetic layers comprise two magnetic layers within the aperture.

11. The inductor of claim 1, wherein the one or more magnetic layers comprise three magnetic layers within the aperture.

12. The inductor of claim 1, wherein the first set of conductive lines is located in a first redistribution layer, and wherein the second set of conductive lines is located in a second redistribution layer.

13. The inductor of claim 1, wherein the integrated inductor is formed on the surface of a power management integrated circuit (PMIC), and wherein the input terminal of the integrated inductor is coupled to the circuitry of the PMIC.

14. The inductor of claim 1, wherein at least one of the input terminal of the integrated inductor and the output terminal of the integrated inductor is coupled to a solder ball.

15. An apparatus, the apparatus comprising: Integrated device, the integrated device comprising: First group of conductive wires; The second set of conductive wires; Conductive posts, which connect the first set of conductive lines to the second set of conductive lines to form an integrated inductor; and One or more magnetic layers extend along the length of the integrated inductor and within the apertures of the integrated inductor.

16. The device of claim 15, further comprising a packaging substrate, wherein the integrated inductor is located within or on the packaging substrate.

17. The device of claim 15, wherein the one or more magnetic layers comprise one or more of CoZrTa, CoZrTaB, or FeCoB.

18. The device of claim 15, wherein the first set of conductive lines is located above the wafer surface, wherein a magnetic layer of one or more magnetic layers is located above the first set of conductive lines and below the second set of conductive lines, and the device further comprises a molding compound located between the first set of conductive lines and the second set of conductive lines.

19. The device of claim 15, wherein the one or more magnetic layers comprise a magnetic layer within the pore.

20. The device of claim 15, wherein the one or more magnetic layers comprise a plurality of magnetic layers within the pores.

21. The device of claim 15, wherein the first set of conductive lines is located in a first redistribution layer, and wherein the second set of conductive lines is located in a second redistribution layer.

22. The device of claim 15, wherein the integrated inductor is formed on the surface of a power management integrated circuit (PMIC), and wherein the input terminal of the integrated inductor is coupled to the circuitry of the PMIC.

23. A method for manufacturing an inductor, the method comprising: The first set of conductive lines is formed; One or more magnetic layers are formed above the first set of conductive lines; Form conductive posts connected to the first set of conductive wires; as well as A second set of conductive lines connected to the conductive pillars is formed above the one or more magnetic layers to form an integrated inductor. The one or more magnetic layers extend along the length of the integrated inductor and within the apertures of the integrated inductor.

24. The method of claim 23, wherein the one or more magnetic layers comprise one or more of CoZrTa, CoZrTaB, or FeCoB.

25. The method of claim 23, wherein the first set of conductive lines is located above the wafer surface.

26. The method of claim 23, further comprising encapsulating at least partially the conductive pillar in a molding compound.

27. The method of claim 26, further comprising forming an insulating layer above the first set of conductive lines, wherein a magnetic layer of one or more magnetic layers is located above the insulating layer and below the molding compound.

28. The method according to claim 26, further comprising: A first insulating layer is formed above the first set of conductive lines, wherein the first magnetic layer of one or more magnetic layers is located above the first insulating layer; A second insulating layer is formed over the first insulating layer and the first magnetic layer, wherein the second magnetic layer of the one or more magnetic layers is located above the second insulating layer and below the molding compound.

29. The method of claim 26, wherein the magnetic layer is located above the molding compound, and wherein the insulating layer is located above the magnetic layer and below the second set of conductive lines.

30. The method of claim 23, wherein the integrated inductor is formed on the surface of a power management integrated circuit (PMIC), and wherein the input of the integrated inductor is coupled to the circuitry of the PMIC.

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