Hybrid current-limiting control method for direct-current side fault of half-bridge modular multilevel converter

Abstract

The invention discloses a hybrid current-limiting control method for a DC side fault of a half-bridge modular multilevel converter, and relates to the technical field of power system protection, and the method comprises the following steps: continuously obtaining a DC voltage and a DC current change rate; when the direct current is lower than the corresponding preset threshold value and the direct current change rate exceeds the corresponding preset limit value, it is judged that a fault occurs, and current limiting control is activated; and performing current-limiting control based on a double-layer hybrid control method to realize fault current suppression. According to the hybrid control-based current limiting method special for the half-bridge MMC direct-current power grid, on the basis of a double-layer hybrid control method, the DCCB breaking stress is relieved, the fault ride-through capability of a converter is improved, and effective fault current suppression is achieved under the condition that system complexity and coordination difficulty are not increased.

Description

Technical Field

[0001] This invention relates to the field of power system protection technology, and more specifically, to a hybrid current limiting control method for DC-side faults in a half-bridge modular multilevel converter. Background Technology

[0002] In China, power resources are unevenly distributed, and flexible DC grids based on overhead lines are increasingly used for long-distance, high-capacity power transmission. However, compared with cable lines, overhead DC systems have a higher failure rate, and due to their inherent low damping and low inertia, short-circuit faults can lead to extremely high and rapidly rising fault currents, seriously threatening converter safety and grid stability.

[0003] Existing practical engineering projects mostly use half-bridge submodules, which themselves lack DC fault blocking capabilities. In such configurations, DC faults are cleared in coordination with high-voltage DC circuit breakers (DCCBs), promptly isolating the faulty section. However, the realization of high-capacity DCCBs still faces technical challenges and cost pressures, limiting the scalability of high-voltage multi-terminal DC networks. Therefore, developing effective current-limiting control schemes has become a key research direction.

[0004] Rate limiting methods can generally be divided into two categories. The first category involves adding an auxiliary fault current limiter (FCL)—such as a superconducting or hybrid device—to increase the fault path impedance, or utilizing a DC-DC converter with built-in current limiting function, such as the "Short-circuit fault current limiter and its control method" disclosed in patent CN120454001A. Its core structure includes a capacitor, an IGBT module, and a diode group. The characteristics and working principle of this scheme are: during normal operation, the IGBT is turned on and the device is bypassed, with minimal impact on the system; during a fault, the IGBT is quickly turned off, and a pre-charged capacitor is connected in series in the fault circuit. The high impedance presented by the capacitor during charging is used to quickly limit the current rise. The advantage of this type of scheme based on an external FCL is its fast response speed and compatibility with existing half-bridge MMC topologies. However, its inherent limitation is that it still adds an independent hardware device connected in series in the line, which inevitably increases the complexity of the system, the footprint, the equipment cost, and the potential fault points. The second category focuses on converter topology improvement, designing sub-modules that can essentially suppress fault currents, such as the "Modular Multilevel DC / DC Converter" disclosed in patent CN118232683A. The core feature of this scheme is that the bridge arm of its power main circuit can be composed of one or more hybrid components such as half-bridge sub-module (HBSM), full-bridge sub-module (FBSM), and clamped twin sub-module (CDSM). This topology design gives the DC / DC converter functional advantages and inherent safety advantages. Although both methods have been proven effective, they often increase system complexity and coordination difficulty, reducing the feasibility of engineering implementation.

[0005] To address the above problems, this invention proposes a solution. Summary of the Invention

[0006] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide a hybrid current limiting control method for DC-side faults in half-bridge modular multilevel converters. This method, based on hybrid control and specifically designed for half-bridge MMC DC grids, addresses the problem of fault currents severely threatening converter safety and grid stability.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A hybrid current limiting control method for DC-side faults in a half-bridge modular multilevel converter includes the following steps: continuously acquiring the DC voltage and DC current change rate; when the DC current is lower than the corresponding preset threshold and the DC current change rate exceeds the corresponding preset limit, a fault is determined to have occurred, and current limiting control is activated; current limiting control is performed based on a two-layer hybrid control method to achieve fault current suppression.

[0008] In a preferred embodiment, the continuous acquisition of DC voltage and DC current change rate includes a detection module that employs a low-pass filter and voting logic to suppress transient noise.

[0009] In a preferred embodiment, the dual-layer hybrid control method includes an outer-loop preset command current limiting and an adaptive current limiting based on DC voltage changes. Specifically, the outer-loop preset command current limiting restricts the active power injected from the AC side after a fault, reducing the transient peak values ​​of AC current and bridge arm current; the adaptive current limiting is based on DC voltage changes, and dynamically adjusts the number of connected sub-modules by constructing a correction coefficient to suppress fault current.

[0010] In a preferred embodiment, limiting the active power injected from the AC side includes introducing a command reset signal to clear the PI controller output upon detecting a fault, thereby setting the d-axis current component reference value to zero.

[0011] In a preferred embodiment, the steps for constructing the correction coefficient are as follows: when a fault occurs, the instantaneous value of the DC voltage is divided by the steady-state value of the DC voltage to obtain the relative voltage coefficient; the relative voltage coefficient is corrected to obtain the correction coefficient.

[0012] In a preferred embodiment, the dual-layer hybrid control method includes coordinating with the DC circuit breaker to minimize fault current stress and breaking energy during DC circuit breaker operation.

[0013] In a preferred embodiment, an electronic device is characterized by comprising a processor and a storage medium; the storage medium is used to store instructions; and the processor is used to operate according to the instructions to perform the steps of the method according to any one of claims 1-6.

[0014] In a preferred embodiment, a computer-readable storage medium stores a computer program thereon, characterized in that the program, when executed by a processor, implements the steps of the method according to any one of claims 1-6.

[0015] In a preferred embodiment, a computer program product includes a computer program / instructions, characterized in that, when executed by a processor, the computer program / instructions implement the steps of the method according to any one of claims 1-6.

[0016] The technical effects and advantages of the hybrid current limiting control method for DC-side faults in half-bridge modular multilevel converters of the present invention are as follows: This invention provides a hybrid control-based current limiting method specifically for half-bridge MMC DC grids. Based on a two-layer hybrid control method, it reduces DCCB breaking stress, improves the fault ride-through capability of the converter, and achieves effective fault current suppression without increasing system complexity or coordination difficulty. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a hybrid current limiting control method for DC-side faults in a half-bridge modular multilevel converter, provided in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the MMC topology.

[0019] Figure 3 This is a schematic diagram of a current-limiting combination control method.

[0020] Figure 4 This is a schematic diagram of a current-limiting controller that uses pre-determined outer-loop control commands.

[0021] Figure 5 A schematic diagram of the MMC control structure considering current limiting measures.

[0022] Figure 6 This is a schematic diagram of an adaptive current limiting controller based on DC voltage variation.

[0023] Figure 7 This is a schematic diagram of the equivalent model for a DC-side short-circuit fault.

[0024] Figure 8 This is a schematic diagram of a four-terminal DC power grid.

[0025] Figure 9 This is a schematic diagram of the DC bus current of MMC1.

[0026] Figure 10 This is a schematic diagram of the DC bus current of MMC2.

[0027] Figure 11 This is a schematic diagram comparing the active power before and after an AC system fault.

[0028] Figure 12 This is a schematic diagram of the active power before and after a fault at each converter station in the AC system.

[0029] Figure 13 This is a schematic diagram showing the AC current without current limitation before and after an MMC1 fault.

[0030] Figure 14 This diagram illustrates the AC current before and after an MMC1 fault when using this method.

[0031] Figure 15 This is a schematic diagram illustrating the AC current usage method A before and after an MMC1 fault.

[0032] Figure 16 This is a schematic diagram showing the current of the bridge arm without current limitation before and after an MMC1 fault.

[0033] Figure 17 This diagram illustrates the application of this method to the arm currents before and after an MMC1 fault.

[0034] Figure 18 This is a schematic diagram showing the use of bridge arm current method A before and after an MMC1 fault.

[0035] Figure 19 This is a schematic diagram for noise impact analysis. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0037] Example 1, Figure 1 The present invention provides a hybrid current limiting control method for DC-side faults in a half-bridge modular multilevel converter, comprising the following steps: S1 continuously acquires the rate of change of DC voltage and DC current; S2, when the DC current is lower than the corresponding preset threshold and the DC current change rate exceeds the corresponding preset limit, a fault is determined to occur, and current limiting control is activated; S3 uses a dual-layer hybrid control method for current limiting control to suppress fault current.

[0038] S1 includes the following: S101, the continuous acquisition of DC voltage and DC current change rate includes a detection module, which employs a low-pass filter and voting logic to suppress transient noise.

[0039] Includes the following steps: The topology of a half-bridge modular multilevel converter is as follows: Figure 2 As shown, each phase consists of two bridge arms, upper and lower. Each bridge arm is composed of N sub-modules connected in series. Each sub-module includes a bridge arm inductor, a sub-module capacitor, and insulated-gate bipolar transistors VT1 and VT2. The sub-modules have three operating states: latched (both switches are off), engaged (VT1 is on, VT2 is off), and bypassed (VT1 is off, VT2 is on). During steady-state operation, the total number of engaged sub-modules in each phase remains at N to ensure a stable DC voltage output. ; In practical applications, measurement noise and signal transmission delay may introduce slight uncertainties to the detection of DC voltage and current derivatives. To enhance robustness, the detection module employs a low-pass filter and voting logic to suppress transient noise.

[0040] S2 includes the following: A schematic diagram of the current limiting combination control method is shown below. Figure 3 As shown, the system continuously monitors the DC voltage. and DC current change rate ,when Below the preset threshold and If the preset limit ξ is exceeded, a DC-side fault is determined, and current limiting control is activated. , Because the converter control cycle is short, the response time of this scheme is negligible. Since the DC fault current is mainly contributed by the converters near the fault, the current limiting control is only selectively applied to these converters to avoid unnecessary disturbance to the remote terminal.

[0041] S3 includes the following: S301, the dual-layer hybrid control method includes an outer-loop preset command current limiting and an adaptive current limiting based on DC voltage changes. Specifically, the outer-loop preset command current limiting restricts the active power injected from the AC side after a fault, reducing the transient peak values ​​of AC current and bridge arm current; the adaptive current limiting is based on DC voltage changes, and dynamically adjusts the number of connected sub-modules by constructing a correction coefficient to suppress fault current.

[0042] S302, the limitation of active power injected from the AC side includes introducing a command reset signal to clear the PI controller output once a fault is detected, so as to set the d-axis current component reference value to zero.

[0043] S303, the specific steps for constructing the correction coefficient are as follows: when a fault occurs, the instantaneous value of the DC voltage is divided by its steady-state value to obtain the relative voltage coefficient; the relative voltage coefficient is corrected to obtain the correction coefficient.

[0044] S304, the dual-layer hybrid control method includes coordinating with the DC circuit breaker to minimize fault current stress and breaking energy during DC circuit breaker operation.

[0045] The current limiting control includes an outer loop preset command current limiting and an adaptive current limiting based on DC voltage changes; The outer ring preset command rate limiting, the specific steps are as follows: The principle of outer loop command preset control is as follows: Figure 4 As shown, P ref For constant power input, U dcref With a constant voltage input, a DC-side fault could cause power and voltage oscillations that saturate the outer-loop proportional-integral controller, reducing its controllability. To prevent this, a reset signal is introduced. Once a fault is detected, the PI controller output is cleared, thus resetting the d-axis current component reference value. Set to zero; The MMC control structure including the proposed current limiting element is as follows: Figure 5 As shown in the figure, and These represent reactive power and its reference value, respectively. and Indicates the measured and reference values ​​of the AC terminal voltage. and These are the maximum and reference values ​​of the q-axis component of the AC current on the valve side of the converter, respectively, with symbols... Represents the system's angular frequency. and These are the d-axis and q-axis components of the AC voltage on the valve side, while and The d-axis and q-axis components of the differential voltage of the bridge arm are represented. Given a short control cycle (approximately 100 μs) for the converter, the inner loop current rapidly follows the updated reference value, thereby reducing the instantaneous active power exchange between the AC and DC sides. The active power at the converter port is expressed as: , Therefore, when When approaching zero, active power transmission Consequently, the amplitude of the AC phase current and the peak value of the bridge arm current decrease, as shown in the following formula: , , This represents the effective value of the AC terminal voltage of the converter. This refers to the reactive power component; Limiting through the outer ring reset mechanism The active power injected into the AC system by the converter decreases, and the AC current amplitude decreases. and The peak current of the bridge arms is effectively constrained. This mechanism serves as a fast, non-intrusive control measure to suppress transient overcurrents during DC faults.

[0046] The adaptive current limiting based on DC voltage changes involves the following steps: The number of sub-modules activated is dynamically adjusted based on changes in DC voltage, such as... Figure 6 As shown, when the fault occurs, the DC voltage A sharp drop, which will happen instantly Divide by its steady-state value Obtain the relative voltage coefficient Subtracting it from 1 gives the correction coefficient. This coefficient determines the proportion of submodules that remain in operation, and the DC voltage at the converter port is given by the following formula: , in The average capacitor voltage of the input submodule; Bipolar DC short-circuit fault is the most severe fault condition in a half-bridge MMC DC power grid. The equivalent fault circuit can be modeled as a second-order RLC network, such as... Figure 7 As shown, the equivalent parameter is defined as: , here, and These are the equivalent resistance and inductance of the three-phase converter bridge arms. , These are the resistance, inductance, and equivalent capacitance of a DC circuit. The total stored energy originating from the capacitors in the submodules; Due to the weak damping characteristics of DC systems This leads to an underdamped oscillating response. The fault current can therefore be expressed as: , , in, and These are the initial voltage and current values ​​at the moment the fault occurred; The first term of this expression plays a dominant role in the initial transient phase of a fault, reflecting the rapid rise of the fault current. By employing adaptive current limiting control, the converter uses a correction factor... The dynamic adjustment of the submodule input ratio reduces the initial DC voltage. At the same time, the equivalent capacitance was increased. This reduces the resonant frequency. Ultimately, the overall coefficient This reduces the peak fault current and effectively suppresses its rise rate. It should be noted that the analytical derivation simplifies by assuming uniform submodule capacitance and negligible control delay. In actual MMC systems, manufacturing tolerances typically result in submodule capacitance deviations of less than ±5%, which has a limited impact on the equivalent capacitance and resonant frequency. Furthermore, the converter's control cycle (100 μs in this study) is much smaller than the transient time constant of the DC fault current rise, ensuring that the delay does not significantly affect the dynamic response of the proposed control. Therefore, these assumptions are reasonable for equivalent circuit modeling and control mechanism analysis. As the fault evolves and Convergence occurs when the number of submodules in operation stabilizes at approximately half of what it would be under normal conditions, preventing excessive bypassing from affecting converter performance. This adaptive process ensures effective current suppression and partial fault ride-through capability.

[0047] Example 2: To verify the effectiveness of the proposed current limiting control method, a four-terminal half-bridge MMC DC grid model was established in the PSCAD / EMTDC platform, as follows: Figure 8 As shown, Includes the following steps: The system employs a master-slave control scheme: MMC4 operates in constant DC voltage control mode, while the remaining converter stations (MMC1, MMC2, and MMC3) operate in constant active power control mode. During normal operation, MMC1 and MMC3 act as rectifiers, injecting power into the DC grid, while MMC2 and MMC4 act as inverters, supplying power to the AC system. After reaching steady-state operation, a metallic bipolar DC short-circuit fault is applied at the output (location) of MMC1 at t=1.5s. Upon fault detection, the near-end converters MMC1 and MMC2 switch to the proposed current-limiting control method, while the far-end converters MMC3 and MMC4 maintain normal operation. The fault duration is set to 6ms, after which the fault is cleared, and the system returns to normal operation. 1) DC bus current analysis The dynamic behavior of the DC bus current at the MMC1 port before and after the fault is as follows: Figure 9 Dynamic behavior of DC bus current at MMC2 port before and after fault Figure 10 As shown, in contrast, Method A refers to the traditional technique of reducing the number of input sub-modules to a factor of km (where k is the reduction factor and m is the modulation ratio), with the reduction factor km=0.43 corresponding to the method proposed in previous literature based on simultaneously reducing the DC and AC components of the bridge arm voltage. Before the fault, the steady-state DC currents of MMC1 and MMC2 were 1.1488kA and -1.6309kA, respectively. Without any current limiting control, the DC currents rose rapidly after the fault, reaching 8.6kA and 2.24kA at 6ms. Using method A, the peak currents decreased to 4.89kA and 0.32kA, respectively, representing reductions of 49.9% and 49.6%. Using the proposed hybrid control method, the currents further decreased to 4.55kA and -0.34kA, representing reductions of 54.5% and 66.7%, respectively. These results indicate that both methods can effectively limit fault current, but the proposed method provides better suppression, especially for the converter closest to the fault. 2) Active power analysis The active power behavior of the AC system before and after the fault is as follows: Figure 11 As shown, compared with method A, the proposed method significantly reduces the active power injected from the AC side during the fault, alleviates power oscillation, and maintains steady-state transmission capability. For near-end converter stations (MMC1 and MMC2), the peak active power decreased from 875.68MW and -76.16MW to 733.02MW and -439.80MW, respectively. Based on their steady-state reference values ​​(600MW and -800MW), the reduction amounts are 51.7% and 50.2%, respectively, which verifies the analysis. The active power curves before and after the fault at each converter station are as follows: Figure 12 As shown, the near-end stations (MMC1 and MMC2) exhibited moderate power fluctuations after activating current limiting control, while the far-end stations (MMC3 and MMC4) maintained stable output. After the fault was cleared, the system power recovery time was almost the same regardless of whether current limiting control was applied, indicating that the proposed method does not affect the power recovery after the fault. 3) Valve-side AC current analysis The valve-side AC current of MMC1 under no current limiting conditions is as follows: Figure 13 As shown, the valve-side AC current of MMC1 under the conditions of using this method is as follows: Figure 14 As shown, under method A, the valve-side AC current of MMC1 is as follows: Figure 15 As shown, under unlimited current conditions, the AC current increases sharply after a fault, with positive and negative peak values ​​of 3.49kA and -2.76kA, respectively. Using method A, the number of sub-modules in operation for all converters is reduced to 0.43 times the original number. This lowers the arm voltage but increases the power injected from the AC side, resulting in higher AC current peak values ​​(4.78kA and -5.59kA). In contrast, using the proposed control method, the peak values ​​are reduced to 3.12kA and -3.77kA, representing reductions of 34.7% and 32.6%, respectively. This demonstrates that the proposed method successfully limits the increase in AC current caused by the reduction of submodule input, and maintains the overall balanced fault current response of the converter. 4) Bridge arm current analysis The bridge arm currents of MMC1 before and after the fault under conditions without current limiting are as follows: Figure 16 As shown, the arm currents of MMC1 before and after the fault under the conditions of using this method are as follows: Figure 17 As shown, the bridge arm currents of MMC1 before and after the fault under method A are as follows: Figure 18 As shown, under unlimited current conditions, the arm current rises rapidly, reaching 1.84 kA (positive) and 4.39 kA (negative). Since the arm current contains both DC and AC components, and the DC component dominates during faults, its transient behavior closely follows the DC fault current. When using method A, the peak values ​​increase slightly to 2.67 kA and -4.45 kA, which is due to the increased active power injected from the AC side. When using the proposed hybrid method, the corresponding peak values ​​decrease to 2.16 kA and -2.95 kA, representing reductions of 33.7% and 32.8% respectively compared to method A and the uncontrolled case. Therefore, the proposed control effectively alleviates the overcurrent stress on the power electronic devices of the converter and improves the system safety; 5) Noise verification To evaluate the robustness of the proposed control method, an additional parameter sensitivity study was conducted in PSCAD / EMTDC. Gaussian white noise with a standard deviation of 1% and 2% was injected into the current measurement channel to simulate sensor inaccuracies. The results are as follows: Figure 19 As shown in the figure, the peak DC fault current variation is less than 6%, and the damping ratio of the post-fault oscillation remains almost unchanged. These findings confirm that the proposed control still maintains effective current-limiting performance under moderate parameter deviations, control delays, and measurement disturbances.

[0048] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0049] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0050] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0051] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0052] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0053] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hybrid current limiting control method for half-bridge modular multilevel converter DC side fault, characterized in that, The method comprises the following steps: continuously acquiring DC voltage and DC current rate of change; when the DC current is lower than a corresponding preset threshold and the DC current rate of change exceeds a corresponding preset limit, determining that a fault occurs and activating current limiting control; based on a double-layer hybrid control method, performing current limiting control to achieve fault current suppression.

2. The hybrid current limiting control method of a half bridge modular multilevel converter DC side fault according to claim 1, characterized in that, The continuously acquiring DC voltage and DC current rate of change comprises a detection module that uses a low-pass filter and voting logic to suppress transient noise.

3. The hybrid current limiting control method of a half bridge modular multilevel converter DC side fault according to claim 2, characterized in that, The double-layer hybrid control method comprises outer loop preset instruction current limiting and adaptive current limiting based on DC voltage change, specifically: the outer loop preset instruction current limiting is to limit active power injected from the AC side after a fault to reduce transient peak values of AC current and bridge arm current; the adaptive current limiting is to dynamically adjust the number of input sub-modules based on DC voltage change by constructing a correction coefficient to suppress fault current.

4. The hybrid current limiting control method of a half bridge modular multilevel converter DC side fault according to claim 3, characterized in that, The limiting of active power injected from the AC side comprises introducing an instruction reset signal, and clearing the PI controller output upon detection of a fault to set the d-axis current component reference value to zero.

5. The hybrid current limiting control method of a half bridge modular multilevel converter DC side fault according to claim 4, characterized in that, The steps of constructing the correction coefficient are as follows: when a fault occurs, divide the DC voltage instantaneous value by the DC voltage steady-state value to obtain a relative voltage coefficient; correct the relative voltage coefficient to obtain the correction coefficient.

6. The hybrid current limiting control method of a half bridge modular multilevel converter DC side fault according to claim 5, characterized in that, The double-layer hybrid control method comprises coordination with a DC circuit breaker to minimize fault current stress and breaking energy during operation of the DC circuit breaker.

7. An electronic device, comprising: It comprises a processor and a storage medium. The storage medium is used to store instructions. The processor is used to operate according to the instructions to perform the steps of the method according to any one of claims 1-6.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the steps of the method according to any one of claims 1-6.

9. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instructions are executed by the processor to implement the steps of the method according to any one of claims 1-6.

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