Insulating medium capacitance detection structure and method

Abstract

The application relates to the technical field of integrated circuits, in particular to an insulating medium capacitor detection structure and method, which comprises a substrate, a common electrode formed on the substrate and a capacitor to be detected, the capacitor to be detected is located in the common electrode of the enclosed structure, and the capacitor to be detected comprises a laminated polar plate one, an insulating medium layer to be detected and a polar plate two; the polar plate one is laterally extended at the edge to form a first lead-out part corresponding to the contact of a first signal pin of a GSG probe; the polar plate two is laterally extended at the edge to form a second lead-out part corresponding to the contact of a second signal pin of the GSG probe; and the common electrode is formed with a third lead-out part corresponding to the contact of a ground pin of the GSG probe. The application can guarantee the accuracy of capacitor measurement and realize the capacitor value measurement of the insulating medium capacitor detection structure with small size and low order of magnitude.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to an insulating medium capacitor detection structure and method. BACKGROUND

[0002] In the continuous evolution of integrated circuit technology, nanowire wide logic circuits exhibit lower capacitance values due to their own characteristics. To meet the performance requirements of the circuit, a larger capacitance value is often obtained through multi-layer parallel connection to reduce the adverse effects of system parasitic capacitance on circuit performance.

[0003] In the application scenario of MIM (Metal-Insulator-Metal) multi-layer parallel capacitor test structure, the spacing between the multi-layer plate electrodes is very small. Under the interference of manufacturing process deviation, environmental stress and other factors, short circuit phenomenon is prone to occur. Once a short circuit occurs, the capacitance value obtained by testing is actually the capacitance of the short-circuit metal electrode, rather than the true capacitance value of the insulating medium, which will cause the test results to be seriously inconsistent with the actual situation, greatly affecting the performance evaluation and optimization design of integrated circuits. SUMMARY

[0004] The purpose of the present application is to provide an insulating medium capacitor detection structure and method which can ensure the accuracy of capacitance measurement and realize the capacitance value measurement of small-size, low-order insulating medium capacitor detection structure.

[0005] To achieve the above purpose, the technical solution adopted by the present application is as follows:

[0006] In a first aspect, the present application provides an insulating medium capacitor detection structure, comprising a substrate, a common ground electrode formed on the substrate and a to-be-measured capacitor, the to-be-measured capacitor being located in the common ground electrode of the enclosed structure, the to-be-measured capacitor comprising a plate one, a to-be-measured insulating medium layer and a plate two stacked together; the edge of the plate one extends laterally to form a first lead-out part corresponding to the contact of the first signal pin of the GSG probe; the edge of the plate two extends laterally to form a second lead-out part corresponding to the contact of the second signal pin of the GSG probe; the common ground electrode is formed with a third lead-out part corresponding to the contact of the ground pin of the GSG probe.

[0007] Further, the top surface of the first lead-out part is in contact with the first signal pin, the top surface of the second lead-out part is in contact with the second signal pin, the top surface of the third lead-out part is in contact with the ground pin, and the top surface of the first lead-out part, the top surface of the second lead-out part and the top surface of the third lead-out part are located on the same plane.

[0008] Further, the first lead-out portion is formed in a first direction, and the second lead-out portion is formed in a second direction; the third lead-out portion is four in number, two of which are formed in the first direction and the first lead-out portion is located in the middle of the two third lead-out portions, and the other two of which are formed in the second direction and the second lead-out portion is located in the middle of the two third lead-out portions; and the first direction and the second direction are opposite.

[0009] Further, the common ground electrode is in a rectangular frame structure, and the four third lead-out portions are respectively located at the four corners of the rectangular frame.

[0010] Further, the common ground electrode is made of aluminum, aluminum alloy, copper, tungsten, molybdenum or a first composite layer; the material of the first and second electrode plates is independently aluminum, aluminum alloy, copper, tungsten, molybdenum, tantalum or a second composite layer; the first composite layer comprises a first barrier layer and a first conductive layer arranged in a stack, and the first barrier layer is arranged close to the substrate; the material of the first barrier layer is titanium nitride, and the material of the first conductive layer is copper; or, the material of the first barrier layer is tungsten, and the material of the first conductive layer is aluminum; the second composite layer comprises a second barrier layer and a second conductive layer arranged in a stack, and the second barrier layer is arranged close to the to-be-measured insulating medium layer; the material of the second barrier layer is at least one of titanium and titanium nitride, and the material of the second conductive layer is copper or aluminum.

[0011] In a second aspect, the present application discloses a method for detecting the capacitance of an insulating medium, which comprises:

[0012] The above-mentioned insulating medium capacitance detection structure is connected with a vector network analyzer, the first lead-out portion of the first electrode plate is in corresponding contact with a first signal pin of a GSG probe, the second lead-out portion of the second electrode plate is in corresponding contact with a second signal pin of the GSG probe, and the third lead-out portion of the common ground electrode is in corresponding contact with a ground pin of the GSG probe; the first signal pin and the second signal pin of the GSG probe are connected with a port 1 and a port 2 of the vector network analyzer respectively, and the ground pin of the GSG probe is connected with a ground port of the vector network analyzer.

[0013] A high-frequency test signal of 100MHz-10GHz is applied from the port 1 or the port 2 of the vector network analyzer to obtain a scattering parameter amplitude matrix;

[0014] The scattering parameter amplitude matrix is converted into an admittance parameter matrix through matrix operation;

[0015] The capacitance value is calculated based on the imaginary part of the admittance parameter.

[0016] Further, the scattering parameter amplitude matrix S is ;

[0017] S11 is a reflection coefficient of port one, i.e. a ratio of a reflected wave amplitude at port one to an incident wave amplitude when a test signal is input from port one, and represents a reflection characteristic of port one;

[0018] S12 is a transmission coefficient from port one to port two, i.e. a ratio of a transmitted wave amplitude at port two to an incident wave amplitude at port one when a test signal is input from port one, and represents a transmission characteristic from port one to port two;

[0019] S21 is a transmission coefficient from port two to port one, i.e. a ratio of a transmitted wave amplitude at port one to an incident wave amplitude at port two when a test signal is input from port two, and represents a transmission characteristic from port two to port one;

[0020] S22 is a reflection coefficient of port two, i.e. a ratio of a reflected wave amplitude at port two to an incident wave amplitude when a test signal is input from port two, and represents a reflection characteristic of port two.

[0021] Further, a conversion formula for converting the scattering parameter amplitude matrix into a admittance parameter matrix through matrix operation is: ; in the formula, Y is the admittance parameter matrix, S is the scattering parameter amplitude matrix, I is the unit matrix, and Z0 is the standard impedance;

[0022] The calculation formula of the capacitance value is: ; in the formula, C is the calculated capacitance value, f is the frequency of the test signal, Im(Y11) is the imaginary part of the admittance parameter Y11, and the admittance parameter Y11 is the input admittance of port one when port two is short-circuited.

[0023] Further, the method further comprises: performing normalization processing on the capacitance value based on a capacitance area, and the calculation formula is , C is the calculated capacitance value before the normalization processing, C norm is the capacitance value after the normalization processing, A is the capacitance area, i.e. the effective area of the insulating dielectric layer covered by the first electrode plate or the second electrode plate.

[0024] Further, the method further comprises: performing SOLT calibration on the GSG probe before the insulating dielectric capacitance detection structure is connected with the vector network analyzer.

[0025] The unexpected beneficial effects of the present application are as follows:

[0026] The common-ground electrode of this invention encloses the capacitor under test, and its third lead, formed by lateral extension, contacts the grounding pin of the GSG probe, forming a grounding reference plane. This shields against external electromagnetic interference, reduces signal fluctuations, and significantly improves the measurement signal-to-noise ratio. The enclosed structure of the common-ground electrode suppresses parasitic inductance and electromagnetic coupling interference, avoids signal crosstalk and jumps at high frequencies, ensures signal stability, optimizes high-frequency signal transmission, reduces transmission line loss and signal reflection, ensures accurate measurement of scattering parameters, and provides a reliable basis for capacitance calculation. This allows for the precise capture of weak phase changes in small capacitors below the picofarad level at high frequencies, solving the problem of insufficient accuracy in traditional quasi-static testing of small capacitors. Attached Figure Description

[0027] Figure 1 A schematic diagram of the insulating dielectric capacitance detection structure according to an embodiment of the present invention is shown.

[0028] Figure 2 It shows Figure 1 A schematic diagram of the AA section.

[0029] Figure 3 A schematic diagram of the structure after a common ground electrode is formed on the substrate is shown.

[0030] Figure 4 It shows Figure 3 A schematic diagram of the BB cross section.

[0031] Figure 5 A schematic diagram of the structure after the formation of electrode one is shown.

[0032] Figure 6 It shows Figure 5 A schematic diagram of the CC section.

[0033] Figure 7 A schematic diagram of the structure after the insulating dielectric layer to be tested is shown.

[0034] Figure 8 It shows Figure 7 Schematic diagram of the DD cross section.

[0035] Figure 9 A schematic flowchart of the dielectric capacitance detection method according to an embodiment of the present invention is shown.

[0036] In the figure, 1—substrate, 2—common ground electrode, 21—third lead-out, 3—plate one, 31—first lead-out, 32—first connection, 4—insulating dielectric layer to be tested, 5—plate two, 51—second lead-out, 52—second connection. Detailed Implementation

[0037] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0038] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] In this invention, it should be noted that terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, terms such as "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0040] In one embodiment, see Figure 1 and Figure 2 As shown, the present invention provides an insulating dielectric capacitance detection structure, including a substrate 1, a common ground electrode 2 formed on the substrate 1, and a capacitor under test. The capacitor under test is located within the common ground electrode 2 of the enclosing structure. The capacitor under test includes a first electrode plate 3, a test insulating dielectric layer 4, and a second electrode plate 5 formed by stacking. The edge of the first electrode plate 3 extends laterally to form a first lead-out portion 31 that contacts the first signal pin of the GSG probe. The edge of the second electrode plate 5 extends laterally to form a second lead-out portion 51 that contacts the second signal pin of the GSG probe. A third lead-out portion 21 that contacts the ground pin of the GSG probe is formed on the common ground electrode 2.

[0041] In this embodiment, the common ground electrode 2 surrounds the capacitor under test, and the common ground electrode 2 is directly connected to the grounding pin of the GSG probe, which is equivalent to building an electromagnetic protection barrier around the capacitor under test. Simultaneously, the common ground electrode 2 and the grounding pin of the GSG probe form a stable grounding reference plane, keeping the capacitor under test surrounded by a grounded environment. Therefore, electromagnetic noise from the external environment (such as spatial electromagnetic fields and equipment interference signals) is difficult to penetrate the enclosed grounding barrier and cannot interfere with the plate signals of the capacitor under test. Furthermore, the grounding reference plane can quickly absorb stray signals around the capacitor under test, preventing them from mixing into the detection signals of plate 3 and plate 5. This significantly improves the ratio of effective signal to noise during measurement, reduces signal fluctuations, and lays the foundation for subsequent accurate measurements.

[0042] Parasitic inductance is one of the core interference sources in high-frequency testing. Traditional small-area grounding structures are prone to generating parasitic inductance due to unstable current paths. The common ground electrode of this invention, as a large-area grounding plane, can significantly reduce parasitic inductance in the test circuit by increasing the conductor cross-sectional area and optimizing current distribution, thus avoiding additional disturbances to the phase and amplitude of high-frequency signals. At high frequencies, signal crosstalk between different electrodes and leads can severely distort the detection signal. The large-area common ground electrode provides a low-impedance unified grounding reference, directing stray coupled signals from each electrode to the ground terminal, cutting off crosstalk paths, and ensuring that the signal from the capacitor under test is independent and pure.

[0043] If the grounding reference is incomplete during the transmission of high-frequency signals, it will lead to impedance mismatch of the transmission line, resulting in signal reflection and transmission loss. The common ground electrode of this invention can provide a uniform, low-impedance grounding reference for signal transmission, accurately match the characteristic impedance of the transmission line of the GSG probe, and ultimately make the measurement results of the S-parameter, i.e. the scattering parameter, closer to the true characteristics of the capacitor, providing a reliable data basis for subsequent capacitance value calculation.

[0044] Microcapacitors below the picofarad level (e.g., fF level) have extremely small capacitance values, resulting in very weak electrical signals (especially phase changes at high frequencies). Traditional quasi-static testing lacks effective anti-interference design, causing these weak phase signals to be masked by noise, making accurate capture impossible and leading to significant measurement errors. This invention, through electromagnetic interference shielding, parasitic / coupling suppression, and precise S-parameter measurement, enables the clear and accurate capture of the weak phase changes of microcapacitors at high frequencies. Combined with a precise S-parameter calculation model, the accurate values ​​of microcapacitors below the picofarad level can be derived in reverse, completely solving the problem of inaccurate measurement of microcapacitors in traditional quasi-static testing.

[0045] In the dielectric capacitance detection structure of the present invention, the edges of the first electrode 3, the second electrode 5, and the common ground electrode 2 extend laterally to form a first lead-out portion 31, a second lead-out portion 51, and a third lead-out portion 21, which correspond to the signal pin and ground pin of the GSG probe, respectively. This transfers the probe contact point from the main body area of ​​the electrode to the edge, avoiding damage to the electrode-dielectric interface caused by probe pressure, and reducing the impact of the contact area on the effective area of ​​the capacitor.

[0046] The stacked arrangement of the first electrode 3, the insulating dielectric layer 4, and the second electrode 5 of the capacitor under test in this invention concentrates the electric field in the dielectric region under test, reducing capacitance deviation caused by edge effects.

[0047] For example, the insulating dielectric layer 4 to be tested includes SiCN (silicon carbide nitrogen), TEOS (tetraethyl orthosilicate), ELK (ultra-low k material, referring to a material with extremely low dielectric constant, typically k value < 3), SICO (silicon carbon oxide) stack or any combination of several layers.

[0048] As a preferred embodiment of the present invention, see Figure 2 As shown, the top surface of the first lead-out portion 31 is in contact with the first signal pin, the top surface of the second lead-out portion 51 is in contact with the second signal pin, and the top surface of the third lead-out portion 21 is in contact with the ground pin. The top surfaces of the first lead-out portion 31, the second lead-out portion 51, and the third lead-out portion 21 are located on the same plane.

[0049] In this preferred embodiment, when the top surfaces of the first lead-out portion 31, the second lead-out portion 51, and the third lead-out portion 21 are located on the same plane, the first signal pin, the second signal pin, and the ground pin of the GSG probe can simultaneously contact the corresponding lead-out portions, avoiding uneven contact pressure caused by height differences. Furthermore, the coplanar design improves the consistency of the overlap area between the pins and the lead-out portions, reducing capacitance measurement errors.

[0050] Furthermore, the contact points of the leads within the same plane ensure that the difference in transmission path length between the signal pin and the ground pin is within a preset range, matching the differential measurement requirements of a two-port network. Compared to a non-coplanar design, this improves the phase measurement accuracy of scattering parameters, ensuring that phase changes of small capacitors can be accurately captured. Simultaneously, the coplanar structure ensures a uniform impedance distribution on the lead surface, avoiding impedance discontinuities caused by height abrupt changes and reducing interference from energy reflection on the measurement signal.

[0051] As a preferred embodiment of the present invention, see Figure 1As shown, the first lead-out portion 31 extends along a first direction, and the second lead-out portion 51 extends along a second direction; there are four third lead-out portions 21, of which two third lead-out portions 21 extend along the first direction and the first lead-out portion 31 is located in the middle of the two third lead-out portions 21, and the other two third lead-out portions 21 extend along the second direction and the second lead-out portion 51 is located in the middle of the two third lead-out portions 21; the first direction and the second direction are opposite.

[0052] In this preferred embodiment, the first lead-out portion 31 is located between two third leads-out portions 21 in the same direction, forming a symmetrical "G (Ground)-S (Single)-G (Ground)" structure, precisely matching the three-pin layout of the GSG probe, i.e., grounded on both sides and signaled in the middle. This arrangement ensures that the spacing between the signal pins and the ground pins is consistent, forming an equivalent coaxial transmission line and reducing crosstalk and phase deviation in signal transmission. The second lead-out portion 51 extending in the opposite direction forms a symmetrical two-port network structure with the two corresponding grounded third leads 21, ensuring the symmetry of the signal paths at both ports, matching the differential measurement mode of the two-port network analyzer, and suppressing common-mode noise interference.

[0053] The grounding leads extending in the same direction form a wrap-around shield around the signal leads, ensuring a symmetrical distribution of parasitic capacitance and inductance between the signal leads and the grounding leads. For example, the parasitic capacitances of the third leads 21 on both sides of the first lead 31 cancel each other out, avoiding signal distortion caused by asymmetric parasitic parameters and ensuring phase consistency of scattering parameter measurements at high frequencies.

[0054] Further, see Figure 1 As shown, the common ground electrode 2 has a rectangular frame structure, with four third leads 21 located at the four corners of the rectangular frame. This configuration serves two purposes: firstly, multi-point grounding further reduces the parasitic inductance of the grounding loop. Single-point grounding is prone to parasitic inductance due to long current paths, while multi-point grounding shortens the current path, effectively suppressing parasitic parameter interference, especially at high frequencies; secondly, the uniform distribution of the four points makes the grounding potential of the entire common ground frame more uniform, avoiding stray electric fields caused by local potential differences, providing a more stable grounding reference for the capacitor under test, and indirectly improving the phase capture accuracy of small capacitor measurements.

[0055] The width of the third lead-out portion 21 is greater than the width of the rectangular frame side beam of the common ground electrode 2. This configuration serves two purposes: first, it increases the contact area with the grounding pin of the GSG probe, reducing the contact resistance between the GSG probe and the third lead-out portion, thus avoiding grounding failure or signal loss due to excessive contact resistance. Especially in high-frequency testing, low contact resistance can reduce additional signal transmission losses. Second, it ensures that the first lead-out portion 31 and the second lead-out portion 51 can be located in the middle position of the two third lead-out portions 21.

[0056] For example, the fabrication method of the insulating dielectric capacitance detection structure includes: first, a common ground electrode 2 is fabricated on an insulating wafer substrate 1 by a metal stripping process or Cu ECP and CMP processes, and an electrode plate 3 can be fabricated simultaneously; second, an insulating dielectric layer 4 to be tested is deposited by a CVD process; and third, an electrode plate 5 is fabricated by a metal stripping process or Cu ECP and CMP processes.

[0057] Specifically, it includes the following steps:

[0058] Substrate 1 is provided.

[0059] Photoresist is coated on substrate 1, exposed, and developed to obtain the patterned window of common ground electrode 2.

[0060] A common ground electrode 2 is formed by deposition or electroplating on substrate 1, and then polished to a predetermined height using a chemical polishing process, followed by removal of the photoresist. (See also...) Figure 3 and Figure 4 As shown, the common electrode 2 formed by deposition has a rectangular frame structure, with four third leads 21 located at the four corners of the rectangular frame, and the width of the third leads 21 is greater than the width of the side beams of the common electrode 2.

[0061] Photoresist is coated on substrate 1, exposed, and developed to obtain the patterned window of electrode 3.

[0062] Electrode 3 is deposited on substrate 1 and polished to a predetermined height using a chemical polishing process, followed by removal of the photoresist. (See also...) Figure 5 and Figure 6 As shown, the electrode 3 includes a main body and a laterally extending first lead-out portion 31, which is connected to the main body via a first connecting portion 32. It should be noted that the electrode 3 can also be deposited and formed in one step with the common ground electrode 2, i.e., through exposure and development, patterned windows of the common ground electrode 2 and the electrode 3 are formed simultaneously.

[0063] Photoresist is coated on substrate 1, exposed, and developed to obtain a patterned window of the insulating dielectric layer 4 under test. The patterned window of the insulating dielectric layer 4 under test is located above electrode 3. See also Figure 7 and Figure 8 As shown, an insulating dielectric layer 4 to be tested is then deposited on the electrode 3, and the photoresist is removed.

[0064] Photoresist is coated on substrate 1, exposed, and developed to obtain a patterned window for electrode 2 5, which is located above the insulating dielectric layer 4 to be tested. Then, electrode 2 5 is deposited on the insulating dielectric layer 4 to be tested, and the photoresist is removed to obtain the insulating dielectric capacitance detection structure of the present invention. See also...Figure 1 and Figure 2 As shown, the second electrode plate 5 includes a second main body and a second lead-out portion 51 extending laterally. The second lead-out portion 51 is connected to the second main body via a second connecting portion 52.

[0065] Furthermore, the dielectric capacitance detection structure can be of any structure and size.

[0066] For example, see Figure 1 and Figure 2 As shown, the cross-sections of electrode 3, the insulating dielectric layer 4, and electrode 5 are all rectangular. Alternatively, the cross-sections of electrode 3, the insulating dielectric layer 4, and electrode 5 are all circular.

[0067] In a preferred embodiment of the present invention, the common ground electrode 2 is made of aluminum, aluminum alloy, copper, tungsten, molybdenum or a first composite layer; the first composite layer includes a first barrier layer and a first conductive layer stacked together, the first barrier layer being disposed close to the substrate 1; the first barrier layer is made of titanium nitride and the first conductive layer is made of copper; or, the first barrier layer is made of tungsten and the first conductive layer is made of aluminum.

[0068] In this preferred embodiment, copper and aluminum provide a low-impedance grounding path to reduce signal loss at high frequencies. Copper is suitable for high-performance processes, while aluminum has the advantage of process maturity in low-power applications. High-melting-point metals (tungsten, molybdenum) can maintain structural stability in high-temperature processes.

[0069] Titanium nitride is used as the first barrier layer to form a dense physical barrier, which inhibits metal diffusion and enhances the interfacial adhesion with substrate 1, reducing the risk of interlayer delamination during thermal cycling.

[0070] Using tungsten and aluminum as the first composite layer, the stress concentration caused by thermal expansion is alleviated by modulus gradient, thereby improving the device's resistance to thermal fatigue.

[0071] In a preferred embodiment of the present invention, the materials of the first electrode 3 and the second electrode 5 are independently aluminum, aluminum alloy, copper, tungsten, molybdenum, tantalum or a second composite layer; the second composite layer includes a second barrier layer and a second conductive layer stacked together, the second barrier layer being arranged close to the insulating dielectric layer 4 to be tested; the material of the second barrier layer is at least one of titanium and titanium nitride, and the material of the second conductive layer is copper or aluminum.

[0072] In this preferred embodiment, aluminum and aluminum alloys have good electrical conductivity and process maturity, and can be deposited by PECVD (plasma-enhanced chemical vapor deposition) or sputtering processes.

[0073] Copper has a lower resistivity than aluminum, which reduces RC delay and improves the efficiency of high-frequency signal transmission. RC delay is a signal propagation obstruction phenomenon caused by the charging and discharging effects of resistors and capacitors.

[0074] Tungsten, molybdenum, and tantalum are high-melting-point metals that are resistant to high temperatures and are suitable for high-k dielectric integration that requires high-temperature annealing processes, thus avoiding the diffusion and agglomeration of metals at high temperatures.

[0075] Titanium and titanium nitride serve as a second barrier layer, providing physical isolation. The dense Ti or TiN layer prevents copper atom diffusion, reducing leakage current in the test insulating dielectric layer 4. Furthermore, Ti or TiN forms strong chemical bonds with the test insulating dielectric layer 4, enhancing interfacial adhesion and reducing the risk of interlayer delamination due to thermal stress. Simultaneously, the Ti or TiN barrier layer forms a modulus gradient with the copper / aluminum conductive layer, mitigating stress concentration caused by thermal expansion coefficient mismatch. By adjusting the Ti / TiN thickness, the interfacial stress is kept within a preset range, improving device reliability.

[0076] A second conductive layer of copper or aluminum provides a low-impedance path for signal transmission.

[0077] In one embodiment, the present invention discloses a method for detecting the capacitance of an insulating dielectric, see [link to relevant documentation]. Figure 9 As shown, the method includes the following steps:

[0078] Step 1: Connect the dielectric capacitance detection structure described in any of the above embodiments to the vector network analyzer. The first lead 31 of electrode 3 of the dielectric capacitance detection structure contacts the first signal pin of the GSG probe, the second lead 51 of electrode 5 contacts the second signal pin of the GSG probe, and the third lead 21 of the common ground electrode 2 contacts the ground pin of the GSG probe. The first and second signal pins of the GSG probe are connected to port 1 and port 2 of the vector network analyzer, respectively, and the ground pin of the GSG probe is connected to the ground port of the vector network analyzer.

[0079] Step 2: Apply a high-frequency test signal from port 1 or port 2 of the vector network analyzer to obtain the scattering parameter amplitude matrix; the frequency of the high-frequency test signal is 100MHz~10GHz.

[0080] Step 3: Convert the scattering parameter amplitude matrix into an admittance parameter matrix through matrix operations.

[0081] Step four: Calculate the capacitance value based on the imaginary part of the admittance parameter.

[0082] In this embodiment, a high-frequency test signal of 100MHz to 10GHz is used, covering the typical operating frequency band in integrated circuits. This can capture the changes in capacitance characteristics of the insulating medium under actual operating conditions, avoiding measurement errors caused by the sensitivity of low-frequency tests to parasitic parameters. Furthermore, the high-frequency signal can excite the polarization effect in the insulating medium, reflecting the intrinsic dielectric properties of the material, and is particularly suitable for the accurate characterization of high-k dielectric materials.

[0083] The GSG (Ground-Signal-Ground) probe structure creates a coaxial signal transmission path, effectively shielding against external electromagnetic interference. The ground pin provides a low-impedance return path, reducing signal reflection and radiation loss. The corresponding contact design between the GSG probe and the first lead-out section 31, the second lead-out section 51, and the third lead-out section 21 ensures the shortest and most symmetrical signal path, reducing parasitic inductance and capacitance, and improving the transmission efficiency of high-frequency signals.

[0084] In step three, the scattering parameter amplitude matrix S is converted into admittance parameters through matrix operations, directly relating it to the current-voltage relationship. This separates the capacitance (imaginary part) and conductivity (real part) of the insulating medium, facilitating accurate extraction of the capacitance value. Admittance parameters are more sensitive to capacitance changes than scattering parameters, significantly improving resolution, especially in small capacitance measurements.

[0085] The imaginary part of the admittance parameter directly corresponds to the capacitive reactance characteristics of the insulating medium, eliminating interference from conductivity loss and reducing measurement deviations caused by leakage current or dielectric loss. It is suitable for capacitance measurement of high-resistivity insulating materials.

[0086] The low impedance characteristics of the common ground electrode 2, combined with the grounding pin of the GSG probe, form a unified grounding reference plane, reducing ground bounce noise and common-mode interference, and improving the stability of the measurement system. The symmetrical layout of the four third leads 21 matches the three-pin structure of the GSG probe, enabling the test signal to form a uniform electric field distribution between the plates, reducing edge effects and improving the accuracy of capacitance measurement.

[0087] In a preferred embodiment of the present invention, the scattering parameter amplitude matrix S is: ;

[0088] S11 is the reflection coefficient of port one, which is the ratio of the amplitude of the reflected wave to the amplitude of the incident wave when the test signal is input from port one, and characterizes the reflection characteristics of port one.

[0089] S12 is the transmission coefficient from port one to port two, which is the ratio of the amplitude of the transmitted wave at port two to the amplitude of the incident wave at port one when the test signal is input from port one, and characterizes the transmission characteristics from port one to port two.

[0090] S21 is the transmission coefficient from port 2 to port 1, which is the ratio of the amplitude of the transmitted wave at port 1 to the amplitude of the incident wave at port 2 when the test signal is input from port 2, and characterizes the transmission characteristics from port 2 to port 1.

[0091] S22 is the reflection coefficient of port two, which is the ratio of the amplitude of the reflected wave to the amplitude of the incident wave when the test signal is input from port two, and characterizes the reflection characteristics of port two.

[0092] In this preferred embodiment, the scattering parameter amplitude matrix encompasses the port reflection (S11, S22) and transmission (S12, S21) characteristics, comprehensively reflecting the signal interaction patterns of the insulating dielectric capacitance detection structure and providing multi-dimensional basis for accurate analysis. Each parameter corresponds to a port characteristic, enabling rapid identification of signal reflection and transmission anomalies, assisting in troubleshooting detection system faults or insulating dielectric defects, and improving problem diagnosis efficiency.

[0093] Furthermore, the scattering parameter is a voltage ratio, and when converting to dB, it needs to be taken as 20log|S|, where |S| is the amplitude of S.

[0094] dB (decibel) is a logarithmic unit used to represent the relative ratio of physical quantities. Its core function is to transform multiplication and division relationships into addition and subtraction relationships, making very large or very small values ​​easier to understand, calculate and compare, while also meeting the analytical needs of "relative change" in engineering.

[0095] Specifically, the scattering parameter itself is a voltage ratio. For example, S11 is the voltage ratio of the reflected wave to the incident wave. However, directly looking at the value of the voltage ratio, such as S11=0.01 or S11=100, does not provide an intuitive understanding of the signal attenuation and gain.

[0096] After converting 20log|S| to dB: If |S|=1, then 20log(1)=0dB, indicating that the signal has no attenuation / gain and no reflection, i.e., it is in an ideal matching state. If |S|<1, for example: S11=0.1, then 20log(0.1)=-20dB, the negative number indicates signal attenuation and reflection, the smaller the value, the more severe the attenuation or reflection. If |S|>1, for example: S21=2, then 20log(2)≈6dB, the positive number indicates signal gain.

[0097] In a preferred embodiment of the present invention, the transformation formula for converting the scattering parameter magnitude matrix into the admittance parameter matrix through matrix operations is as follows: In the formula, Y is the admittance parameter matrix, S is the scattering parameter magnitude matrix, I is the identity matrix, and Z0 is the standard impedance.

[0098] The formula for calculating capacitance is: In the formula, CTo calculate the capacitance value, f Let Y be the frequency of the test signal, and Im(Y11) be the imaginary part of the admittance parameter Y11. The admittance parameter Y11 is the input admittance of port one when port two is short-circuited.

[0099] In existing technologies, parasitic resistance, inductance, and capacitance parameters need to be extracted using complex models (such as π-type equivalent circuits). This invention eliminates the plate-to-ground parasitic capacitance by using a common ground electrode 2; and reduces contact resistance and lead inductance through the design of the first lead-out portion 31, the second lead-out portion 51, and the third lead-out portion 21. Furthermore, since the common ground electrode 2 shields against external interference and fixes the reference potential, the scattering parameters (S-parameters) measured by the two-port network can be directly converted into admittance parameters (Y-parameters). Calculating capacitance values ​​does not require parameter deduction through multi-frequency fitting or equivalent circuits, avoiding errors caused by modeling assumptions. It is especially suitable for rapid detection of capacitances below the picofarad level in nanometer linewidth circuits.

[0100] In a preferred embodiment of the present invention, the capacitance value is normalized based on the capacitance area, and the calculation formula is as follows: , C The capacitance value is the value calculated before normalization. C norm The capacitance value is the normalized value. A The capacitance area is the effective area of ​​the insulating dielectric layer covering either electrode one or electrode two.

[0101] This preferred embodiment normalizes the capacitance value, unifies the evaluation standard, and provides standardized evaluation indicators for insulating dielectric capacitors of different sizes and structures. It supports multiple applications such as production line yield analysis and material research and development, and improves the universality and comparability of data.

[0102] Furthermore, normalization eliminates area dependence and focuses on the essence of the insulating medium under test. Traditional capacitance values ​​are directly affected by the plate area. After normalization, the result is strongly correlated only with the dielectric properties of the insulating medium, allowing for accurate comparison of dielectric performance under different sizes and structures, and avoiding interference with material or process evaluation due to design differences.

[0103] As a preferred embodiment of the present invention, it further includes: performing SOLT calibration on the GSG probe before connecting the insulating dielectric capacitance detection structure to the vector network analyzer.

[0104] The SOLT calibration of this preferred embodiment can eliminate systematic errors such as probe contact impedance, test cable loss, and fixture parasitic parameters, so that the measurement results only reflect the true capacitance characteristics of the insulating medium under test.

[0105] The specific steps for SOLT calibration include:

[0106] 1) Device connection: Connect the first signal pin and the second signal pin of the GSG probe to port one and port two of the vector network analyzer, respectively, and connect the ground pin to the ground port of the analyzer.

[0107] 2) Open-circuit calibration: Place the GSG probe in contact with an open-circuit standard (ideal open circuit, infinite impedance) and record the scattering parameters of the two-port network at this time. This is used to calibrate the parasitic parallel capacitance in the system and establish a zero-charge reference state.

[0108] 3) Short-circuit calibration: Place the GSG probe in contact with a short-circuit standard (ideal short circuit, impedance 0) and record the scattering parameters. This is used to calibrate parasitic series inductance and contact resistance in the system, eliminating impedance deviations in the low-frequency range.

[0109] 4) Load calibration: Contact the GSG probe with a 50Ω standard load (matching the network characteristic impedance) and record the scattering parameters to compensate for transmission loss in the system and ensure energy matching of the signal in the transmission path.

[0110] 5) Straight-through calibration: The GSG probe is brought into contact with a straight-through standard, i.e., the two ports are directly connected. The scattering parameters are recorded to calibrate the phase delay and amplitude attenuation between the ports and establish a reference model for two-port transmission.

[0111] 6) Calibration data processing: Using the built-in algorithm of the vector network analyzer, the scattering parameters of the above standard parts are substituted into the calibration matrix to automatically cancel the parasitic parameters of the system.

[0112] 7) Calibration and verification: Verify using a standard MIM capacitor with a known capacitance value to ensure that the measurement error is within the preset range.

[0113] The following will illustrate this with specific examples.

[0114] For example, a method for detecting the capacitance of an insulating dielectric includes the following steps:

[0115] The test circuit is connected to the insulating dielectric capacitance detection structure and the vector network analyzer. The first lead 31 of electrode 3 is in contact with the first signal pin of the GSG probe, the second lead 51 of electrode 5 is in contact with the second signal pin of the GSG probe, and the third lead 21 of the common ground electrode 2 is in contact with the ground pin of the GSG probe. The first and second signal pins of the GSG probe are connected to port 1 (input port) and port 2 (output port) of the vector network analyzer, respectively. The ground pin of the GSG probe is connected to the ground port of the vector network analyzer. The input port of the vector network analyzer is connected to the first bias tee, through which a bias voltage is applied to the input terminal. The output port of the vector network analyzer is connected to the second bias tee, through which a bias voltage is applied to the output terminal.

[0116] Set the common ground electrode frequency range to 100M-10GHz, set the intermediate frequency bandwidth to 100Hz, set 100 sweep points, set the RF signal power to 8dBm, and perform open circuit, short circuit, load, and through-circuit calibration on the probe ends on the same calibration plane to remove parasitic capacitance and inductance of cables and probes.

[0117] Obtain small-signal test parameters, set a -5V DC bias, test the two-port scattering parameters of the insulating dielectric detection structure, and obtain the scattering parameter amplitude matrix. .

[0118] The scattering parameters S11 obtained from the test will be converted into Y parameters. The standard impedance Z0 is 50Ω.

[0119] Furthermore, through The capacitance value is calculated and then normalized based on the capacitance area. The calculation formula is as follows: , C The capacitance value is the value calculated before normalization. C norm The capacitance value is the normalized value, in pF / cm. 2 , A The capacitance area is the effective area of ​​the insulating dielectric layer covering either electrode one or electrode two.

[0120] The common ground electrode 2 of this invention encloses the capacitor under test, and its third lead 21, formed by lateral extension, contacts the grounding pin of the GSG probe, forming a grounding reference plane. This shields against external electromagnetic interference, reduces signal fluctuations, and significantly improves the measurement signal-to-noise ratio. The enclosed structure of the common ground electrode 2 suppresses parasitic inductance and electromagnetic coupling interference, avoids signal crosstalk and jumps at high frequencies, ensures signal stability, optimizes high-frequency signal transmission, reduces transmission line loss and signal reflection, ensures accurate measurement of scattering parameters, and provides a reliable basis for capacitance calculation. This allows for the accurate capture of weak phase changes in small capacitors below the picofarad level at high frequencies, solving the problem of insufficient accuracy in traditional quasi-static testing of small capacitors.

[0121] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. An insulating medium capacitance detection structure, characterized by: The application relates to an insulating medium capacitor detection structure, which comprises a substrate (1), a common electrode (2) formed on the substrate (1) and a to-be-detected capacitor, wherein the to-be-detected capacitor is located in the common electrode (2) of an enclosed structure and comprises a polar plate one (3), a to-be-detected insulating medium layer (4) and a polar plate two (5) which are stacked; The polar plate one (3) is extended laterally at the edge to form a first lead-out part (31) which is in contact with a first signal pin of a GSG probe; The polar plate two (5) is extended laterally at the edge to form a second lead-out part (51) which is in contact with a second signal pin of the GSG probe; The common electrode (2) is provided with a third lead-out part (21) which is in contact with a grounding pin of the GSG probe; The top surface of the first lead-out part (31) is in contact with the first signal pin, the top surface of the second lead-out part (51) is in contact with the second signal pin, the top surface of the third lead-out part (21) is in contact with the grounding pin, and the top surfaces of the first lead-out part (31), the second lead-out part (51) and the third lead-out part (21) are located on the same plane; The first lead-out part (31) is extended along a first direction, and the second lead-out part (51) is extended along a second direction; The number of the third lead-out parts (21) is four, two of which are extended along the first direction and the first lead-out part (31) is located at the middle position of the two third lead-out parts (21), and the other two of which are extended along the second direction and the second lead-out part (51) is located at the middle position of the two third lead-out parts (21); The first direction and the second direction are opposite.

2. The insulating dielectric capacitance detection structure of claim 1, wherein: The common electrode (2) is in a rectangular frame structure, and the four third lead-out parts (21) are respectively located at the four corners of the rectangular frame, and the width of the third lead-out part (21) is greater than that of the edge beam of the common electrode (2).

3. The insulating dielectric capacitance detection structure of claim 1, wherein: The material of the common electrode (2) is aluminum, aluminum alloy, copper, tungsten, molybdenum or a first composite layer; the materials of the polar plate one (3) and the polar plate two (5) are independently aluminum, aluminum alloy, copper, tungsten, molybdenum, tantalum or a second composite layer; The first composite layer comprises a first barrier layer and a first conductive layer which are arranged in a stack, and the first barrier layer is arranged close to the substrate; the material of the first barrier layer is titanium nitride, and the material of the first conductive layer is copper; or the material of the first barrier layer is tungsten, and the material of the first conductive layer is aluminum; The second composite layer comprises a second barrier layer and a second conductive layer which are arranged in a stack, and the second barrier layer is arranged close to the to-be-detected insulating medium layer (4); the material of the second barrier layer is at least one of titanium and titanium nitride, and the material of the second conductive layer is copper or aluminum.

4. An insulating medium capacitance detection method characterized by comprising: The application further relates to a vector network analyzer which is connected with the insulating medium capacitor detection structure. The first lead-out part (31) of the polar plate one (3) is in contact with a first signal pin of a GSG probe, the second lead-out part (51) of the polar plate two (5) is in contact with a second signal pin of the GSG probe, and the third lead-out part (21) of the common electrode (2) is in contact with a grounding pin of the GSG probe. The first signal pin and the second signal pin of the GSG probe are connected with port one and port two of the vector network analyzer respectively, and the grounding pin of the GSG probe is connected with a grounding port of the vector network analyzer; A high-frequency test signal of 100MHz-10GHz is applied from the port one or the port two of the vector network analyzer to obtain a scattering parameter amplitude matrix; The scattering parameter amplitude matrix is converted into an admittance parameter matrix through matrix operation; The capacitance value is calculated based on the imaginary part of the admittance parameter.

5. The method of claim 4, wherein: The scattering parameter magnitude matrix S is ; S11 is a reflection coefficient of the port one, that is, a ratio of a reflected wave amplitude to an incident wave amplitude at the port one when a test signal is input from the port one, and represents a reflection characteristic of the port one; S12 is a transmission coefficient from the port one to the port two, that is, a ratio of a transmission wave amplitude at the port two to the incident wave amplitude at the port one when the test signal is input from the port one, and represents a transmission characteristic from the port one to the port two; S21 is a transmission coefficient from the port two to the port one, that is, a ratio of a transmission wave amplitude at the port one to the incident wave amplitude at the port two when the test signal is input from the port two, and represents a transmission characteristic from the port two to the port one; S22 is a reflection coefficient of the port two, that is, a ratio of a reflected wave amplitude to an incident wave amplitude at the port two when the test signal is input from the port two, and represents a reflection characteristic of the port two.

6. The method of claim 4, wherein, The conversion formula for converting the scattering parameter amplitude matrix into a admittance parameter matrix by matrix operation is: ; wherein Y is the admittance parameter matrix, S is the scattering parameter amplitude matrix, I is the unit matrix, and Z0 is the standard impedance. The calculation formula of the capacitance value is: ; in which, C is the calculated capacitance value, f is the frequency of the test signal, Im(Y11) is the imaginary part of the admittance parameter Y11, and Y11 is the input admittance of port one when port two is short-circuited.

7. The method of claim 4, wherein, Further comprising: The capacitance value is normalized based on the capacitance area, and the calculation formula is , C C is the capacitance value calculated before normalization, C norm C is the capacitance value after normalization, A C is the capacitance area, that is, the effective area of one of the electrode plate or the electrode plate two covering the insulating dielectric layer.

8. The method of claim 4, wherein, Further comprising: Before the insulating dielectric capacitance detection structure is connected with the vector network analyzer, SOLT calibration is performed on the GSG probe.

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