Field effect transistor containing silicon oxide-like insulating layer and manufacturing method thereof

Abstract

The invention belongs to the technical field of microelectronics, and particularly relates to a field effect transistor containing a silicon oxide-like insulating layer and a manufacturing method of the field effect transistor. The grid electrode, the source electrode and the drain electrode are located on the semiconductor active layer, the source electrode and the drain electrode are connected through a channel, the grid insulating layer is located between the grid electrode and the semiconductor active layer, and the grid insulating layer is mainly made of silicon oxide-like materials. The silicon oxide-like material is adopted in the gate dielectric insulating layer, the high-dielectric-constant silicon oxide-like gate dielectric layer is deposited and grown at the room temperature through plasma chemical vapor phase, the growth quality is controlled through the process, and remarkable advantages are shown in the aspects of dielectric property, interface stability, deposition process compatibility and mechanical flexibility; the method is suitable for preparation of rigid and flexible electronic devices, meets the application requirements of flexible, transparent and low-power electronic devices, and has a wide industrialization prospect.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a field-effect transistor containing a silicon oxide-like insulating layer and its manufacturing method. Background Technology

[0002] A field-effect transistor (FET) is a core electronic device that controls current switching by regulating the carrier density in a semiconductor channel using a gate electric field. Its typical structure consists of three electrodes: source, drain, and gate, along with a gate dielectric and a semiconductor channel layer. Compared to thin-film transistors (TFTs), primarily used for display driving, FETs have a wider range of applications, encompassing low-power logic, radio frequency devices, analog / sensing, neuromorphic computing, and flexible transparent electronics. The performance and stability of FETs depend on several key indicators, including: threshold voltage and its stability, carrier mobility and transconductance, subthreshold swing and on / off ratio, contact resistance and Schottky barrier, leakage current and breakdown behavior, as well as short-channel effect (SCE) and drain-induced barrier reduction (DIBL).

[0003] Regarding the evolution of channel materials, traditional silicon-based FETs rely on single-crystal silicon and thermal oxide systems, with mature processes, but limitations in flexibility, transparency, and low-temperature fabrication. To meet the demands of new electronics, researchers have introduced materials such as oxide semiconductors, wide-bandgap compounds, and two-dimensional layered semiconductors. Among them, indium diselenide (InSe) has attracted attention due to its layered structure, low interface scattering, and excellent electron transport properties. InSe can achieve high-quality channel layer deposition or transfer at lower temperatures, adapting to the application requirements of flexible, transparent, and post-CMOS integration; at the same time, its atomically thin characteristics help suppress short-channel effects and enhance gate control capabilities. However, InSe is relatively sensitive to interfaces and the environment. Threshold drift, hysteresis, and carrier fluctuations caused by environmental adsorption become important factors affecting device reliability. Therefore, high-quality gate dielectric and top-layer passivation / packaging are crucial for stable device performance.

[0004] In terms of the gate dielectric, as a core component of the FET, it plays a decisive role in the device's performance and stability. An ideal gate dielectric should possess high breakdown field strength and low leakage current to achieve thinner physical thickness and higher equivalent gate capacitance, thereby reducing the operating voltage; simultaneously, it should have low interface state density and low stress to suppress threshold drift and subthreshold characteristic degradation; furthermore, it needs to possess both flexibility and transparency, and be deposited at low temperatures to meet the requirements of flexibility and large-area electrons. Traditional... , While dielectric materials are mature in silicon-based FETs, they often suffer from problems such as limited lower thickness limits, brittle cracking, high density of interface traps, and bias instability in flexible electronics and two-dimensional material FETs.

[0005] In summary, the high mobility and atomically thin InSe channels offer performance potential for short-channel suppression, but they are sensitive to interfaces and the environment. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention provides a field-effect transistor containing a silicon oxide-like insulating layer and its manufacturing method. The silicon oxide-like material is used in the gate insulating layer, and its deposition and growth are controlled by PECVD process, which makes it exhibit significant advantages in dielectric properties, interface stability, deposition process compatibility and mechanical flexibility, and is suitable for the preparation of rigid and flexible electronic devices.

[0007] The technical solution adopted by the present invention to solve its technical problem is as follows: a field-effect transistor containing a silicon oxide-like insulating layer, comprising: a semiconductor active layer and a gate, a source and a drain located thereon, the source and drain being connected by a channel, and further comprising: a gate insulating layer located between the gate and the semiconductor active layer, the gate insulating layer being mainly composed of a silicon oxide-like material grown at room temperature.

[0008] Preferably, it further includes a back channel passivation layer, which is in physical contact with the semiconductor active layer, and the back channel gate dielectric layer is mainly composed of a silicon oxide-like material.

[0009] Preferably, the thickness of the gate insulating layer is 10-300 nm.

[0010] Preferably, the silica-like material comprises 70%–95% silica phase and 5%–30% siloxane polymer phase.

[0011] Preferably, the silica-like material is formed by plasma-enhanced chemical vapor deposition from a gas mixture containing one or more volatile organosilicon precursors and oxygen at room temperature.

[0012] Preferably, the volatile silicon precursor is selected from tetramethyldisiloxane, hexamethyldisiloxane, octamethyltrisiloxane, hexamethylcyclotrisiloxane, octamethylcyclotetrasiloxane, decamethylcyclopentasiloxane, and... .

[0013] Preferably, the material constituting the channel includes InSe, amorphous silicon, nanocrystalline silicon, microcrystalline silicon, polycrystalline silicon, zinc oxide, zinc tin oxide, or zinc gallium oxide.

[0014] The manufacturing method of the aforementioned field-effect transistor containing a silicon oxide-like insulating layer includes: placing a substrate in a PE-CVD chamber, introducing a source gas into the chamber, and applying a radio frequency, microwave frequency, or DC power supply to the chamber, thereby depositing a silicon oxide-like layer on the substrate; the source gas includes a volatile silicon precursor and at least one oxidant gas selected from methylsiloxane, oxygen, ozone, hydrogen peroxide, and nitrous oxide.

[0015] Preferably, the steps are as follows:

[0016] S1. Form a gate electrode on the substrate;

[0017] S2. Place the substrate with the gate electrode in the chamber of the plasma-enhanced chemical vapor deposition instrument, introduce a source gas containing volatile silicon precursor and oxidant gas into the chamber, apply radio frequency, microwave frequency or DC power to the chamber for excitation, and form a silicon oxide-like thin film on the gate electrode and the substrate at room temperature by plasma-enhanced chemical vapor deposition as the gate dielectric layer to obtain silicon oxide-like substrate.

[0018] S4. Form a semiconductor channel layer on a silicon oxide-like thin film;

[0019] S5. Form source and drain electrodes at both ends of the channel and complete the subsequent packaging process.

[0020] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0021] 1. In this invention, the field-effect transistor uses a silicon dioxide-like material as the insulating layer. This material combines the excellent insulating properties of silicon dioxide with the good interfacial compatibility of silicon, which can effectively improve the carrier transport characteristics and long-term reliability of the device while ensuring the electrical stability of the device.

[0022] 2. Silica-like materials can be prepared by plasma-enhanced chemical vapor deposition (PECVD). Siloxane precursors and oxygen are used as reactants, and thin films are deposited on the substrate surface under the action of low-temperature plasma. By adjusting process parameters such as plasma power, gas flow ratio, chamber pressure, and substrate temperature during the deposition process, the composition ratio and structural characteristics of the thin film can be effectively controlled, thereby optimizing its dielectric constant, density, and interface quality.

[0023] 3. This dielectric material has multiple applications in field-effect transistors (FETs). Firstly, it can be used as a gate dielectric layer to provide stable gate control and play a role in reducing leakage current and improving threshold voltage stability. Secondly, it can be used as a bottom dielectric layer to improve channel carrier transport efficiency and reduce the adverse effects of defect states on device performance. Thirdly, it can be used as a back-channel passivation layer to effectively reduce the interface state density that may occur during device operation, reduce performance drift caused by environmental factors or bias voltage, and significantly enhance the long-term stability of the device. The controllable fabrication of silicon oxide-like thin films is fundamental to their multifunctional applications in FETs. Through advanced processes such as atomic layer deposition and plasma-enhanced chemical vapor deposition, the thickness, chemical composition, and interface characteristics of the film can be precisely controlled to obtain silicon oxide-like dielectric layers with excellent electrical properties and good interface quality. These films can be used as gate dielectric layers in FETs to provide stable gate control, effectively suppress leakage current, and improve threshold voltage stability; they can also be used as bottom dielectric layers to help improve channel carrier transport efficiency and reduce the negative impact of defect states on device performance.

[0024] 4. Silicon oxide-like thin films also possess excellent compatibility with existing semiconductor processes, making them suitable for various field-effect transistor structures, including top-gate and bottom-gate structures, and different configurations such as top-contact or bottom-contact. This material can be used not only in silicon-based field-effect transistors but also in oxide semiconductor FETs, two-dimensional material FETs, and other novel thin-film transistor devices, providing important material choices and process pathways for the design and development of high-performance, low-power electronic devices.

[0025] In summary, this invention employs a silicon oxide-like material in the gate insulating layer, and grows a high-dielectric-constant silicon oxide-like gate dielectric layer by plasma chemical vapor deposition at room temperature. By controlling the growth quality through process control, it exhibits significant advantages in dielectric properties, interface stability, deposition process compatibility, and mechanical flexibility. It is suitable for the fabrication of rigid and flexible electronic devices, meets the application requirements of flexible, transparent, and low-power electronic devices, and has broad industrialization prospects. Attached Figure Description

[0026] Figure 1 This is a schematic cross-sectional view of an InSe field-effect transistor according to an embodiment of the present invention.

[0027] Figure 2 yes Figure 1 Transfer characteristics of InSe-FET (I DS –V GS (and gate leakage current diagram).

[0028] Figure 3 yes Figure 1 Output characteristic curve of InSe-FET (IDS –V DS )picture.

[0029] Figure 4 yes Figure 1 Output characteristics of InSe-FET in linear operating state.

[0030] Figure 5 The threshold voltage drift curves of the device of this invention (InSe-FET, silicon oxide-like gate dielectric) under different bias stresses and its comparison with those using conventional methods are shown below. A comparison of the performance of FETs with gate dielectrics at different fabrication temperatures.

[0031] Figure 6 yes Figure 5 A comparison of the transfer characteristics of a FET before and after applying gate bias stress. Detailed Implementation

[0032] To facilitate understanding of the present invention, it will be described in more detail below with reference to the accompanying drawings and specific embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of the present invention.

[0033] A field-effect transistor containing a silicon oxide-like insulating layer includes: a substrate; a gate electrode; a gate insulating layer; a semiconductor active layer; a source and a drain; a back channel passivation layer and / or an underlying layer;

[0034] Substrate: Can be selected from glass substrates, polymer films, or metal foils. For flexible electronics applications, polymer substrates such as polyimide (PI) and polyethylene terephthalate (PET) are particularly preferred.

[0035] Gate electrode: It is usually formed by depositing conductive materials (such as Al, Mo, Ti, Cu, ITO, etc.) on a substrate and forming a pattern through photolithography and etching.

[0036] Gate insulating layer: This is the core feature layer of the present invention, mainly or entirely composed of silicon oxide-like material. The main component of the silicon oxide-like material is organosilicon glass, which preferably contains about 70%–95% silicon dioxide and 30%–5% siloxane polymer, thereby ensuring good thermal stability and mechanical flexibility while maintaining a low dielectric constant (k value).

[0037] Semiconductor active layer: can be amorphous silicon ), polycrystalline silicon (poly-Si), nanocrystalline silicon ( ), microcrystalline silicon (μc-Si:H) or metal oxide semiconductors (such as IGZO).

[0038] Source and drain: They are usually made of metal layers or transparent conductive oxides (TCOs) and can form ohmic contacts with the active layer.

[0039] Back channel passivation layer and / or underlayer (optional): used to improve device reliability and adhesion. This layer is preferably made of organosilicon glass and can be combined with the SiNx underlayer to further optimize interface performance.

[0040] This invention is applicable to various FET architectures, including: inverted staggered structure and top-gate structure:

[0041] Inverted staggered structure: Deposit gate electrode on substrate; deposit silicon oxide-like layer as gate insulating layer by PECVD; deposit semiconductor active layer (such as IGZO) on insulating layer; form source and drain; selectively deposit back channel passivation layer to improve device stability.

[0042] Top-gate structure: Deposit source and drain electrodes on the substrate; deposit and pattern a semiconductor active layer between the source and drain; deposit an organosilicon glass gate insulating layer on the semiconductor layer; form the gate electrode on the insulating layer; complete device patterning through photolithography and etching.

[0043] A method for forming an "inverted interleaved" field-effect transistor with a silicon oxide-like gate insulating layer includes the following steps: (a) depositing a gate electrode on a substrate; (b) placing the substrate with the gate electrode in a PE-CVD chamber; (c) introducing a source gas into the chamber, the source gas comprising a volatile silicon precursor and at least one oxidant gas selected from oxygen, ozone, hydrogen peroxide, and nitrous oxide; and (d) applying a radio frequency, microwave frequency, or DC power supply to the chamber; thereby depositing a silicon oxide-like layer on the gate electrode and the substrate. The substrate can be any substrate known in the art suitable for fabricating field-effect transistors, such as glass, polymer foil, or metal foil. The layers are photolithographically lithographically patterned and etched to obtain a functional transistor; these processes can all employ techniques known in the art.

[0044] The manufacturing method in this invention is as follows:

[0045] (1) First, the substrate is ultrasonically cleaned sequentially in acetone and ethanol, each step lasting 10 to 15 minutes, to thoroughly remove surface organic matter and contaminants. After cleaning, the surface is dried with high-purity nitrogen gas to obtain a clean substrate for later use. The substrate is selected from polyethylene terephthalate, polyimide, polytetrafluoroethylene, polypropylene, silicon / silica, and glass substrate. Taking a silicon substrate as an example.

[0046] (2) The substrate treated as described above is placed in a plasma-enhanced chemical vapor deposition (PE-CVD) chamber, and hexamethyldisiloxane (HDMSO) and oxygen are introduced into the chamber. The gas flow rates are controlled at 40 sccm and 3 sccm, respectively. The RF power supply is turned on to excite the plasma. During the 60-minute reaction process, a silicon oxide-like insulating layer with a thickness of about 100 nm is uniformly deposited on the gate and substrate surfaces.

[0047] (3) Preparation of Indium Selenide (InSe) nanosheets using mechanical exfoliation: First, a thin layer was peeled off from the surface of the bulk InSe using blue film tape and transferred to 3M tape. By repeatedly folding the 3M tape to reduce the thickness, an InSe nanosheet of approximately 27 nm was finally obtained, which was then peeled off using blue film tape. Subsequently, a PDMS transfer template was attached to one side of a glass slide, with the other side in contact with the blue film tape containing InSe. After removing the tape, InSe was attached to the PDMS surface. The glass slide and a silicon substrate with grown SiO2 were placed together on a two-dimensional material transfer platform. By precisely controlling the slow pressing of PDMS to contact the substrate and then smoothly separating it, a reliable transfer of InSe from PDMS to a silicon oxide-like / Si substrate was achieved, ultimately forming a structurally complete InSe / silicon oxide-like / Si substrate. The transfer refers to: first obtaining a thinned semiconductor material through mechanical exfoliation, and then transferring it to the substrate by pressing. The semiconductor material used here is indium selenide, but it can also be graphene, black phosphorus, molybdenum disulfide, tungsten disulfide, tungsten diselenide, indium tin, tantalum disulfide, titanium disulfide, niobium disulfide, antimony telluride, or bismuth telluride.

[0048] (4) Perform photolithography masking process: Use a mask with a specific pattern to cover the target area and fix it precisely to define the channel pattern required for subsequent electrode deposition.

[0049] (5) The substrate with the patterned mask is inverted and mounted on the sample stage of the electron beam evaporation coating instrument, under a vacuum degree better than that of the above-mentioned substrate. In a high vacuum environment, The metal electrode is deposited at a high deposition rate to complete the device fabrication.

[0050] Finally, a high-performance two-dimensional material field-effect transistor was obtained, which consists of a substrate, a dielectric layer, a two-dimensional material layer, and a microchannel layer from bottom to top; the microchannel layer contains microchannel unit structures for flowing liquid metal. The source electrode and drain electrode are connected by a two-dimensional material.

[0051] Example 1: A field-effect transistor containing a silicon oxide-like insulating layer, fabrication method:

[0052] (1) Sonicate the bare silicon wafer in acetone for 10-15 minutes, then sonicate it with ethanol for 10-15 minutes, and finally dry it with nitrogen to obtain a clean substrate.

[0053] (2) Place the substrate prepared in step (1) in the PE-CVD chamber and introduce source gas into the chamber. The rates of hexamethyldisiloxane (HDMSO) and oxygen are 40 sccm and 3 sccm, respectively. Then apply RF power to the chamber and grow for 60 min to deposit a 100 nm silicon oxide-like layer on the gate electrode and the substrate.

[0054] (3) Use blue film tape to peel off the indium selenide material from the block, stick the peeled indium selenide material on 3M tape, and repeatedly fold the 3M tape to obtain an indium selenide material with a thickness of about 27 nm. Then use blue film tape to peel off the indium selenide material from the 3M tape. Then stick one side of the PDMS transfer template on the glass slide and the other side on the blue film tape with indium selenide. Peel off the blue film tape, and then place the glass slide and the silicon dioxide / silicon substrate on the two-dimensional material transfer platform. Use the two-dimensional material transfer platform to slowly press the PDMS with indium selenide material onto the silicon dioxide / silicon substrate, and then slowly lift it. Through the contact between PDMS and the substrate, the indium selenide material is transferred from PDMS to the silicon wafer to obtain indium selenide / silicon dioxide / silicon substrate.

[0055] (4) Mask: A mask is used to cover and fix two-dimensional material to form a channel;

[0056] (5) The substrate is inverted and fixed in the electron beam evaporation coating instrument, and used in vacuum conditions below a certain level. Under a vacuum degree, using The rate of electrode growth.

[0057] Example 2: A field-effect transistor containing a silicon oxide-like insulating layer, fabrication method:

[0058] (1) Preparation of two-dimensional material / substrate: Sonicate the polyimide (PI) film in acetone for 10-15 minutes, then sonicate it with ethanol for 10-15 minutes, and finally dry it with nitrogen to obtain a clean substrate;

[0059] (2) Fabrication of laser-induced graphene / polydimethylsiloxane (LIG / PDMS) electrodes: Laser-induced graphene (LIG) was induced on polyimide (PI) films using a laser marking machine. The laser power and scanning speed were 10~12 W and 10~12 W, respectively. The size of a single electrode is 3~7 mm × 3~7 mm, and the width between two parallel electrodes is 1~2 mm, thus obtaining a LIG / PI thin film.

[0060] (3) The substrate prepared in step (2) is placed in the PE-CVD chamber, and hexamethyldisiloxane (HDMSO) and oxygen are introduced as source gases, with flow rates set to 40 sccm and 3 sccm, respectively. Then, an RF power supply is applied, and the reaction is carried out for 60 minutes to deposit a silicon oxide-like thin film with a thickness of 100 nm on the gate electrode and the substrate surface.

[0061] (4) First, a thin layer of indium selenide was peeled off from the surface of the bulk indium selenide material using blue film tape and attached to the surface of 3M tape. By repeatedly folding the 3M tape, an indium selenide sheet with a thickness of about 27 nm was obtained, and then the indium selenide sheet was peeled off from the surface of the 3M tape using blue film tape. Subsequently, one side of the PDMS transfer template was attached to the glass slide, and the other side was attached to the blue film tape with indium selenide attached. After removing the blue film tape, the glass slide and the silicon substrate with silicon dioxide deposited were placed together on the two-dimensional material transfer platform. By controlling the platform, the PDMS with indium selenide attached was slowly pressed down to the surface of the substrate and then smoothly lifted up. The indium selenide was transferred from the PDMS to the silicon wafer by utilizing the adhesion between the PDMS and the substrate, and finally an indium selenide / silicon dioxide / PI substrate was obtained.

[0062] Example 3: A field-effect transistor containing a silicon oxide-like insulating layer, fabrication method:

[0063] (1) Sonicate the bare silicon wafer in acetone for 10-15 minutes, then sonicate it with ethanol for 10-15 minutes, and finally dry it with nitrogen to obtain a clean substrate.

[0064] (2) Place the substrate prepared in step (1) in the PE-CVD chamber and introduce source gas into the chamber. The rates of trimethylsilane and oxygen are 40 sccm and 3 sccm, respectively. Then apply RF power of 50 W to the chamber and grow for 60 min to deposit a 100 nm silicon oxide-like layer on the gate electrode and the substrate.

[0065] (3) Use blue film tape to peel off the indium selenide material from the block, stick the peeled indium selenide material on 3M tape, and repeatedly fold the 3M tape to obtain an indium selenide material with a thickness of about 27 nm. Then use blue film tape to peel off the indium selenide material from the 3M tape. Then stick one side of the PDMS transfer template on the glass slide and the other side on the blue film tape with indium selenide. Peel off the blue film tape, and then place the glass slide and the silicon oxide / silicon substrate on the two-dimensional material transfer platform. Use the two-dimensional material transfer platform to slowly press the PDMS with indium selenide material onto the silicon oxide / silicon substrate, and then slowly lift it. Through the contact between PDMS and the substrate, the indium selenide material is transferred from PDMS to the silicon wafer to obtain indium selenide / silicon oxide / silicon substrate.

[0066] (4) Mask: A mask is used to cover and fix two-dimensional material to form a channel;

[0067] (5) The substrate is inverted and fixed in the electron beam evaporation coating instrument, and used in vacuum conditions below a certain level. Under a vacuum degree, using The rate of electrode growth.

[0068] Comparative Example 1: A method for fabricating a high-mobility material field-effect transistor, the specific steps of which are as follows:

[0069] (1) First, the silica-silicon substrate is placed in an acetone solution for ultrasonic cleaning for about 15 minutes; then it is transferred to an ethanol solution for ultrasonic treatment for another 15 minutes; finally, the residual ethanol on the substrate surface is dried with a nitrogen gun to obtain a clean silica-silicon substrate. The gate dielectric layer material used in this embodiment is silica.

[0070] (2) Using a material transfer platform and a polydimethylsiloxane (PDMS) transfer template, the high-mobility InSe thin film is precisely positioned and transferred onto the silica-silicon substrate after step (1).

[0071] The specific procedure is as follows: Thin sheets of material are obtained by peeling bulk indium selenide (InSe) using 3M Scotch tape. The material is thinned by repeatedly folding the tape to achieve a thickness in the tens of nanometers range. A pre-prepared PDMS transfer template is fixed to the surface of a glass slide. Then, blue film tape is used to peel the InSe material from the 3M tape and attach it to the other side of the PDMS template, thus transferring the material from the 3M tape to the PDMS template. Finally, the imaging system of the material transfer platform is used to select InSe sheets of suitable thickness and precisely transfer them to the target location on a silica-silicon substrate.

[0072] (3) The high mobility material field-effect transistor is fabricated by depositing the source and drain through a mask process.

[0073] After the high-mobility material transfer was completed, the InSe material was covered with a metal mask under a polarizing microscope to determine the channel region of the device, with the channel width set to approximately 20 μm. The square regions on both sides of the channel on the metal mask correspond to the source and drain electrode regions. Subsequently, the mask-InSe-silicon dioxide-silicon substrate were placed in the chamber of an electron beam evaporation deposition machine, and a 20 nm thick Bi metal layer and a 50 nm thick Au metal layer were deposited sequentially, with the deposition rate controlled at approximately 0.3 Å / s. After the evaporation process, an InSe field-effect transistor with conventional Bi / Au electrode contacts was obtained.

[0074] Figure 1This is a schematic cross-sectional view of an InSe field-effect transistor according to an embodiment of the present invention, wherein a silicon oxide-like gate insulating layer of about 100 nm is deposited at room temperature. Figure 2 It shows Figure 1 Transfer characteristics of InSe-FET (I DS –V GS The data, along with the gate leakage current, demonstrates that the field-effect transistor exhibits greater than [a certain characteristic] in the linear region. Effective electron field-effect mobility, greater than 1×10 7 The on / off current ratio, threshold voltage less than 4.0V, and subthreshold slope less than 500mV / dec. Figure 3 It shows Figure 1 Output characteristic curve of InSe-FET ( This indicates that the device steadily increases in the linear region at a gate voltage of -5 to 5 V with a step of 2 V, and the output current remains stable in the saturation region at a threshold voltage of less than 4.0 V. Figure 4 It shows Figure 1 The output characteristics of the InSe-FET under linear operating conditions indicate that the ohmic current of the device increases linearly under low electric field, demonstrating ohmic contact and thus exhibiting extremely strong gate control capability.

[0075] Further experiments:

[0076] 1. First, the output characteristic curves of the high-performance two-dimensional material field-effect transistor based on van der Waals contact (hereinafter referred to as "van der Waals contact FET") prepared in Example 1 and the indium selenide field-effect transistor with ordinary Bi-Au electrode contact (hereinafter referred to as "ordinary contact FET") prepared in Comparative Example 1 were tested. The test range was set to the gate voltage (V). GS The scan from -10 V to +10 V yielded the following results: Figure 5 As shown. Figure 5 The threshold voltage drift curves of the device of the present invention (InSe-FET, silicon oxide-like gate dielectric) under different bias stresses are shown, and compared with those using conventional SiN. x The performance of FETs with gate dielectrics at different fabrication temperatures was compared. The results show that silicon oxide-like dielectric devices exhibit smaller threshold drift and better stability.

[0077] In the specific testing process, a combination of a source meter and a probe station was used to achieve accurate measurements. A three-probe structure was used to connect to the source, drain, and gate of the device, respectively, thus ensuring the accuracy and repeatability of the test. The source meter used was the Keithley 2636B, which has high-precision current and voltage measurement and output capabilities, and can meet the requirements for accurate characterization of small currents. Under the test conditions, the voltage between the source and drain was defined as V.DS The gate voltage is V GS The current between the source and drain is I. DS .

[0078] Depend on Figure 5 It can be observed that, regardless of whether it is a FET based on van der Waals contacts or a conventional contact FET, its source-drain current (Id) is... DS All of them can be significantly modulated by changes in gate voltage, and I DS With V GS The gradual increase in voltage as the voltage increases indicates that both types of devices exhibit typical field-effect transistor characteristics. However, a comparison clearly reveals that van der Waals contact FETs are more sensitive to gate voltage response under the same conditions. DS The faster growth rate indicates that its gate control capability and carrier injection efficiency are both superior to those of ordinary contact FETs.

[0079] 2. To further verify the above conclusions, the output characteristics of the two types of devices were also tested over a wider voltage range. The test conditions for this experiment were: gate voltage (V GS The voltage varies between 0V and +10V, while the source-drain voltage (V) varies between 0V and +10V. DS The test was performed from -5 V to 5 V. The test results are as follows: Figure 6 As shown.

[0080] from Figure 6 It can be clearly seen that as the gate voltage gradually increases, the source-drain current I of both types of devices increases. DS All exhibit a trend of increasing voltage, and all can be effectively controlled, conforming to the basic operating principles of field-effect transistors. However, compared to ordinary contact FETs, van der Waals contact FETs can output higher Ig under the same voltage conditions. DS The current saturation value of van der Waals contact FETs is significantly higher, especially when entering the saturation region. This result demonstrates that van der Waals contacts play a crucial role in reducing the metal-semiconductor interface barrier and improving charge injection characteristics, thereby enabling the device to maintain excellent conductivity under high-voltage operating conditions.

[0081] 3. Subsequently, the transfer characteristic curves of the two types of devices were systematically tested, and the results are as follows: Figure 6 As shown. The test method is the same as described above, still using a Keithley 2636B source meter, and contacting the source, drain, and gate with a three-probe system via a probe station. During the test, the source-drain voltage V is maintained. DS Constant, by scanning the gate voltage V GS The source and drain current I is obtained. DS With V GS The relationship curve between them.

[0082] Depend on Figure 6 The results show that both devices exhibit typical transfer characteristic curves. However, the threshold voltage of the van der Waals contact FET shows a significant leftward shift compared to the ordinary contact FET, indicating a certain n-type doping effect. This change in threshold voltage demonstrates that van der Waals contacts can effectively reduce the Fermi level pinning effect and mitigate the adverse effects of interface traps on device performance. Simultaneously, the van der Waals contact FET also exhibits a larger turn-on current and a higher on / off ratio, demonstrating its significant application potential in low-power logic circuits and high-performance electronic devices.

[0083] 4. Based on the comparison of transfer characteristic curves, the mobility of the two types of devices was further calculated using test data, and the results are as follows: Figure 5 As shown. The formula for calculating mobility is as follows:

[0084] Formula 1;

[0085] Where L is the channel length, W is the channel width, and Ci is the capacitance per unit area of ​​the gate dielectric layer.

[0086] Gate dielectric capacitance C i The calculation can be performed using the following formula:

[0087] The C i It can be calculated using Equation 2;

[0088] Formula 2;

[0089] Where ε0 is the vacuum permittivity (8.854 × 10^-12 F·m). -1 εr is the relative permittivity of the gate dielectric (3.9), and d is the thickness of the gate dielectric.

[0090] The calculation results clearly show that the mobility of van der Waals contact FETs is significantly better than that of ordinary contact FETs, with an improvement of nearly five times. This result indicates that van der Waals contacts can significantly improve carrier transport capability and reduce interface scattering, thereby effectively improving the electrical performance of devices.

[0091] 5. In addition, according to Figure 5 Based on the transfer characteristic curve data, the contact resistance (Rsd) of the two types of devices was analyzed and calculated using the Y-function method.

[0092] Depend on Figure 6As can be seen, the contact resistance of the van der Waals contact FET is significantly reduced compared to that of a conventional contact FET, with a reduction of nearly 10 times. This significant improvement further validates the advantages of van der Waals contacts in reducing the metal-semiconductor contact barrier and improving charge injection efficiency. Lower contact resistance means that the device can achieve lower power consumption and faster response speed in high-frequency applications, which is of great significance for the realization of future ultra-low power electronic devices.

[0093] In summary, the embodiments of this invention, through a series of comparative experiments, fully demonstrate that the introduction of van der Waals contacts can significantly improve the performance of indium selenide (InSelenide) field-effect transistors (FETs) in multiple aspects. Specifically, this is reflected in: higher source-drain current modulation sensitivity, larger saturation current, a significant leftward shift of the threshold voltage and a higher on / off ratio, while simultaneously improving mobility and significantly reducing contact resistance. These improvements not only illustrate the unique advantages of van der Waals contacts in two-dimensional material devices but also provide new design ideas and technical paths for the development of future high-performance, low-power two-dimensional electronic devices.

[0094] It's important to understand that when one component is described as being "above" another, it means it's located further away from the substrate, not limited to direct physical contact; other functional layers can exist between them. For example, in a top-gate FET structure, the gate electrode can be described as being "above" the substrate, even if dielectric layers, channel layers, and other intermediate layers are present in between. Similarly, an "electrical connection" between two components means that current can be conducted from one component to the other, regardless of whether there are other conductive or semiconductor layers in between.

[0095] It should be emphasized that although the technical solution has been described in detail in conjunction with the accompanying drawings, this does not constitute a limitation on the scope of protection of the present invention. Various modifications, equivalent substitutions, or variations that can be made by those skilled in the art without creative effort based on the technical solution of the present invention should be considered to fall within the scope of protection of the present invention.

Claims

1. A field-effect transistor containing a silicon oxide-like insulating layer, comprising: A semiconductor active layer and a gate, a source, and a drain located thereon, wherein the source and drain are connected by a channel, characterized in that it further comprises: a gate insulating layer located between the gate and the semiconductor active layer, the gate insulating layer being mainly composed of a silicon oxide-like material grown at room temperature.

2. The field-effect transistor containing a silicon oxide-like insulating layer according to claim 1, characterized in that, It also includes a back channel passivation layer, which is in physical contact with the semiconductor active layer, and the back channel gate dielectric layer is mainly composed of silicon oxide-like materials.

3. The field-effect transistor containing a silicon oxide-like insulating layer according to claim 1, characterized in that, The thickness of the gate insulating layer is 10-300 nm.

4. The field-effect transistor containing a silicon oxide-like insulating layer according to any one of claims 1-3, characterized in that, The silica-like material comprises 70%–95% silica phase and 5%–30% siloxane polymer phase.

5. The field-effect transistor containing a silicon oxide-like insulating layer according to claim 4, characterized in that, Silica-like materials are formed by plasma-enhanced chemical vapor deposition from a gas mixture containing one or more volatile organosilicon precursors and oxygen at room temperature.

6. The field-effect transistor containing a silicon oxide-like insulating layer according to claim 5, characterized in that, The volatile silicon precursor is selected from tetramethyldisiloxane, hexamethyldisiloxane, octamethyltrisiloxane, hexamethylcyclotrisiloxane, octamethylcyclotetrasiloxane, decamethylcyclopentasiloxane, and... .

7. The field-effect transistor containing a silicon oxide-like insulating layer according to claim 1, characterized in that, The materials that make up the trench include Amorphous silicon, nanocrystalline silicon, microcrystalline silicon, polycrystalline silicon, zinc oxide, zinc tin oxide or zinc gallium oxide.

8. The method for manufacturing a field-effect transistor containing a silicon oxide-like insulating layer as described in any one of claims 1-7, characterized in that, include: The substrate is placed in a PE-CVD chamber, a source gas is introduced into the chamber, and radio frequency, microwave frequency or DC power is applied to the chamber to deposit a silicon oxide-like layer on the substrate; the source gas includes volatile silicon precursors and at least one oxidant gas selected from methyl siloxane, oxygen, ozone, hydrogen peroxide and nitrous oxide.

9. The manufacturing method according to claim 8, characterized in that, The steps are as follows: S1. Form a gate electrode on the substrate; S2. Place the substrate with the gate electrode in the chamber of the plasma-enhanced chemical vapor deposition instrument, introduce a source gas containing volatile silicon precursor and oxidant gas into the chamber, apply radio frequency, microwave frequency or DC power to the chamber for excitation, and form a silicon oxide-like thin film on the gate electrode and the substrate at room temperature by plasma-enhanced chemical vapor deposition as the gate dielectric layer to obtain silicon oxide-like substrate. S4. Form a semiconductor channel layer on a silicon oxide-like thin film; S5. Form source and drain electrodes at both ends of the channel and complete the subsequent packaging process.

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