High-side driving circuit, electronic equipment and vehicle
By introducing a current-limiting protection circuit into the high-side drive circuit, overcurrent protection is achieved through a hardware mechanism, which solves the problem of slow response speed in traditional software, improves the safety and flexibility of the circuit, and is suitable for application scenarios that require long-term power supply.
Patent Information
- Application Number
- CN202411000731.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-24
- Publication Date
- 2026-01-27
AI Technical Summary
Traditional high-side drive circuits rely on software task cycles for overcurrent protection, resulting in slow response speeds. They cannot effectively limit current or shut down the circuit in a timely manner, posing a risk of circuit board burnout.
A hardware overcurrent protection mechanism is adopted. When the load current exceeds the preset value, the current limiting protection circuit switches to the on state and converts the input voltage into the target voltage for output. When the current limiting protection circuit is off, the PMOS transistor is in the variable resistance region and in the constant current region when it is on, thus realizing overcurrent protection.
It improves the response speed of overcurrent protection, can limit current in a timely and effective manner, reduces the risk of circuit damage, is suitable for bypass current power supply needs when the equipment is not in operation, and has a simple circuit structure and low hardware cost.
Smart Images
Figure CN121417643A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power electronics technology, and in particular to a high-side drive circuit, electronic equipment, and vehicle. Background Technology
[0002] High-side drive circuits refer to circuits that directly drive a load by adding a controllable switch at the power supply end. High-side drive circuits typically integrate overcurrent protection during design. Traditional high-side drive circuits rely on software task cycles and responses for overcurrent protection; however, this software overcurrent protection mechanism has a slow response speed and cannot effectively limit current or shut down the circuit in a timely manner, posing a risk of circuit board burn-out. Summary of the Invention
[0003] In view of the above problems, this application provides a high-side drive circuit, electronic device, and vehicle to improve the response speed of overcurrent protection in the high-side drive circuit. The specific solution is as follows:
[0004] The first aspect of this application provides a high-side driving circuit, including: a power distribution circuit 100 and a current limiting protection circuit 200;
[0005] The power distribution circuit 100 includes a PMOS transistor and a first resistor circuit 10. The gate G of the PMOS transistor is grounded through the first resistor circuit 10, the drain D of the PMOS transistor is used to connect to the load, and the source S of the PMOS transistor and the input terminal of the current limiting protection circuit 200 are used to connect to the DC power supply. The output terminal of the current limiting protection circuit 200 is connected to the gate G of the PMOS transistor.
[0006] The current limiting protection circuit 200 is used to switch from the off state to the on state when the load current is detected to exceed the preset value; in the on state, the current limiting protection circuit 200 converts the input voltage into the target voltage for output, and in the off state, there is no voltage output;
[0007] The PMOS transistor is in the variable resistance region when the current limiting protection circuit 200 is off, and in the constant current region when the current limiting protection circuit 200 is on.
[0008] In one possible implementation, the current limiting protection circuit 200 includes a PNP transistor, a second resistor circuit 20, a third resistor circuit 30, and a fourth resistor circuit 40.
[0009] The first end of the second resistor circuit 20 is connected to the source S of the PMOS transistor, and the second end of the second resistor circuit 20 is used to connect to the DC power supply.
[0010] The emitter E of the PNP transistor is connected to the second terminal of the second resistor circuit 20, the collector C of the PNP transistor is connected to the gate G of the PMOS transistor through the third resistor circuit 30, and the base B of the PNP transistor is connected to the source S of the PMOS transistor through the fourth resistor circuit 40.
[0011] The current limiting protection circuit 200 switches from the off state to the on state, specifically: the PNP transistor switches from the cutoff region to the amplification region.
[0012] In one possible implementation, the second resistor circuit 20 includes a shunt resistor.
[0013] In one possible implementation, the high-side drive circuit further includes: a reverse protection diode D1; the anode of the reverse protection diode D1 is connected to the DC power supply, and the cathode of the reverse protection diode D1 is connected to the input terminal of the current limiting protection circuit 200.
[0014] In one possible implementation, the high-side driving circuit further includes a first filtering circuit connected to the output terminal of the current limiting protection circuit 200, for filtering the output signal of the current limiting protection circuit 200.
[0015] In one possible implementation, the first filter circuit includes a first capacitor C1 connected in parallel with the first resistor circuit 10.
[0016] In one possible implementation, the high-side drive circuit further includes a second filter circuit connected to the drain D of the PMOS transistor for filtering the output signal of the drain D of the PMOS transistor.
[0017] In one possible implementation, the second filter circuit includes a second capacitor C2, one end of which is connected to the drain D of the PMOS transistor, and the other end is grounded.
[0018] A second aspect of this application provides an electronic device, including: a high-side driving circuit as described in the first aspect or any implementation thereof.
[0019] In one possible implementation, the electronic device is an in-vehicle controller.
[0020] A third aspect of this application provides a vehicle, including: an electronic device as described in the second aspect or any implementation thereof.
[0021] Using the above technical solution, the high-side drive circuit provided in this application has no output from the current-limiting protection circuit 200 when the load current is normal, and the gate-source voltage VGS of the PMOS transistor is reverse-biased. At this time, the PMOS transistor is in the variable resistance region, and the drain D and source S of the PMOS transistor are equivalent to a resistor, which is connected in series with the load for normal power distribution. However, when the load current is overcurrent, the current-limiting protection circuit 200 starts to output current, pulling down the absolute value of the gate-source voltage |VGS|, causing the PMOS transistor to enter the constant current region, limiting the load current to a small value, thereby achieving overcurrent protection. This application adopts a hardware overcurrent protection mechanism, which can effectively limit the current in a timely manner when the load current is overcurrent. The hardware overcurrent protection mechanism has a faster response speed than the software overcurrent protection mechanism. Attached Figure Description
[0022] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0023] Figure 1 This application provides a schematic diagram of the structure of a regional controller in an automobile.
[0024] Figure 2 A schematic diagram of a high-side drive circuit provided in this application;
[0025] Figure 3 A schematic diagram of yet another high-side drive circuit provided in this application;
[0026] Figure 4 A schematic diagram of yet another high-side drive circuit provided in this application;
[0027] Figure 5 A schematic diagram of yet another high-side drive circuit provided in this application;
[0028] Figure 6 This application provides a state simulation diagram of a high-side drive circuit when the load current does not exceed a predetermined safety level.
[0029] Figure 7 This application provides a state simulation diagram of a high-side drive circuit when the load current exceeds a predetermined safety level.
[0030] Figure 8 This is a schematic diagram of the structure of another type of area controller in a car provided in this application. Detailed Implementation
[0031] In order to ensure the accuracy of the citations and the fluency of reading, the key technical terms, abbreviations or acronyms used in the text are summarized and explained as follows:
[0032] HSD: HighSide Driver;
[0033] EEA: Electrical / Electronic Architecture;
[0034] ADAS: Advanced Driver Assistance System;
[0035] ECU: Electronic Control Unit;
[0036] MCU: Microcontroller Unit;
[0037] PCB: Printed Circuit Board, also known as printed circuit board or printed circuit board;
[0038] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor.
[0039] HSD circuits (also known as HSD power distribution drive circuits) are circuit configurations that achieve direct drive of the load by adding a controllable switch at the power supply end. This circuit configuration allows for precise control of the power supply and is particularly suitable for precision devices that require fine adjustment of the power output, and has wide application value in fields such as automotive and industrial control.
[0040] Taking the application of HSD circuits in automotive area controllers as an example: With the adjustment of automotive EEA (Electrical Engineering, Automation, and Control), the design of in-vehicle controllers is gradually shifting from the traditional functionally integrated domain controller architecture to a physical space domain fusion controller architecture. This new domain fusion architecture mainly consists of area controllers and a central domain controller. The central domain controller is primarily responsible for handling tasks requiring significant computing power, including but not limited to the computational processing of complex functions such as ADAS (Advanced Driver Assistance Systems) and autonomous driving. The area controller, on the other hand, undertakes more execution-level tasks, integrating the functions of many smaller controllers, including but not limited to air conditioning control, tailgate control, and power distribution-related functions. The area controller is essentially an ECU (Electronic Control Unit), such as... Figure 1 As shown, this ECU integrates an MCU, an HSD circuit, and various other chips. Figure 1(Not shown in the image), the HSD circuit is used to directly drive the vehicle body load under the power supply of power source KL30, which may include, for example, another ECU and a capacitive load. Figure 1 In this context, GND represents the ground terminal.
[0041] HSD circuits are typically designed with multiple protection functions integrated, such as overcurrent protection, to ensure circuit stability and safety. Overcurrent protection means that when the current in the circuit exceeds a predetermined safe level, the HSD circuit automatically reduces the output current or shuts down the circuit to prevent damage to the load or power supply.
[0042] Overcurrent protection in traditional HSD circuits relies on software task cycles and software responses (e.g., Figure 1 Overcurrent protection in HSD circuits needs to be implemented under the software control of the MCU. However, this software overcurrent protection mechanism has a slow response speed and cannot effectively limit current or shut down the circuit in a timely manner, posing a risk of PCB trace burning, which can easily lead to damage to the load or power supply. PCB trace burning refers to the burning phenomenon of traces (also known as circuit lines or copper wires) on the PCB due to overheating or other reasons.
[0043] To improve the response speed of overcurrent protection in HSD circuits, this application provides an HSD circuit that employs a hardware overcurrent protection mechanism. This mechanism can effectively limit the current in a timely manner when the load current exceeds a predetermined safety level. Compared with software overcurrent protection mechanisms, hardware overcurrent protection mechanisms have a faster response speed.
[0044] The HSD circuit provided in the embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.
[0045] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.
[0046] See Figure 2 The HSD circuit provided in this application embodiment includes: a power distribution circuit 100 and a current limiting protection circuit 200;
[0047] The power distribution circuit 100 includes a PMOS transistor and a first resistor circuit 10. The gate G of the PMOS transistor is grounded through the first resistor circuit 10, the drain D of the PMOS transistor is used to connect to the load, and the source S of the PMOS transistor and the input terminal of the current limiting protection circuit 200 are used to connect to the DC power supply. The output terminal of the current limiting protection circuit 200 is connected to the gate G of the PMOS transistor.
[0048] The current limiting protection circuit 200 is used to be in the off state when the load current is detected to be within the preset value (i.e., the load current is not exceeding the predetermined safety level), and to switch from the off state to the on state when the load current is detected to exceed the preset value; the current limiting protection circuit 200 converts the input voltage into the target voltage for output in the on state, and has no voltage output in the off state;
[0049] When the current limiting protection circuit 200 is in the off state, the PMOS transistor is in the variable resistance region, and when the current limiting protection circuit 200 is in the on state, it enters the constant current region.
[0050] The following section discusses the operating characteristics of PMOS transistors. Figure 2 The working principle of the HSD circuit shown is explained in detail below:
[0051] HSD circuits achieve direct load driving by adding a controllable switch at the power supply end. This controllable switch is typically a MOSFET, or MOS transistor for short. MOS transistors can be divided into two types based on their channel type: NMOS (N-channel MOS transistor) and PMOS (P-channel MOS transistor). In this embodiment, a PMOS transistor is used as the controllable switch. The operating characteristics of the PMOS transistor are described in sections 1-2 below:
[0052] 1) The conduction and cutoff of the PMOS transistor are mainly controlled by the gate-source voltage VGS (the voltage difference between the gate G and the source S). When the gate-source voltage VGS of the PMOS transistor is greater than the turn-on voltage VGSth (the turn-on voltage VGSth is negative), the PMOS transistor is in the cutoff region. At this time, there is no conductive path between the drain D and the source S, and the drain current is close to zero.
[0053] 2) When the gate-source voltage VGS < the turn-on voltage VGSth, the PMOS transistor turns on, allowing current to flow from the source (S) to the drain (D). During this stage, the following conditions 2.1 to 2.2 are met:
[0054] 2.1) When the gate-source voltage VGS < the threshold voltage VGSth and the drain-source voltage VDS (the voltage difference between the drain and the source) > VGS - VGSth, the PMOS transistor enters the variable resistance region. In the variable resistance region, the drain D and the source S of the PMOS transistor can be regarded as a variable resistance controlled by the gate-source voltage VGS. In the variable resistance region, when the gate-source voltage VGS is constant, the drain current and the drain-source voltage VDS are basically linearly related. The absolute value of the drain-source voltage of the PMOS transistor |VDS| = Rdson × Iload, where Rdson represents the on-resistance of the PMOS transistor and Iload represents the drain current, that is, the load current.
[0055] 2.2) When the gate-source voltage VGS < the threshold voltage VGSth and the drain-source voltage VDS < VGS - VGSth, the PMOS transistor enters the constant current region. In the constant current region, the magnitude of the drain current is only controlled by the gate-source voltage VGS and is positively correlated with the absolute value of the gate-source voltage |VGS|. At this time, the drain D and the source S of the PMOS transistor can be regarded as a current source controlled by the gate-source voltage VGS. In the constant current region, when the gate-source voltage VGS is constant, the drain current hardly changes with the change of the drain-source voltage VDS and shows a constant current characteristic. The cut-off region, the variable resistance region, and the constant current region all belong to the working regions of the PMOS transistor.
[0056] When the load current is different, Figure 2 the states of the HSD circuit shown are different. Refer to the following content 1-2:
[0057] 1) When the load current does not exceed the predetermined safety level, there is:
[0058] When the load current does not exceed the predetermined safety level, the current limiting protection circuit 200 is in the off state and has no voltage output; the gate G of the PMOS transistor is grounded through the first resistor circuit 10, and the first resistor circuit 10 is called a pull-down resistor. When there is no external signal driving the gate of the PMOS transistor, the pull-down resistor will pull down the gate voltage of the PMOS transistor to close to zero voltage; and the source of the PMOS transistor is connected to the DC power supply, so the source voltage of the PMOS transistor is a relatively high voltage. At this time, there is a reverse bias between the gate and the source of the PMOS transistor (that is, a reverse voltage is applied between the gate and the source of the PMOS transistor), the gate-source voltage VGS remains a negative value and the absolute value of the gate-source voltage |VGS| > the absolute value of the threshold voltage |VGSth|, meeting the conduction condition of the PMOS transistor. The PMOS transistor conducts, and through reasonable circuit parameter configuration, it can be ensured that at this time the drain-source voltage VDS > VGS - VGSth, making the PMOS transistor in the variable resistance region.
[0059] When Figure 2When the PMOS transistor in it is in the variable resistance region, since the gate-source voltage VGS is basically fixed at this time, the drain D and source S of the PMOS transistor can be regarded as a fixed resistor. At this time, the HS0D circuit is connected in series with the load for normal power distribution.
[0060] The bypass function means that even when the device enters a non-working state (such as sleep, standby, etc.), it can ensure normal power distribution to the load (mainly some key loads), ensuring that the power supply line of the load is not cut off. It is especially suitable for scenarios where the load needs to be powered for a long time, such as maintaining the continuity of certain functions or states inside the load, such as maintaining data and maintaining the clock signal. The power distribution current output by the circuit during bypass is called the bypass current (Bypass current). The HSD circuit provided in the embodiments of the present application can be used to provide this bypass current to the load. That is to say, the embodiments of the present application are especially suitable for application scenarios where small current power supply and power distribution are still required for a long time when the device is in a non-working state.
[0061] The current from the device to the ground when the device is in a non-working state (such as sleep, standby, etc.) is called the static current. The power consumption generated by the static current flowing through the circuit is called the static power consumption. Its order of magnitude is small, but it persists throughout the operation of the entire circuit. Accumulated over a long time, it will also cause obvious energy waste. For Figure 2 For the HSD circuit shown, when the load current does not exceed the predetermined safety level, the static current of the HSD circuit is mainly the current flowing through the first resistor circuit 10. Since the voltage drop across the first resistor circuit 10 is basically zero, the static current of the HSD circuit is basically zero, and the static power consumption is basically zero.
[0062] 2) When the load current exceeds the predetermined safety level, there is:
[0063] When a short-circuit condition, a soft short-circuit condition, or a large inrush current (i.e., Inrush current) occurs during power distribution, the load current may exceed the predetermined safety level. At this time, the current limiting protection circuit 200 enters the on state and outputs current to the first resistor circuit 10. The voltage drop across the first resistor circuit 10 increases. Correspondingly, the gate voltage of the PMOS transistor increases, resulting in a decrease in the absolute value of the gate-source voltage |VGS|. Through reasonable circuit parameter configuration, it can be ensured that the drain-source voltage VDS < VGS - VGSth at this time, and the PMOS transistor enters the constant current region. In the constant current region, the drain current of the PMOS transistor, that is, the load current, is positively correlated with |VGS|. A decrease in |VGS| will limit the drain current of the PMOS transistor to a small value, thereby achieving overcurrent protection. The magnitude of the current limiting (i.e., the magnitude of the limited drain current) is related to the circuit parameter configuration and can be flexibly configured according to actual application requirements.
[0064] In summary, the HSD circuit provided in this application embodiment has no output from the current limiting protection circuit 200 when the load current is normal, and the gate-source voltage VGS of the PMOS transistor is reverse biased. At this time, the PMOS transistor is in the variable resistance region, and the drain D and source S of the PMOS transistor are equivalent to a resistor, which is connected in series with the load for normal power distribution. However, when the load current is excessive (which may be due to short circuit, soft short circuit, or excessive surge current during power distribution), the current limiting protection circuit 200 starts to output current, lowering the absolute value of the gate-source voltage |VGS|, causing the PMOS transistor to enter the constant current region, limiting the load current to a small value, thereby achieving overcurrent protection. This application embodiment adopts a hardware overcurrent protection mechanism, which can effectively limit the current in a timely manner when the load current is excessive. The hardware overcurrent protection mechanism has a faster response speed than the software overcurrent protection mechanism.
[0065] Moreover, the embodiments of this application can provide the bypass current required to output to the load when the device is not in operation, and the static current is basically zero, which is particularly suitable for application scenarios where a small current power supply needs to be maintained for a long time when the device is not in operation.
[0066] Moreover, the embodiments of this application are self-built circuits, and the current limiting current and bypass current are hardware configurable (flexible configuration of circuit parameters refers to the ability to adjust various circuit parameters as needed during circuit design and implementation to meet specific performance requirements). The circuit parameters can be flexibly configured according to actual application needs. This has a significant advantage over integrated HSD circuit chips, whose parameters cannot be adjusted and can only be upgraded to adapt to different needs (due to limitations in chip size and heat dissipation, integrated HSD circuit chips can support relatively small bypass current when the device is not in operation, and can only obtain larger bypass current through chip upgrades).
[0067] Moreover, traditional HSD circuits often experience inrush currents during power distribution. Traditional HSD circuits rely on software overcurrent protection mechanisms, which may directly shut down the circuit when the inrush current exceeds a predetermined safety level, resulting in unsuccessful power distribution. In contrast, the embodiments of this application limit the current supply to subsequent loads when the inrush current exceeds a predetermined safety level, thus fulfilling the function of normal power distribution.
[0068] Moreover, the circuit structure of the embodiments of this application is simple and the hardware cost is low.
[0069] In one possible implementation, see Figure 3 The current limiting protection circuit 200 includes a PNP transistor, a second resistor circuit 20, a third resistor circuit 30, and a fourth resistor circuit 40.
[0070] The first end of the second resistor circuit 20 is connected to the source S of the PMOS transistor, and the second end is used to connect to the DC power supply. The emitter E of the PNP transistor is connected to the second end of the second resistor circuit 20. The collector C of the PNP transistor is connected to the gate G of the PMOS transistor via the third resistor circuit 30, and the base B of the PNP transistor is connected to the source S of the PMOS transistor via the fourth resistor circuit 40.
[0071] The following is about Figure 3 The working principle of the current limiting protection circuit 200 shown in the figure is described in detail below:
[0072] The second resistor circuit 20 is a sampling resistor. The current limiting protection circuit 200 samples the load current by sampling the voltage across the second resistor circuit 20. A PN junction is formed between the emitter (E) and base (B) of the PNP transistor. The second resistor circuit 20 is connected in parallel with this PN junction, so the voltage drop across the second resistor circuit 20 is equal to the voltage drop across the PN junction. The magnitude of the load current directly affects the voltage drop across the PN junction.
[0073] With proper circuit parameter configuration, when the load current is within the normal range, the absolute value of the voltage drop across the PN junction is less than the absolute value of the turn-on voltage of the PNP transistor, |VEBth|. At this time, the PNP transistor is in the cutoff region, and the voltage difference VEC between the emitter E and collector C of the PNP transistor is close to infinity, with almost no current flowing from the emitter E to the collector C. However, when the load current is too large, the absolute value of the voltage drop across the PN junction is greater than the absolute value of the turn-on voltage, |VEBth|. At this time, the PNP transistor enters the amplification region, and a small change in the base current will cause a large change in the collector current, thereby amplifying the signal. The on-resistance of the PNP transistor directly affects the gate-source voltage VGS of the PMOS transistor, making the drain current of the PMOS transistor in the constant current region approximately equal to VBEth / Rshunt, where Rshunt represents the resistance value of the second resistor circuit 20. As can be seen, the current limiting protection circuit 200 switches from the off state to the on state, specifically: the PNP transistor switches from the cutoff region to the amplification region. Both the cutoff region and the amplification region are the working regions of the PNP transistor.
[0074] The third resistor circuit 30 and the fourth resistor circuit 40 mainly serve as current limiting protection.
[0075] In one possible implementation, for example Figure 4 As shown, the second resistor circuit 20 includes a first resistor R9. Further, the first resistor R9 can be a shunt resistor. A shunt resistor, also known as a current-shunt resistor, is a low-resistance resistor primarily used in high-current sensing applications. Compared to ordinary resistors, shunt resistors offer low resistance and high precision, ensuring a measurable voltage is generated when current flows, and providing accurate measurement results.
[0076] In one possible implementation, see still Figure 4 The first resistor circuit 10 in any of the HSD circuits provided above includes a second resistor R1.
[0077] In one possible implementation, see still Figure 4 The third resistor circuit 30 in any of the HSD circuits provided above includes a third resistor R2.
[0078] In one possible implementation, see still Figure 4 The fourth resistor circuit 40 in any of the HSD circuits provided above includes a fourth resistor R7.
[0079] In one possible implementation, see Figure 5 The HSD circuit provided above further includes: a reverse protection diode D1, the anode of which is connected to the DC power supply, and the cathode of which is connected to the input terminal of the current limiting protection circuit 200. The reverse protection diode D1 mainly serves to prevent reverse conduction, that is, to prevent energy from flowing back into the DC power supply.
[0080] In one possible implementation, any of the HSD circuits provided above further includes: a first filter circuit connected to the output terminal of the current limiting protection circuit 200, used to filter the output signal of the current limiting protection circuit 200, reduce the influence of interference signals on the output signal of the current limiting protection circuit 200, make the output signal more stable and clear, thereby improving the reliability and stability of the circuit.
[0081] In one possible implementation, see still Figure 5 The first filter circuit includes a first capacitor C1, and the first capacitor C1 and the first resistor circuit 10 ( Figure 5 (The diagram only shows the first resistor circuit R1 including the second resistor R1) in parallel.
[0082] In one possible implementation, any of the HSD circuits provided above further includes: a second filter circuit connected to the drain D of the PMOS transistor, used to filter the output signal of the drain D of the PMOS transistor, reduce the influence of interference signals on the output signal of the drain D of the PMOS transistor, make the output signal more stable and clear, thereby improving the reliability and stability of the circuit.
[0083] In one possible implementation, see still Figure 5 The second filter circuit includes a second capacitor C2, one end of which is connected to the drain D of the PMOS transistor, and the other end is grounded.
[0084] To more clearly demonstrate the technical effects of the embodiments of this application, this application also provides a method based on... Figure 5The state simulation diagram of the HSD circuit obtained from the simulation.
[0085] exist Figure 5 In this setup, a parallel capacitor C3 and resistor R3 simulate the load. The capacitor C3 = 1mF, resistor R3 = 30Ω, the reverse protection diode D1 is an MBRS340, the first resistor R9 = 1Ω, the PMOS transistor is a PWV250EPEA, the fourth resistor R7 = 10kΩ, the third resistor R2 = 1kΩ, the first capacitor C1 = 100nF, the second resistor R1 = 200kΩ, the second capacitor C2 = 100nF, the DC power supply output voltage V1 = 12V, and the PNP transistor is a BC807-40. Based on this setup, the following is obtained: Figure 6 and Figure 7 Two simulation diagrams.
[0086] exist Figure 6 and Figure 7 The simulation timeframe of 0s to 10s shown in the figure includes the periods from 0s to 3s and from 6s to 10s, which represent the power-on timeframe of the HSD circuit (i.e., the period during which the DC power supply outputs 12V), and the period from 3s to 6s, which represents the power-off timeframe of the HSD circuit (i.e., the period during which the DC power supply outputs no voltage). The main purpose of this simulation is to observe and compare the state of the HSD circuit during its power-on timeframe.
[0087] When the load current does not exceed the predetermined safety level, the state simulation diagram of the HSD circuit is as follows: Figure 6 As shown, Figure 6 The figures show the curves of the following parameters as a function of time: the cathode voltage V(n002) of the anti-reverse diode D1, the source voltage V(n003) of the PMOS transistor, the drain voltage V(n004) of the PMOS transistor, the gate voltage V(n005) of the PMOS transistor, the absolute value of the gate-source voltage V(n003)-V(n005) of the PMOS transistor, the load current (i.e., the current I(R3) on resistor R3), and the current I(R1) on the second resistor R1. Figure 6 The diagram shows that during the power-on period of the HSD circuit, the cathode voltage of the anti-reverse diode D1 is approximately 11.709V, the source voltage of the PMOS transistor is approximately 11.334V, the drain voltage of the PMOS transistor is approximately 11.266V, and the gate voltage of the PMOS transistor is approximately 1.163mV.
[0088] The state simulation diagram of the HSD circuit when the load current exceeds the predetermined safety level is as follows: Figure 7 As shown, Figure 7The figures show the curves of the following parameters as a function of time: the cathode voltage V(n002) of the anti-reverse diode D1, the source voltage V(n003) of the PMOS transistor, the drain voltage V(n004) of the PMOS transistor, the gate voltage V(n005) of the PMOS transistor, the absolute value of the gate-source voltage V(n003)-V(n005) of the PMOS transistor, and the load current, i.e., the current I(R3) across resistor R3. Figure 7 The diagram shows that during the power-on period of the HSD circuit, the cathode voltage of the anti-reverse diode D1 is approximately 11.696V, the source voltage of the PMOS transistor is approximately 11.197V, the drain voltage of the PMOS transistor is approximately 5.989V, and the gate voltage of the PMOS transistor is approximately 8.902V.
[0089] In addition, embodiments of this application also provide an electronic device, including: an HSD circuit as provided in any of the above embodiments.
[0090] In one possible implementation, the electronic device is, for example, an in-vehicle controller.
[0091] In one possible implementation, the onboard controller is, for example, a region controller within a physical space domain fusion controller architecture for the vehicle. Figure 8 As shown, compared to Figure 1 The HSD circuit in this area controller can be without communication connection to the MCU. The overcurrent protection of the HSD circuit does not need to be implemented under the software control of the MCU, but is implemented using a hardware overcurrent protection mechanism.
[0092] In addition, this application also provides a vehicle, including: electronic equipment as provided in any of the above embodiments.
[0093] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the invention. Therefore, the embodiments of the invention are not to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A high-side driving circuit, characterized in that, include: Power distribution circuit (100) and current limiting protection circuit (200); The power distribution circuit (100) includes a PMOS transistor and a first resistor circuit (10); the gate (G) of the PMOS transistor is grounded through the first resistor circuit (10), the drain (D) of the PMOS transistor is used to connect to the load, and the source (S) of the PMOS transistor and the input terminal of the current limiting protection circuit (200) are both used to connect to the DC power supply; the output terminal of the current limiting protection circuit (200) is connected to the gate (G) of the PMOS transistor. The current limiting protection circuit (200) is used to switch from the off state to the on state when the load current exceeds the preset value; the current limiting protection circuit (200) converts the input voltage into the target voltage for output in the on state, and has no voltage output in the off state; The PMOS transistor is in the variable resistance region when the current limiting protection circuit (200) is off, and in the constant current region when the current limiting protection circuit (200) is on.
2. The high-side driving circuit according to claim 1, characterized in that, The current limiting protection circuit (200) includes a PNP transistor, a second resistor circuit (20), a third resistor circuit (30), and a fourth resistor circuit (40); The first end of the second resistor circuit (20) is connected to the source (S) of the PMOS transistor, and the second end of the second resistor circuit (20) is used to connect to the DC power supply. The emitter (E) of the PNP transistor is connected to the second terminal of the second resistor circuit (20), the collector (C) of the PNP transistor is connected to the gate (G) of the PMOS transistor through the third resistor circuit (30), and the base (B) of the PNP transistor is connected to the source (S) of the PMOS transistor through the fourth resistor circuit (40). The current limiting protection circuit (200) switches from the off state to the on state, specifically: the PNP transistor switches from the cutoff region to the amplification region.
3. The high-side driving circuit according to claim 2, characterized in that, The second resistor circuit (20) includes a shunt resistor.
4. The high-side driving circuit according to claim 1 or 2, characterized in that, The high-side drive circuit also includes: a reverse protection diode (D1); The anode of the anti-reverse diode (D1) is connected to the DC power supply, and the cathode of the anti-reverse diode (D1) is connected to the input terminal of the current limiting protection circuit (200).
5. The high-side driving circuit according to claim 1 or 2, characterized in that, The high-side driving circuit further includes a first filtering circuit connected to the output terminal of the current limiting protection circuit (200), the first filtering circuit being used to filter the output signal of the current limiting protection circuit (200).
6. The high-side driving circuit according to claim 5, characterized in that, The first filter circuit includes a first capacitor (C1); the first capacitor (C1) is connected in parallel with the first resistor circuit (10).
7. The high-side driving circuit according to claim 1 or 2, characterized in that, The high-side drive circuit further includes a second filter circuit connected to the drain (D) of the PMOS transistor, the second filter circuit being used to filter the output signal of the drain (D) of the PMOS transistor.
8. The high-side driving circuit according to claim 7, characterized in that, The second filter circuit includes a second capacitor (C2); one end of the second capacitor (C2) is connected to the drain (D) of the PMOS transistor, and the other end is grounded.
9. An electronic device, characterized in that, include: The high-side driving circuit as described in any one of claims 1 to 8.
10. A vehicle, characterized in that, include: The electronic device as described in claim 9.