A broadband MMIC delay line chip based on constant resistance delay network

Abstract

The application discloses a kind of broadband MMIC delay line chips based on constant resistance delay network, including input port, output port and six sequentially connected delay units, the input port is connected with the output port by six sequentially connected delay units;Each of the delay unit includes first port, second port, reference state transmission line, constant resistance delay network and first switch-eighth switch;The constant resistance delay network includes coupled microstrip line, and parallel capacitor loaded on coupled microstrip line.The application is based on the gating of constant resistance delay network and series-parallel switch, realizes delay and ground state selection, can improve isolation, and effectively reduce chip volume.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microstrip monolithic integrated circuit (MMIC), and particularly relates to a wideband MMIC delay line chip based on a constant resistance delay network. BACKGROUND

[0002] The existing programmable delay line chip is mostly implemented by using a distributed transmission line or a digital control switch array to realize delay adjustment, but has the following problems:

[0003] 1. Limited bandwidth: the traditional structure is difficult to match impedance under a wideband signal, leading to deterioration of high-frequency performance;

[0004] 2. Contradiction between size and precision: the distributed transmission line needs to occupy a large area, and it is difficult to realize compatibility of small size and high-precision delay;

[0005] 3. High insertion loss: the cascade of the switch network and the transmission line introduces additional loss, affecting the dynamic range of the system;

[0006] 4. High control complexity: a special level control is mostly used, and the compatibility with a general logic level (such as TTL) is poor. SUMMARY

[0007] The application aims to overcome the deficiencies of the prior art, and provides a wideband MMIC delay line chip based on a constant resistance delay network, which realizes delay and ground state selection based on the gating of the constant resistance delay network and the series-parallel switch, can improve the isolation, and effectively reduces the chip size.

[0008] The application aims to overcome the deficiencies of the prior art, and provides a wideband MMIC delay line chip based on a constant resistance delay network, which realizes delay and ground state selection based on the gating of the constant resistance delay network and the series-parallel switch, can improve the isolation, and effectively reduces the chip size.

[0009] Each delay unit comprises a first port, a second port, a reference state transmission line, a constant resistance delay network, and a first switch to an eighth switch; the first end of the reference state transmission line is connected to the first port through the first switch, and the second end of the reference state transmission line is connected to the second port through the second switch; the first end of the constant resistance delay network is connected to the first port through the third switch, and the second end of the constant resistance delay network is connected to the second port through the fourth switch; one end of the fifth switch is connected to the first end of the reference state transmission line, and the other end is grounded; one end of the sixth switch is connected to the second end of the reference state transmission line, and the other end is grounded; one end of the seventh switch is connected to the first end of the constant resistance delay network, and the other end is grounded; one end of the eighth switch is connected to the second end of the constant resistance delay network, and the other end is grounded.

[0010] The six sequentially connected delay units have different delay bits.

[0011] The constant resistance delay network comprises a coupled microstrip line; one end of the coupled microstrip line serves as a first end of the constant resistance delay network, and the other end of the coupled microstrip line serves as a second end of the constant resistance delay network.

[0012] Starting from the first end of the constant resistance delay network, every 1 / 4 wavelength corresponding to a working frequency is used as a loading position of a capacitor on the coupled microstrip line, and each loading position of the capacitor is used for connecting a capacitor, and when the capacitor is connected, one end of the capacitor is connected with the loading position of the capacitor, and the other end of the capacitor is grounded.

[0013] The first port of the first delay unit is connected with the input port, the first port of each of the second to sixth delay units is connected with the second port of the previous delay unit, and the second port of the sixth delay unit is connected with the output port.

[0014] The beneficial effects of the present application are as follows: 1. wideband impedance matching: constant resistance characteristics are realized in the range of 200MHz-4GHz, and signal reflection and loss are reduced;

[0015] 2. high-precision delay adjustment: through comprehensive optimization of constant resistance delay network and switch parasitic parameters, precise control of step length is realized;

[0016] 3. small size design: the coupled microstrip line is adopted, so that the chip area can be effectively compressed;

[0017] 4. low insertion loss: through complementary switch group design to improve isolation, energy loss in the signal path is reduced; BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a schematic diagram of the principle of the present application;

[0019] Figure 2 is a schematic diagram of the serpentine coupled microstrip line;

[0020] Figure 3 is a schematic diagram of the circular ring coupled microstrip line;

[0021] Figure 4 is a schematic diagram of the square ring coupled microstrip line;

[0022] Figure 5 is a schematic diagram of the delay unit. DETAILED DESCRIPTION

[0023] The technical solutions of the present application will be further described in detail below with reference to the accompanying drawings, but the protection scope of the present application is not limited to the following description.

[0024] As shown in Figure 1 A wideband MMIC delay line chip based on constant resistance delay network includes an input port, an output port and six delay units connected in sequence, the input port is connected with the output port through the six delay units connected in sequence.

[0025] Each of the delay units includes a first port, a second port, a reference state transmission line, a constant resistance delay network and a first switch to an eighth switch; the first end of the reference state transmission line is connected to the first port through the first switch, and the second end of the reference state transmission line is connected to the second port through the second switch; the first end of the constant resistance delay network is connected to the first port through the third switch, and the second end of the constant resistance delay network is connected to the second port through the fourth switch; one end of the fifth switch is connected with the first end of the reference state transmission line, and the other end is grounded; one end of the sixth switch is connected with the second end of the reference state transmission line, and the other end is grounded; one end of the seventh switch is connected with the first end of the constant resistance delay network, and the other end is grounded; one end of the eighth switch is connected with the second end of the constant resistance delay network, and the other end is grounded.

[0026] As shown in Figure 1 In the embodiment of the application, either port 1 can be used as the input port and port 2 as the output port, or port 2 can be used as the output port and port 1 as the output port.

[0027] In the embodiment of the application, the first port and the second port of each of the delay units are grounded through a 50-ohm resistor.

[0028] The six delay units connected in sequence have different delay bits.

[0029] The constant resistance delay network includes a coupled microstrip line; one end of the coupled microstrip line is used as the first end of the constant resistance delay network, and the other end of the coupled microstrip line is used as the second end of the constant resistance delay network.

[0030] Starting from the first end of the constant resistance delay network, every 1 / 4 wavelength corresponding to the working frequency on the coupled microstrip line is used as a loading position of a capacitor, and each loading position of the capacitor is used to connect a capacitor, and when the capacitor is connected, one end of the capacitor is connected with the loading position of the capacitor, and the other end of the capacitor is grounded.

[0031] In the six delay units connected in sequence, the first port of the first delay unit is connected with the input port; for the second delay unit to the sixth delay unit, the first port of each of the delay units is connected with the second port of the previous delay unit; the second port of the sixth delay unit is connected with the output port.

[0032] First, unit delay analysis is performed. A constant-resistance delay network structure is adopted, and a constant-resistance delay network model is established by using coupled microstrip lines with loaded capacitors.

[0033] The delay of this constant impedance delay network can be expressed by the following formula:

[0034]

[0035] in, For the equivalent inductance of the coupled microstrip line, For microstrip line phase velocity, To load a parallel capacitor. In the embodiments of this application, the coupled microstrip line is a serpentine coupled microstrip line, a circular ring coupled microstrip line, or a square ring coupled microstrip line, such as... Figures 2-4 As shown; for serpentine coupled microstrip lines, coupling is generated by different parallel segments within the microstrip line; in circular or square ring coupled microstrip lines, coupling occurs between different rings; the network delay can be adjusted by modifying the linewidth, spacing, length, and applied capacitance of the coupled microstrip line. Considering that ordinary microstrip lines require a very large physical length (much greater than the physical length of a straightened coupled microstrip line), thus greatly increasing the physical size of the chip and causing bandwidth narrowing, this application uses coupled microstrip lines, which significantly improves the equivalent inductance, exhibits good impedance-frequency characteristics, significantly increases bandwidth, and reduces the physical size of the chip.

[0036] In the embodiments of this application, for each delay unit, two branches are constructed. One branch is inserted into a constant-impedance delay network, and the other branch is in the reference state. The branch selection is controlled by two sets of switches operating in complementary states to achieve switching between the reference state and the delay state. The schematic diagram is as follows. Figure 5 As shown.

[0037] Switches SW1, SW4, SW5, and SW8 are connected in series to enable and disable branch selection, while switches SW2, SW3, SW6, and SW7 are connected in parallel to improve isolation. When VG1 is 0V and VG2 is -5V, SW5 and SW8 are on, and SW6 and SW7 are off, enabling the reference-state branch selection. At this time, the signal from the first port is transmitted to the second port without delay (only path delay). When VG1 is -5V and VG2 is 0V, SW1 and SW4 are on, and SW2 and SW3 are off, enabling the constant-resistance delay network branch selection. The series switches exhibit parasitic capacitance. Parallel switches have a turn-off capacitor. .

[0038] The unit delay is mainly a constant impedance delay network. Meanwhile, the pHEMT switch also introduces RC delay. Due to the introduction of the switch's parasitic capacitance, the constant resistance delay network experiences delay. It can be represented as:

[0039]

[0040] wherein, is the on-state capacitance of the parallel switch, is the parasitic capacitance of the series switch.

[0041] the pHEMT switch introduces which can be expressed as:

[0042]

[0043] wherein, is the on-state resistance of the series switch.

[0044] After the process is determined, the of the pHEMT switches SW2 and SW3, the size of the SW2 and SW4 only depends on its physical size, and its size will affect the loss and isolation of the delay line. When the size of the switch is determined, the unit delay can be adjusted by adjusting the line width, line spacing and line length of the interwinding microstrip line and the size of the loaded capacitor.

[0045] In the embodiment of the present application, the chip is composed of six different delay bits, which are 25ps, 50ps, 100ps, 200ps, 400ps and 800ps respectively. The six delay bits are connected in series to obtain a maximum delay of 1575ps. The overall circuit diagram is shown in Figure 1 .

[0046] The overall delay of the six delay bits can be expressed by the following formula.

[0047]

[0048] The delay of the whole chip is composed of six delay bits. The delay of each delay bit includes a constant resistance delay network part and the part introduced by the pHEMT switch . When is 1, the kth delay bit is gated, and the bit generates delay. When is 0, the kth delay bit is not gated, and the bit is the ground state.

[0049] In the embodiment of the present application, the chip adopts WIN P25ED process design, and the line width and line spacing of each delay bit are designed to be consistent. The microstrip line width is designed to be 30um, and the spacing is set to 20um. The delay amount is adjusted by the length of the microstrip line and the size of the loaded capacitor. After the design of each delay bit is completed, the layout is arranged by comprehensively considering the input and output standing wave, and the logic control unit and the corresponding PAD are placed together.

[0050] The foregoing description illustrates and describes one preferred embodiment of the present application only, and as previously discussed it is to be understood that the application is not limited to the precise forms described herein, and that all modifications, equivalents, and alternatives falling within the spirit and scope of the application as described herein are included.

Claims

1. A broadband MMIC delay line chip based on a constant impedance delay network, characterized in that: It includes an input port, an output port, and six sequentially connected delay units, wherein the input port is connected to the output port through the six sequentially connected delay units; Each of the aforementioned delay units includes a first port, a second port, a reference state transmission line, a constant impedance delay network, and a first to an eighth switch; the first end of the reference state transmission line is connected to the first port via the first switch, and the second end of the reference state transmission line is connected to the second port via the second switch; the first end of the constant impedance delay network is connected to the first port via the third switch, and the second end of the constant impedance delay network is connected to the second port via the fourth switch; one end of the fifth switch is connected to the first end of the reference state transmission line, and the other end is grounded; one end of the sixth switch is connected to the second end of the reference state transmission line, and the other end is grounded; one end of the seventh switch is connected to the first end of the constant impedance delay network, and the other end is grounded; one end of the eighth switch is connected to the second end of the constant impedance delay network, and the other end is grounded. The constant impedance delay network includes a coupled microstrip line; one end of the coupled microstrip line serves as the first end of the constant impedance delay network, and the other end of the coupled microstrip line serves as the second end of the constant impedance delay network. Starting from the first end of the constant impedance delay network, on the coupled microstrip line, every 1 / 4 wavelength corresponding to the operating frequency is used as a capacitor loading position. Each capacitor loading position is used to connect a capacitor. When connecting the capacitor, one end of the capacitor is connected to the capacitor loading position, and the other end of the capacitor is grounded. The coupled microstrip line can be a serpentine coupled microstrip line, a circular ring coupled microstrip line, or a square ring coupled microstrip line. For a serpentine coupled microstrip line, coupling is generated by different parallel segments in the microstrip line. In a circular ring coupled microstrip line or a square ring coupled microstrip line, coupling is generated between different rings. The network delay can be adjusted by adjusting the linewidth, line spacing, line length, and the size of the applied capacitor of the coupled microstrip line.

2. The broadband MMIC delay line chip based on a constant impedance delay network according to claim 1, characterized in that: The six sequentially connected delay units have different delay bits.

3. A broadband MMIC delay line chip based on a constant impedance delay network according to claim 1, characterized in that: In the six sequentially connected delay units, the first port of the first delay unit is connected to the input port; for the second to sixth delay units, the first port of each delay unit is connected to the second port of the previous delay unit; the second port of the sixth delay unit is connected to the output port.

4. A broadband MMIC delay line chip based on a constant impedance delay network according to claim 1, characterized in that: The first to the eighth switches are all MOS switches.

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