Anti-pad structure for optimizing high-speed via hole of PCB (Printed Circuit Board)

Abstract

The utility model relates to an anti-pad structure for optimizing a PCB high-speed via hole, which comprises a via hole pile, the via hole pile penetrates through a multi-layer PCB, and two ends of the via hole pile are respectively connected with differential signal pair wires; the combined elliptical anti-bonding pads are distributed at the wire inlet and the wire outlet of the via hole pile and are composed of a large elliptical bonding pad and a small elliptical bonding pad which are tangent, the long axis length of the large ellipse is D1, the short axis length of the large ellipse is d1, the long axis length of the small ellipse is D2, and the short axis length of the small ellipse is d2; the single circle anti-bonding pad is arranged in the copper column area of the via hole pile, the diameter of the single circle anti-bonding pad is d3, and d3 is larger than the diameter d0 of the via hole and smaller than d1. According to the anti-bonding pad structure for optimizing the PCB high-speed via hole, the combined elliptical anti-bonding pad realizes impedance gradual change from differential routing to a copper column area by means of a specific size proportion, and signal reflection at the two ends of a via hole pile is reduced; a single circle anti-bonding pad optimizes impedance in a copper column area and is matched with a U-shaped shunting groove to shield electromagnetic interference, and meanwhile, a diversion groove is communicated with the U-shaped shunting groove to form a three-stage backflow path, so that crosstalk is reduced.

Description

Technical Field

[0001] This utility model relates to the field of electronic information technology, specifically to an optimized anti-soldering pad structure for high-speed vias on PCBs. Background Technology

[0002] In high-speed digital circuits and communications, the signal integrity of printed circuit boards (PCBs) directly affects device performance. Differential signal transmission is widely used in high-speed interfaces (such as PCIe and USB 3.0) due to its advantages such as strong anti-interference ability and low power consumption.

[0003] However, in traditional PCB design, vias, as a key structure for vertical interconnects, are prone to signal reflection and attenuation due to impedance abrupt changes. Especially in GHz-level high-frequency scenarios, the parasitic capacitance and inductance of vias can lead to signal integrity deterioration. It is necessary to improve impedance matching by optimizing the shape of the anti-pad (such as combining elliptical or circular anti-pads).

[0004] With the rapid development of technologies such as 5G and data centers, the long-distance transmission of high-speed signals in multilayer PCBs faces severe challenges. In existing technologies, impedance mismatch between vias and differential pairs can easily cause electromagnetic radiation and crosstalk, especially in backplane or high-density interconnect scenarios. Traditional designs lack targeted optimization for the distribution of high-frequency electromagnetic fields, making it difficult to balance signal integrity, power stability and electromagnetic compatibility. Therefore, an optimized anti-pad structure for high-speed vias in PCBs is proposed. Utility Model Content

[0005] To achieve the above objectives, this utility model provides the following technical solution: an optimized anti-pad structure for high-speed PCB vias, including via posts.

[0006] The via pins penetrate the multi-layer PCB board, with differential signal pairs connected to their respective ends;

[0007] The combined elliptical anti-pads are distributed at the inlet and outlet of the via pins. They consist of two tangent elliptical pads, one large and one small. The major axis of the large ellipse is D1 and the minor axis is d1, while the major axis of the small ellipse is D2 and the minor axis is d2.

[0008] A single circular anti-pad is set in the copper pillar area of ​​the via pin, with a diameter of d3, and satisfies d3 > via diameter d0 and d3 < d1;

[0009] Non-functional pads surround the outside of the combined elliptical anti-pads and are connected to the combined elliptical anti-pads;

[0010] The anti-pad area is covered by a combination of elliptical anti-pads and a single circular anti-pad, forming a stepped isolation structure.

[0011] The flow channel is located at the connection between the differential signal pair trace and the combined elliptical anti-pad to guide the signal return path;

[0012] The gradient transition region, located between the combined elliptical antipad and the single circular antipad, consists of three levels of elliptical rings with decreasing major axes and a spacing of 0.1d0 between adjacent elliptical rings.

[0013] U-shaped flow dividers are symmetrically opened on both sides of the through-hole copper pillar area, with a width of 0.2d0 and a depth of 0.3 times the dielectric layer thickness.

[0014] Furthermore, the size ratio of the large ellipse to the small ellipse in the combined elliptical anti-pad satisfies: D1 / D2=1.5~2.5, d1 / d2=1.2~1.8.

[0015] Furthermore, the diameter d3 of the single circular anti-pad is in the range of: d0+20μm≤d3≤d1-30μm.

[0016] Furthermore, the width of the non-functional pad is S, and S ≥ 2 times the via diameter d0.

[0017] Furthermore, the anti-soldering pad area is symmetrically distributed between PCB layers, and the distance between its outer boundary and inner boundary is 0.5 to 1 times the via diameter d0.

[0018] Furthermore, the elliptical rings in the gradient transition region adopt a gradually shrinking design, with the major axis decreasing from D1 to d3, and the spacing between each level of elliptical rings being 0.1d0.

[0019] Furthermore, the U-shaped diversion channel is connected to the guide channel to form a three-stage return path, and the bottom of the channel is flush with the surface of the medium layer.

[0020] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0021] 1. This optimized anti-pad structure for high-speed PCB vias combines elliptical anti-pads with specific size ratios to achieve impedance gradients from differential traces to the copper pillar area, reducing signal reflections at both ends of the via post; a single circular anti-pad optimizes impedance in the copper pillar area, working in conjunction with a U-shaped shunt to shield electromagnetic interference. Simultaneously, the shunt and the U-shaped shunt are connected to form a three-stage return path, reducing crosstalk and solving signal integrity problems caused by impedance abrupt changes and parasitic parameters in traditional vias.

[0022] 2. The optimized anti-pad structure for high-speed vias on PCBs features non-functional pads surrounding a combined elliptical anti-pad, with a wider width to enhance mechanical support and prevent via posts from delaminating due to thermal expansion differences in thick boards. The anti-pad area is stepped, compensating for impedance and suppressing electromagnetic interference. The gradient transition area achieves smooth impedance transition, taking into account signal integrity, power stability, and electromagnetic compatibility. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of this utility model;

[0024] Figure 2 This is a top view of the structure of a single circular anti-solder pad of this utility model;

[0025] Figure 3 This is a top view of the combined elliptical anti-pad, non-functional pad, and anti-pad region of this utility model.

[0026] Figure 4 This is a schematic diagram of the gradient transition region of this utility model.

[0027] In the diagram: 101, via pin; 102, differential signal pair trace; 103, combined elliptical anti-pad; 104, single circular anti-pad; 105, non-functional pad; 106, anti-pad area; 107, flow channel; 108, gradient transition area; 109, U-shaped flow channel. Detailed Implementation

[0028] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0029] Please see Figure 1-4 This embodiment provides an optimized anti-pad structure for high-speed PCB vias, including via posts 101.

[0030] The via 101 penetrates the multilayer PCB board and is connected to the differential signal pair traces 102 at both ends.

[0031] The combined elliptical anti-pad 103 is distributed at the inlet and outlet of the via 101. It consists of two tangent elliptical pads, one large and one small. The major axis of the large ellipse is D1 and the minor axis is d1, while the major axis of the small ellipse is D2 and the minor axis is d2.

[0032] A single circular anti-solder pad 104 is set in the copper pillar area of ​​the via post 101, with a diameter of d3, and satisfies d3 > via diameter d0 and d3 < d1;

[0033] Non-functional pad 105 surrounds the outside of combined elliptical anti-pad 103 and is connected to combined elliptical anti-pad 103.

[0034] The anti-pad region 106 covers the combined elliptical anti-pad 103 and the single circular anti-pad 104, forming a stepped isolation structure.

[0035] A guide groove 107 is provided at the connection between the differential signal pair trace 102 and the combined elliptical anti-pad 103 to guide the signal return path.

[0036] The gradient transition region 108 is located between the combined elliptical anti-pad 103 and the single circular anti-pad 104. It consists of three levels of elliptical rings with decreasing major axes and a spacing of 0.1d0 between adjacent elliptical rings.

[0037] U-shaped diversion channels 109 are symmetrically opened on both sides of the through-hole copper pillar area, with a channel width of 0.2d0 and a depth of 0.3 times the dielectric layer thickness.

[0038] The via pin 101 is a copper pillar structure that vertically penetrates the multilayer PCB board to realize the vertical interconnection of differential signals between different layers. Its through-through design reduces the bending of the signal transmission path and reduces transmission loss. It is directly connected to the differential signal pair trace 102 to ensure a lossless transition of signals from horizontal routing to vertical interconnection. In thick boards such as 4mm backplanes, the high aspect ratio design of the via pin 101 needs to be combined with the stress dispersion function of the guide groove 107 and the U-shaped diversion groove 109 to avoid copper pillar breakage.

[0039] Differential signal pair traces 102 are designed with equal length and equal impedance to transmit complementary signals. Common-mode noise is suppressed through coupling effect. The connection end with the via 101 adopts a stepped guide groove 107 to guide the signal return path and match the impedance of the anti-pad. The depth H of the guide groove 107 is 0.1~0.3 times the thickness of the dielectric layer and is connected to the U-shaped shunt groove 109 to form a three-level return path: guide groove 107 → U-shaped shunt groove 109 → dielectric layer, which reduces the signal return impedance and suppresses electromagnetic radiation.

[0040] The combined elliptical anti-pad 103 is located at the inlet and outlet ends of the via 101. It consists of two tangent ellipses of different sizes, D1 / D2=1.5~2.5 and d1 / d2=1.2~1.8. Its gradient elliptical ring design achieves a smooth transition of impedance from the differential trace to the copper pillar area. By gradually changing the impedance D1→D2→d3, the reflection of high-frequency signals at both ends of the via 101 is reduced. For example, when D1=100μm and D2=60μm, the impedance gradually decreases from 50Ω to 35Ω, matching the impedance of the single circular anti-pad in the copper pillar area.

[0041] A single circular anti-pad 104 is located in the copper pillar area of ​​the via 101, with a diameter d3 satisfying d0+20μm≤d3≤d1-30μm. Its circular structure reduces impedance abrupt changes in the copper pillar area and avoids secondary reflections caused by the gradient design of the combined elliptical anti-pad 103 in the middle of the copper pillar. In conjunction with the gradient transition area 108, impedance abrupt changes are limited to the end of the copper pillar area. Combined with the electromagnetic shielding function of the U-shaped shunt 109, common-mode noise radiation is reduced.

[0042] Non-functional pads 105 surround the outer side of the combined elliptical anti-pads 103 with a width S≥2d0. By increasing the pad area, mechanical support is enhanced, preventing via pins 101 from delaminating in thick plates due to differences in thermal expansion coefficients. Combined with the stepped isolation structure of the anti-pad area 106, the bonding force between PCB layers is improved, making it suitable for high-temperature and high-vibration environments.

[0043] The anti-pad region 106 covers the combined elliptical anti-pad 103 and the single circular anti-pad 104, forming a stepped isolation structure with a distance of 0.5~1d0 between the outer and inner boundaries. Electromagnetic interference is suppressed through stepped impedance compensation. In multilayer PCBs, the stepped isolation structure and the dielectric constant gradient distribution εr=3.5→2.8 of the dielectric layer work together to compensate for high-frequency signal transmission loss and meet the timing consistency requirements of PCIe 5.0.

[0044] A guide channel 107 is formed at the connection between the differential signal pair trace 102 and the combined elliptical anti-pad 103, with a depth H = 0.1~0.3 times the dielectric layer thickness, guiding the signal return path. A U-shaped shunt channel 109 is symmetrically formed on both sides of the copper pillar area, with a channel width of 0.2d0 and a depth of 0.3 times the dielectric layer thickness, and is connected to the end of the guide channel 107 to form a three-stage return path. The collaborative design of the guide channel 107 and the U-shaped shunt channel 109 divides the signal return path into three stages: guide channel 107 → U-shaped shunt channel 109 → dielectric layer, reducing the return path impedance and reducing crosstalk. For example, when the dielectric layer thickness is 50μm, the depth of the U-shaped shunt channel 109 is 15μm, ensuring that common-mode noise is discharged through the dielectric layer rather than interfering with the differential signal.

[0045] In summary, this optimized anti-pad structure for high-speed PCB vias, using a combination of elliptical anti-pads 103 with specific size ratios, achieves impedance gradient from differential traces to the copper pillar region, reducing signal reflection at both ends of the via post 101. A single circular anti-pad 104 optimizes impedance in the copper pillar region, working in conjunction with a U-shaped shunt 109 to shield electromagnetic interference. Simultaneously, the guide channel 107 connects to the U-shaped shunt 109, forming a three-stage return path, reducing crosstalk and solving signal integrity problems caused by impedance abrupt changes and parasitic parameters in traditional vias.

[0046] Furthermore, the non-functional pad 105 surrounds the combined elliptical anti-pad 103, with a wider width to enhance mechanical support and prevent the via pin 101 from delaminating due to thermal expansion differences in the thick plate; the anti-pad area 106 is stepped, compensating for impedance and suppressing electromagnetic interference, and the gradient transition area 108 achieves a smooth impedance transition, taking into account signal integrity, power stability and electromagnetic compatibility.

[0047] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An optimized anti-pad structure for high-speed vias on PCBs, comprising via posts (101), characterized in that: The via pin (101) penetrates the multilayer PCB board and is connected to the differential signal pair traces (102) at both ends. The combined elliptical anti-pad (103) is distributed at the inlet and outlet of the via pin (101). It consists of two tangent elliptical pads, one large and one small. The major axis of the large ellipse is D1 and the minor axis is d1. The major axis of the small ellipse is D2 and the minor axis is d2. A single circular anti-pad (104) is set in the copper pillar area of ​​the via post (101), with a diameter of d3, and satisfies d3 > via diameter d0 and d3 < d1; Non-functional pads (105) surround the outside of the combined elliptical anti-pads (103) and are connected to the combined elliptical anti-pads (103); The anti-pad area (106) covers the combined elliptical anti-pad (103) and the single circular anti-pad (104) to form a stepped isolation structure; A guide channel (107) is provided at the connection between the differential signal pair trace (102) and the combined elliptical anti-pad (103) to guide the signal return path; The gradient transition region (108), located between the combined elliptical antipad (103) and the single circular antipad (104), consists of three levels of elliptical rings with decreasing major axes and a spacing of 0.1d0 between adjacent elliptical rings; U-shaped diversion channels (109) are symmetrically opened on both sides of the through-hole copper pillar area, with a channel width of 0.2d0 and a depth of 0.3 times the dielectric layer thickness.

2. The optimized anti-pad structure for high-speed PCB vias according to claim 1, characterized in that, The size ratio of the large ellipse to the small ellipse in the combined elliptical anti-solder pad (103) satisfies: D1 / D2=1.5~2.5, d1 / d2=1.2~1.

8.

3. The optimized anti-pad structure for high-speed PCB vias according to claim 1, characterized in that, The diameter d3 of the single circular anti-solder pad (104) is in the range of: d0+20μm≤d3≤d1-30μm.

4. The optimized anti-pad structure for high-speed PCB vias according to claim 1, characterized in that, The width of the non-functional pad (105) is S, and S ≥ 2 times the via diameter d0.

5. The optimized anti-pad structure for high-speed PCB vias according to claim 1, characterized in that, The anti-soldering pad area (106) is symmetrically distributed between PCB layers, and the distance between its outer boundary and inner boundary is 0.5 to 1 times the via diameter d0.

6. The optimized anti-pad structure for high-speed PCB vias according to claim 1, characterized in that, The elliptical rings of the gradient transition region (108) adopt a gradually shrinking design, with the major axis decreasing from D1 to d3, and the spacing between each level of elliptical rings is 0.1d0.

7. The optimized anti-pad structure for high-speed PCB vias according to claim 1, characterized in that, The U-shaped diversion channel (109) is connected to the flow guide channel (107) to form a three-stage return path, with the bottom of the channel flush with the surface of the medium layer.

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