Data transmission method and device of network on chip, slice assembly, and storage medium

Abstract

The embodiment of the application discloses a data transmission method and device of a network on chip, a slice component and a storage medium. The method comprises the following steps: in the case that a data packet is received from an upstream routing node, confirming a target output direction of the data packet; according to the storage state of a target output register and a target backup register corresponding to the target output direction, writing the data packet into the target output register or the target backup register, or sending a retransmission signal for the data packet to the upstream routing node; sending the data packet to a downstream routing node through the target output register or the target backup register, and temporarily storing the data packet in the target backup register or the target output register before confirming that the data packet is received by the downstream routing node; in the case that a retransmission signal sent by the downstream routing node to the data packet is received, sending the data packet from the target output register or the target backup register to the downstream routing node.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of network-on-chip technology, and particularly relates to a data transmission method and device of a network-on-chip, a slice component and a storage medium. BACKGROUND

[0002] With the rapid development of multi-core processors and network-on-chip (NoC) technology, network communication plays a vital role in chip design. The network-on-chip realizes the temporary storage and delivery of data packets through a router component, and its performance directly affects the delay, throughput and power consumption of the entire slice component.

[0003] In high-demand scenarios such as multi-core servers, communication delay is extremely sensitive. In the prior art, a valid-ready flow control scheme is usually used. The downstream storage buffer needs to consider both overflow and flow interruption, so a FIFO (First Input First Output) with a large depth is required. This scheme occupies a large area on the chip and is not suitable for network-on-chip routing scenarios. SUMMARY

[0004] Therefore, the embodiments of the present application provide at least a data transmission method and device of a network-on-chip, a slice component and a storage medium.

[0005] The technical scheme of the embodiments of the present application is as follows:

[0006] In one aspect, the embodiments of the present application provide a data transmission method of a network-on-chip, applied to a slice component of the network-on-chip, the slice component being connected between two routing nodes in the network-on-chip, the slice component being provided with corresponding output registers and backup registers in a plurality of different output directions, and the method comprising:

[0007] In the case of receiving a data packet from an upstream routing node, the target output direction of the data packet is confirmed;

[0008] According to the storage state of the target output register and the target backup register corresponding to the target output direction, the data packet is written into the target output register or the target backup register, or a retransmission signal for the data packet is sent to the upstream routing node;

[0009] The data packet is sent to a downstream routing node through the target output register or the target backup register, and the data packet is temporarily stored in the target backup register or the target output register before the downstream routing node confirms the reception of the data packet;

[0010] In case a retransmission signal for the data packet sent by the downstream routing node is received, the data packet is sent from the target output register or the target backup register to the downstream routing node.

[0011] In another aspect, an embodiment of the present application provides a data transmission device of a network-on-chip, applied to a slice component of the network-on-chip, the slice component being connected between two routing nodes in the network-on-chip, the slice component being provided with corresponding output registers and backup registers in a plurality of different output directions, and the device comprising:

[0012] a processing module configured to, in case a data packet is received from an upstream routing node, confirm a target output direction of the data packet;

[0013] a read-write module configured to, according to a storage state of a target output register and a target backup register corresponding to the target output direction, write the data packet into the target output register or the target backup register, or send a retransmission signal for the data packet to the upstream routing node; send the data packet to a downstream routing node through the target output register or the target backup register, and temporarily store the data packet in the target backup register or the target output register before confirming that the downstream routing node receives the data packet;

[0014] a transmission module configured to, in case a retransmission signal for the data packet sent by the downstream routing node is received, send the data packet from the target output register or the target backup register to the downstream routing node.

[0015] In still another aspect, an embodiment of the present application provides a slice component connected between two routing nodes in a network-on-chip, the slice component comprising: a processor, and output registers and backup registers corresponding to a plurality of different output directions; the processor being configured to perform part or all steps of the data transmission method of the network-on-chip.

[0016] In yet another aspect, an embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement part or all steps of the data transmission method of the network-on-chip.

[0017] In still another aspect, an embodiment of the present application provides a computer program comprising computer readable code, when the computer readable code is run in a slice component, a processor in the slice component performs part or all steps for implementing the data transmission method of the network-on-chip.

[0018] The embodiment of the present application coordinates the data communication between the routing nodes by using the slice component connected between the routing nodes, and the backup flow control is realized by the slice component through dynamically managing the output register and the backup register, that is, the data backup and retransmission process are cooperatively performed by using the output register and the backup register before the datagram is successfully received by the downstream routing node, since the datagram sends a retransmission signal to the upstream routing node when the register of the slice component cannot write data, so that the upstream routing node attempts to write the register of the slice component again at a subsequent time point instead of directly writing the register of the slice component, thereby avoiding the overflow phenomenon caused by forcibly writing the datagram when the register of the slice component cannot write data, and since the slice component repeatedly issues the datagram backed up in the register to the downstream routing node based on the retransmission signal of the downstream routing node, thereby avoiding the flow interruption phenomenon caused by the fact that the register of the slice component or the downstream routing node cannot receive the datagram, and the efficient flow control is realized by only two registers, thereby reducing the area and timing overhead of the slice component.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the technical solutions of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the technical solutions of the present application.

[0021] Figure 1 An implementation flowchart of a data transmission method of a network-on-chip provided by the embodiment of the present application is shown in the figure;

[0022] Figure 2 A component structure diagram of a slice component provided by the embodiment of the present application is shown in the figure;

[0023] Figure 3 A principle diagram of a data transmission method of a network-on-chip provided by the embodiment of the present application is shown in the figure;

[0024] Figure 4 A transmission diagram of a data transmission method of a network-on-chip provided by the embodiment of the present application is shown in the figure;

[0025] Figure 5 A component structure diagram of a data transmission device of a network-on-chip provided by the embodiment of the present application is shown in the figure;

[0026] Figure 6 A hardware entity diagram of a slice component provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0027] In order to make the purposes, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limitations of the present application. All other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0028] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0029] The terms "first / second / third" involved are only to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the present application and are not intended to limit the present application.

[0031] The embodiments of the present application provide a data transmission method of a network on chip, which is applied to a slice component of the network on chip, the slice component is connected between two routing nodes in the network on chip, and the slice component is provided with corresponding output registers and backup registers in a plurality of different output directions. Figure 1 An implementation flowchart of the data transmission method of the network on chip provided by the embodiments of the present application is shown in FIG. 1, and the method comprises the following steps. Figure 1

[0032] Step 101, in the case of receiving a data packet from an upstream routing node, confirming a target output direction of the data packet.

[0033] ​In the embodiments of the present application, the network-on-chip (NoC) is a new communication method of the system-on-chip (SoC), as a main component of the multi-core technology, the concurrent communication is realized through the distributed routing nodes and the time-division multiplexing link, and the traditional bus architecture is replaced to solve the problems of scalability and performance bottleneck. The slice component is a hardware device arranged between the routing nodes in the system-on-chip (SoC), which has at least the functions of data processing, data transmission and data storage. The upstream routing node is a router component in the network-on-chip located in the data flow starting direction, which is responsible for transmitting the data packet to the adjacent component. The data packet is a unit of information transmitted in the network-on-chip, which contains routing information and a payload. The target output direction is the transmission path direction calculated by the data packet according to the routing algorithm, for example, the east, west, south or north direction (see Figure 2 , wherein the upper side direction is north, the lower side direction is south, the left side direction is west, and the right side direction is east), which is used to determine the output port of the packet in the routing component.

[0034] It is worth noting that the slice component in the embodiments of the present application is connected between two routing nodes, for example Figure 2 , if the sender of the data packet is routing node one 1, then routing node one 1 is the upstream routing node, and at this time the receiver of the data packet is routing node two 2, then routing node two 2 is the downstream routing node; conversely, if the sender of the data packet is routing node two 2, then routing node one 1 is the upstream routing node, and at this time the receiver of the data packet is routing node one 1, then routing node one 1 is the downstream routing node. That is, the upstream routing node and the downstream routing node are not specific to a certain fixed routing node, but are relative to the data transmission direction, that is, the meaning of the upstream routing node is the routing node that sends the data packet to the slice component, and the meaning of the downstream routing node is the routing node that needs to send the data packet to the slice component.

[0035] After the slice component receives the data packet from the upstream routing node, it first parses the routing information of the packet to determine its target output direction. The slice component analyzes the direction identifier in the packet header according to the pre-defined routing algorithm through the built-in routing calculation module, so as to confirm the specific direction of the packet to be transmitted. This process ensures that the packet can be transmitted in the network-on-chip according to the correct path, avoiding transmission delay or error caused by direction error.

[0036] For example, after the slice component receives the data packet from the north, the routing information in the data packet can be extracted and parsed, that is, the target output direction of the data packet is obtained as the east. The routing information is calculated in the upstream routing node and carried in the data packet, and the output direction of the data packet is not calculated at the slice component.

[0037] Step 102, according to the storage state of the target output register and the target backup register corresponding to the target output direction, write the data packet into the target output register or the target backup register, or send a retransmission signal for the data packet to the upstream routing node.

[0038] In the embodiments of the present application, the target output register is a hardware register in the slice component for temporarily storing data packets, located in a specific output direction, responsible for sending the packet to the downstream routing node. Considering that the slice component is arranged between routing nodes, the slice component can transmit data in two directions on the same coordinate axis, that is, from west / east to east / west, or from south / north to north / south, so the output register in the slice component can be provided with two, for example, if the two routing nodes are on the x-axis, the positional relationship of the two routing nodes will be west and east, then the slice component will be provided with an output register in the west direction and an output register in the east direction, if the two routing nodes are on the y-axis, the positional relationship of the two routing nodes will be south and north, then the slice component will be provided with an output register in the south direction and an output register in the north direction.

[0039] The target backup register is a hardware register in the slice component for backing up data packets, located in the same output direction, used to store a copy of the packet to prevent data loss when the output register cannot send normally. The backup register and the output register are the same, since they are both corresponding to the output direction, so the slice component will be provided with backup registers corresponding to the two directions of east and west, or backup registers corresponding to the two directions of north and south.

[0040] The slice component can determine whether the target output register and the target backup register into which the data packet can enter are empty, if one of them is empty, the data packet can be placed into the target output register or the target backup register, if both are empty, the data packet is preferentially placed into the target output register, of course, if both are not empty, it indicates that the slice component cannot temporarily buffer the data packet, but in order to ensure that data is not interrupted, the slice component will send a retransmission signal for the data packet to the upstream routing node, after the upstream routing node receives the retransmission signal, it will continue to resend the data packet to the slice component at the next time node, if the slice component still cannot receive it will continue to send the retransmission signal, until the slice component successfully receives the data packet, so as to ensure that the data packet sent by the upstream routing node can be successfully transmitted.

[0041] Step 103, send the data packet to the downstream routing node through the target output register or the target backup register, and temporarily store the data packet in the target backup register or the target output register before confirming that the downstream routing node receives the data packet.

[0042] In the embodiments of the present application, the downstream routing node is a router component in the on-chip network located in the direction of the termination of the data stream, responsible for receiving data packets from the upstream component. The target output register is a hardware register in the slice component used for temporarily storing and sending data packets. The target backup register is a hardware register in the slice component used for backing up data packets, ensuring that it can be retransmitted in the event of a transmission failure.

[0043] The slice component sends data packets to the downstream routing node through the target output register or the target backup register, while storing a copy of the packet in the target output register or the target backup register. The transmission process is managed by the timing control module to ensure that the packet is transmitted within the clock cycle. If the target output register or the target backup register is transmitting a packet, the slice component will store the data packet in the target output register or the target backup register before confirming that the downstream routing node has successfully received the data packet, in order to prevent data loss if the downstream node cannot receive. The register in which the data packet is temporarily stored here depends mainly on which of the target backup register and the target output register is empty. If both registers are empty, the target backup register is preferred. If only one of the two registers is empty, the empty register is used. This mechanism ensures the continuity and reliability of packet transmission, avoiding data interruption due to downstream congestion.

[0044] Step 104, in the case of receiving a retransmission signal sent by the downstream routing node for the data packet, sending the data packet from the target output register or the target backup register to the downstream routing node.

[0045] In the embodiments of the present application, the retransmission signal sent by the slice component is used to instruct the upstream routing node to retransmit the data packet that was not successfully received to the slice component. The target output register is a hardware register in the slice component used for sending data packets. The target backup register is a hardware register in the slice component used for backing up data packets.

[0046] Upon receiving the retransmission signal sent by the downstream routing node, the slice component immediately retrieves the corresponding data packet from the target output register or the target backup register and retransmits it to the downstream routing node. The retransmission process is controlled by the signal processing module, which parses the content of the retransmission signal to determine the packet that needs to be retransmitted and extracts the data from the register. If the packet is stored in the backup register, the slice component preferentially uses the backup data for transmission; if it is stored in the output register, the slice component directly retransmits it. This step ensures that data packets can be reliably retransmitted in the event of transmission errors or downstream congestion, avoiding data loss.

[0047] The embodiment of the present application coordinates data communication between routing nodes by using a slice component connected between the routing nodes. The slice component implements backup flow control by dynamically managing an output register and a backup register. Before a data packet is successfully received by a downstream routing node, the output register and the backup register are used to cooperatively perform data backup and retransmission processes. When a data packet cannot be written into a register of the slice component, a retransmission signal is sent to an upstream routing node, so that the upstream routing node attempts to write the data packet into the register of the slice component at a subsequent time point instead of directly writing the data packet into the register of the slice component. Therefore, overflow caused by forcibly writing the data packet into the register of the slice component when the register cannot be written into is avoided. In addition, the slice component repeatedly sends the data packet stored in the register to a downstream routing node based on a retransmission signal of the downstream routing node. Therefore, flow interruption caused by the register of the slice component or the downstream routing node being unable to receive the data packet is avoided. Only two registers are needed to implement efficient flow control, and the area and timing overhead of the slice component are reduced.

[0048] Optionally, the step 102 comprises:

[0049] In step 1021, if the target output register or the target backup register meets the write condition, the data packet is written into the target output register or the target backup register meeting the write condition.

[0050] In the embodiment of the present application, the write condition is a logical rule for the slice component to determine whether the data packet is allowed to be written into the register, including register state checking, for example, checking whether the register is empty or can receive new data.

[0051] After confirming the target output direction of the data packet, the slice component checks the state of the target output register and the target backup register corresponding to the direction. The slice component evaluates whether the register meets the write condition through a state detection module. The write condition is, for example, that the output register is empty, or the backup register is empty and the output register is not empty but the data packet written into the output register at the previous time node can be discarded. If the condition is met, the slice component writes the data packet into the empty output register or the backup register. If both the output register and the backup register are empty, the output register is written into first, so that the packet is not lost or blocked due to the full register during transmission. This step optimizes data flow control by dynamically managing the register resource.

[0052] In step 1022, if neither the target output register nor the target backup register meets the write condition, a retransmission signal for the data packet is sent to the upstream routing node.

[0053] In the embodiments of the present application, if the target backup register and the target output register of the target transmission direction do not meet the write-in condition, it indicates that the slice component cannot process the data packet at the current time point temporarily. In order to make the data packet be sent out through the slice component at the subsequent time point and ensure continuous data transmission, the slice component sends a retransmission signal of the data packet to the upstream routing node sending the data packet. After receiving the retransmission signal, the upstream routing node re-sends the data packet to the slice component at the next time node until the slice component successfully receives the data packet, that is, the target output register or the target backup register meets the write-in condition, and the slice component does not send the retransmission signal to the upstream routing node.

[0054] Optionally, the step 1021 comprises:

[0055] Step 10211, in the case that the target output register corresponding to the target output direction is empty, the data packet is written into the target output register.

[0056] In the embodiments of the present application, the slice component first detects the states of the target output register and the target backup register corresponding to the target output direction. If both registers are in the empty state, the slice component directly writes the data packet into the target output register. After the write-in is completed, the target output register immediately enters the non-empty state and is ready to transmit the data packet to the downstream routing node. For example, when the data packet is received from the west direction, the target backup register and the target output register corresponding to the east direction are detected, and then the data packet is written into the target output register and the target backup register which are not empty. If both of them are not empty, the data packet is preferentially written into the target output register corresponding to the east direction. This process ensures that the data packet quickly enters the transmission channel without any blocking condition, and avoids the delay caused by the register occupation.

[0057] Step 10212, in the case that the target output register corresponding to the target output direction is not empty and the target backup register is empty, the data packet is written into the target backup register.

[0058] In the embodiments of the present application, the target output register not being empty indicates that the register is currently storing or transmitting the data packet and cannot immediately receive new data. The target backup register being empty indicates that the register does not store any backup data and can be used as a temporary storage unit to receive new packets, thereby ensuring the continuity of data transmission.

[0059] When the slice component detects that the target output register is not empty and the target backup register is empty, the data packet is written into the target backup register. After the write operation is completed, the target backup register records the content of the packet, and the slice component maintains the current transmission state of the target output register. This mechanism allows the data packet to be temporarily stored in the backup unit when the output register is busy, and the transmission is activated through the subsequent process when the output register is idle, avoiding the interruption of data flow.

[0060] At step 10213, when the target output register corresponding to the target output direction and the target backup register are both not empty, and the retransmission signal corresponding to the target output register is empty, the data packet is written into the target output register at the next time node.

[0061] In the embodiments of the present application, the target output register and the target backup register both not empty means that both registers store data packets and are in active transmission or backup state. The retransmission signal is an indication signal returned by the downstream routing node, and its state empty means that there is currently no data packet to be retransmitted, and the data in the target output register will be successfully received or discarded, releasing the storage space.

[0062] The slice component detects that the target output register and the target backup register are both not empty, and the retransmission signal corresponding to the target output register is empty. The slice component determines that the data packet in the target output register will be processed by the downstream routing node at the next time node, and the register will become idle state. Therefore, the slice component schedules the data packet to be written into the target output register at the next time node. This operation predicts the change of the register state, arranges the data transmission in advance, and optimizes the resource utilization.

[0063] The embodiments of the present application dynamically detect the states of the target output register and the target backup register, preferentially write the received data packet into the empty output register, and write it into the empty backup register when the output register is not empty, so as to ensure that the data packet can be written into the empty register, avoid the overflow problem of repeated writing of data packets, and if the output register and the backup register are both not empty, send the retransmission signal to the upstream routing node, avoiding the flow interruption phenomenon caused by the fact that the slice component cannot receive data.

[0064] Optionally, the step 1022 comprises: in the case that the target output register and the backup register are both not empty, and the retransmission signal corresponding to the target output register is not empty, sending the retransmission signal for the data packet to the upstream routing node.

[0065] In the embodiments of the present application, the retransmission signal is an electronic signal sent by the downstream routing node to the slice component, indicating that the data packet is not successfully received and needs to be retransmitted. The upstream routing node is the network-on-chip node where the data packet originates from, responsible for generating and initially sending the data packet. The data packet is a data unit transmitted in the network-on-chip, containing routing information and a payload.

[0066] The slice component first checks whether the target output register and the backup register in the slice component are both empty, which indicates that the target output register stores the current data packet to be sent, and the backup register stores a backup copy of the data packet. At the same time, the slice component detects whether the retransmission signal corresponding to the target output register is empty, which indicates that the downstream routing node has sent a retransmission signal indicating that the data packet is not successfully received. After meeting these conditions, the slice component generates and sends a retransmission signal for the data packet to the upstream routing node. This signal informs the upstream routing node to resend the data packet, ensuring that the data transmission will not be interrupted, and using the copy in the backup register as a recovery mechanism to avoid data loss or repeated processing.

[0067] The embodiments of the present application ensure continuous and reliable transmission of data packets in the network-on-chip by dynamically handling the reception failure of the downstream routing node during data transmission.

[0068] Optionally, the method further comprises: in the case where the next time node does not receive the retransmission signal sent by the downstream routing node for the data packet, confirming that the downstream routing node receives the data packet, and discarding the data packet in the target backup register or the target output register.

[0069] In the embodiments of the present application, the downstream routing node is a router component downstream of the data flow in the network-on-chip, responsible for receiving and processing data packets from the upstream. The discarding operation refers to the slice component removing the data packet from the register, releasing the storage space for subsequent data.

[0070] The slice component first monitors the signal input from the downstream routing node. If the downstream routing node successfully receives the data packet, the slice component will not receive the retransmission signal; on the contrary, if the data packet transmission fails, the downstream routing node will generate and send the retransmission signal. The slice component determines the transmission result of the data packet by analyzing the signal state, and does not receive the retransmission signal, indicating that the data packet has been correctly received by the downstream, and does not need further processing. This step ensures that the slice component can respond to the feedback from the downstream in time, avoiding unnecessary retransmission operations.

[0071] The slice component performs a discard operation after confirming that the retransmission signal is not received. Specifically, the slice component accesses the storage area of the target backup register or the target output register, identifies and deletes the data message stored therein. This process is implemented by a hardware logic circuit, ensuring that the data message is completely cleared, while updating the status flag of the register to reflect the idle state. After the discard operation is completed, the slice component can immediately receive a new data message, maintaining the continuity of the data stream and preventing invalid occupation of register resources.

[0072] The embodiments of the present application ensure that the register resources are optimally utilized by detecting the retransmission signal and discarding the successfully transmitted data message accordingly, thereby avoiding data overflow and flow interruption.

[0073] Optionally, the step 103 comprises:

[0074] Step 1031, in the case where the data message is stored in the target output register and the target backup register is empty, copying the data message from the target output register to the target backup register.

[0075] In the embodiments of the present application, the slice component first checks whether the data message is stored in the target output register and detects whether the target backup register is empty. If the target backup register is empty, the slice component performs a copy operation to copy the data message from the target output register to the target backup register. This operation is performed while the data message is being sent from the target output register to the downstream routing node, ensuring that the message is backed up during transmission, thereby providing data support for subsequent possible retransmission requests. The slice component controls the copy process through hardware logic, ensuring data consistency and timing synchronization, and avoiding the introduction of additional delay during the backup process.

[0076] Step 1032, in the case where the data message is stored in the target output register and the target backup register is not empty, temporarily storing the data message in the target output register.

[0077] In the embodiments of the present application, the slice component detects that the data message is stored in the target output register, while the target backup register is not empty. The slice component retains the data message in the target output register without performing a copy operation. This temporary storage process ensures that the existing message in the target backup register is not overwritten, while the message in the target output register continues to wait to be sent to the downstream routing node. The slice component manages the state of the register through hardware arbitration logic, ensuring that the data message is not incorrectly copied when the target backup register is not empty, thereby maintaining the integrity of the flow control mechanism.

[0078] Step 1033, in the case where the data message is stored in the target backup register, temporarily storing the data message in the target backup register.

[0079] In the embodiments of the present application, the target backup register is a hardware register in the high-performance slice routing component for backing up data packets, located in the data output direction. When a data packet is stored therein, the slice component can use it for retransmission to cope with the reception failure of the downstream routing node. Staging means that the slice component keeps the data packet in the target backup register without immediate sending, waiting for an external signal to trigger the subsequent operation.

[0080] After the slice component detects that the data packet has been stored in the target backup register, the slice component continues to keep the data packet in the target backup register without performing the staging or sending operation. This staging process allows the slice component to directly retransmit the packet from the target backup register when receiving the retransmission signal of the downstream routing node. The slice component monitors the state of the target backup register through the hardware control logic to ensure the availability of the packet during the staging, thereby supporting the retransmission function in the flow control mechanism and avoiding the transmission interruption caused by the loss of the packet.

[0081] The embodiments of the present application prevent packet overflow and flow interruption by ensuring the dynamic staging and staging of the data packet between the target output register and the target backup register, while supporting the retransmission operation to cope with the reception failure of the downstream routing node.

[0082] Optionally, the method further comprises:

[0083] In step 201, the number of retransmissions of the target backup register is counted by a counting register.

[0084] In the embodiments of the present application, the counting register is a hardware register for storing and updating a value, which is specially used to record the number of retransmissions of the data packet in the target backup register in this step. The target backup register is a storage unit in the slice component for temporarily storing a copy of the data packet, which functions to keep the data packet for retransmission when the downstream routing node fails to successfully receive the data packet. The number of retransmissions refers to the cumulative number of times that the data packet stored in the target backup register is retransmitted to the downstream routing node.

[0085] The slice component counts the number of retransmissions of the data packet in the target backup register by the counting register. The counting register automatically increments the value stored therein each time the data packet in the target backup register is retransmitted. The slice component continuously monitors the retransmission process to ensure that the counting register accurately records the number of retransmissions, thereby providing a data basis for subsequent judgment of whether to trigger the anti-live-lock mechanism.

[0086] Step 202, in the case where the number of retransmissions of the target backup register exceeds the number threshold, a marking signal is sent to the downstream routing node, and the marking signal is used to instruct the downstream routing node to reject receiving other data packets before successfully receiving the data packet in the target backup register.

[0087] In the embodiment of the present application, the number threshold is a preset numerical limit for determining whether the number of retransmissions is too high to trigger the anti-live lock mechanism. The marking signal is a control signal generated by the slice component to inform the downstream routing node to temporarily suspend receiving other data packets under certain conditions. The downstream routing node is the next processor in the data packet transmission path, responsible for receiving and forwarding data packets. The data packet is the basic unit of information transmission, containing routing information and payload.

[0088] If the downstream routing node has no space to receive the data packet in the backup register for a long time, the downstream routing node will send a retransmission signal to the backup register multiple times, and the backup register will also retransmit the data packet to the downstream routing node multiple times. At this time, the number of retransmissions counted by the counting register may exceed the preset number threshold. If the number of retransmissions exceeds the predicted number, the slice component will automatically generate a marking signal and send it to the downstream routing node. After receiving the marking signal, the output register of the downstream routing node considers itself to be marked. After the output register of the downstream routing node writes the data packet written before, if it receives a sending application of other data packets except the data packet of the backup register, it will not be written. The downstream routing node will send a retransmission signal to the slice component until the data packet of the backup register of the slice component is written into the output register of the downstream routing node, and the output register of the downstream routing node will be unlocked. That is, after receiving the marking signal, the downstream routing node adjusts its receiving logic to prioritize processing the retransmission packet of the target backup register, ensuring that the packet is not preempted by other packets. The slice component prevents the live lock phenomenon through this mechanism to ensure smooth transmission of data packets.

[0089] The embodiment of the present application automatically detects and processes the retransmission over-limit problem of the target backup register, ensures that the downstream routing node receives the key packet first, and avoids transmission stagnation due to resource competition. This improves the data transmission reliability and efficiency of the network on chip, reduces the occupation of hardware resources, and optimizes the overall performance of the slice component.

[0090] Optionally, the method further comprises:

[0091] Step 301, adding a number to the sent data packet.

[0092] In the embodiment of the present application, the number is a unique sequence identifier assigned by the slice component to each data packet, used to distinguish different packets and support sequence tracking.

[0093] The slice component automatically generates and appends an incremental or unique number to the message header when the data message enters the sending queue. For example, if there are two data messages, they can be numbered 0 and 1, respectively. The number is based on a hardware counter or sequence generator, which ensures that each message has an independent identifier. The slice component stores the number in association with the message metadata (such as routing direction, priority), and keeps the number unchanged during transmission to support identification and processing by downstream nodes.

[0094] At step 302, when the data messages that need to be sent have been sent, the buffered data messages are sent to the downstream routing node in the order of the numbers, wherein the numbers are used for de-duplication processing of the data messages to be sent by the downstream routing node.

[0095] In the embodiments of the present application, polling refers to the slice component cyclically checking and sending the data messages in the buffer queue in a fixed order. The downstream routing node is the adjacent routing node or processor that receives the message. De-duplication processing is the identification and discarding of duplicate received messages by the downstream node to maintain data consistency.

[0096] The slice component continuously monitors the sending queue state and automatically switches to the buffered message sending mode when it detects that all new data messages have been sent. The slice component reads the messages from the buffer area (such as output registers or backup registers) in order of the numbers from small to large, and transmits them to the downstream routing node through an arbitrator. After receiving the message, the downstream routing node parses its number and compares it with the local record: if the number already exists, the message is discarded; if it is a new number, it is stored and processed. This process is implemented through a hardware comparator and a state register to ensure uninterrupted transmission and data integrity. It is worth noting that the numbering process of the data messages is continuous, while the polling and re-sending mechanism is triggered only when there are no data messages to be sent by the slice component, i.e., during low traffic. If there are continuous new data messages to be sent, the already sent data messages will not be re-sent.

[0097] For example, if the slice component has successfully sent two data messages with numbers 0 and 1, respectively, when polling and sending, the numbers of the data messages received by the downstream routing node will be 0, 1, 0, 1,... If there is only one data message with number 1, the numbers of the data messages received by the downstream routing node will be 1, 1, 1, 1,...

[0098] The embodiments of the present application ensure the orderliness and traceability of the messages through the numbering mechanism. The polling and sending combined with de-duplication processing eliminates the head blocking and repeated transmission problems, thereby improving the parallel communication efficiency of the network-on-chip, reducing the latency, and adapting to various topologies with minimal hardware resources.

[0099] Referring to Figure 2 The input data packet from west to east received by the upstream routing node will be sent out by the output register-E10 of the slice component to the downstream routing node. The data packet in the output register-E10 will be written into the backup register-E20 of the slice component for backup at the same time. When the output register-E10 is not empty, the data packet will be written into the backup register-E20. Then the output register-E10 or the backup register-E20 with the written data packet sends the data packet to the downstream routing node. If the downstream routing node cannot receive the data packet, it will return a retransmission signal (retrans) to the slice component in the next beat. If the slice component receives the retransmission signal from the downstream routing node, it will send the data packet in the backup register-E20 or the output register-E10 to the downstream routing node again.

[0100] The data packet has been routed in the upstream routing node and the routing calculation result (Compute_result) is obtained. The direction of the data packet to be transmitted can be determined by the routing calculation result, and then the data packet is transmitted into the slice component. The routing calculation result will not be changed in the slice component, but will be cached in the register of the router and sent out to the slice component.

[0101] The data packet from west to east will try to write into the output register-E10 of the slice component, and then be sent out to the downstream routing node through the output register-E10. The data packet in the output register-E10 will be written into the backup register-E20 of the slice component for backup at the same time. When the output register-E10 is not empty, the data packet will be written into the backup register-E20. Then the output register-E10 or the backup register-E20 with the written data packet sends the data packet to the downstream routing node. If the downstream routing node cannot receive the data packet, it will return a retransmission signal (retrans) to the slice component in the next beat. If the slice component receives the retransmission signal from the downstream routing node, it will send the data packet in the backup register-E20 or the output register-E10 to the downstream routing node again.

[0102] In this way, the data packet to be transmitted can be continuously sent to the downstream routing node without interruption, and the data packet can be written in the first time as soon as the output register of the corresponding direction of the slice component is empty. At the same time, through this flow control method, only two registers are needed to be instantiated as the output register and the backup register in the slice component, which can effectively reduce the hardware area of the slice.

[0103] Referring to Figure 3 The output transmission process of the slice component at three time nodes is exemplarily shown.

[0104] At cycle0, there is no data packet in the backup register (Backup_E) of the slice component, so the data packet A (Txlfitv_A) is discharged from the eastward output register (Output_reg_E) of the slice component and transmitted to the downstream routing node, and at the same time, the data packet A is put into the backup register of the slice component.

[0105] At cycle1, there is a data packet A in the backup register of the slice component, so the data packet B (Txlfitv_B) is input from the west of the slice component and written into the eastward output register of the slice component, at this time, the slice component sends the data packet B to the downstream routing node from the eastward output register, and the data packet B in the output register will not be discharged (because there is a backup of the data packet A in the backup register); at the same time, if the downstream routing node sends a retransmission signal A (Retrans_A) back to the slice component.

[0106] At cycle2, the data packet A in the backup register is directly sent to the downstream routing node again, at this time, a retransmission signal (Retrans_B) of the data packet B can also be received: if no retransmission signal of the data packet B is received at cycle2, it indicates that the downstream routing has received the data packet B, and the data packet B in the output register is discarded at the next beat (cycle3); if the retransmission signal of the data packet B is received at cycle2, the data packet B is continuously sent at the next beat, and the data packet B will not be discharged from the output register.

[0107] Referring to Figure 3 In the network-on-chip, the slice component provided in the application is used, a plurality of high-performance routing slice components (slices) are inserted between routing nodes with a long physical distance to meet the demand of PPA (power, performance and area). Based on the backup flow control mode, only two registers exist in each slice component single channel, and the data packet can continuously flow through a high-performance slice component every cycle.

[0108] The backup flow control is used between the slice component (slice) and the routing, the packet sent by the upstream router is judged whether it is received according to the retrans signal sent by the downstream slice, if the packet is not received, the packet will be sent again; the downstream slice will identify whether the packet is repeated by the upstream router, and the repeated packet is discarded. The interface between the upstream slice and the downstream routing node is the same.

[0109] Based on the foregoing embodiments, the embodiments of the present application provide a data transmission device of a network on chip, which comprises units and modules included in the units, and can be implemented by a processor in a slice component. Of course, the device can also be implemented by a specific logic circuit. In the implementation process, the processor can be a central processing unit (CPU), a micro processing unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0110] Figure 5 A schematic diagram of a data transmission device of a network on chip is provided in the embodiments of the present application, which is applied to a slice component of a network on chip. The slice component is connected between two routing nodes in the network on chip. The slice component is provided with corresponding output registers and backup registers in a plurality of different output directions, as shown in the figure. The data transmission device 40 of the network on chip comprises: Figure 5

[0111] The processing module 401 is configured to, in the case of receiving a data packet from an upstream routing node, confirm a target output direction of the data packet.

[0112] The read-write module 402 is configured to, according to a storage state of a target output register and a target backup register corresponding to the target output direction, write the data packet into the target output register or the target backup register, or send a retransmission signal for the data packet to the upstream routing node; send the data packet to a downstream routing node through the target output register or the target backup register, and temporarily store the data packet in the target backup register or the target output register before confirming that the downstream routing node receives the data packet.

[0113] The transmission module 403 is configured to, in the case of receiving a retransmission signal sent by the downstream routing node for the data packet, send the data packet from the target output register or the target backup register to the downstream routing node.

[0114] In some embodiments, the read-write module 402 is further configured to:

[0115] In the case that the target output register or the target backup register meets a write condition, write the data packet into the target output register or the target backup register meeting the write condition.

[0116] ​in the case that neither the target output register nor the target backup register meets the write condition, sending a retransmission signal for the data packet to the upstream routing node.

[0117] In some embodiments, the read-write module 402 is further configured to:

[0118] in the case that the target output register corresponding to the target output direction is empty, writing the data packet into the target output register;

[0119] in the case that the target output register corresponding to the target output direction is not empty and the target backup register is empty, writing the data packet into the target backup register;

[0120] in the case that both the target output register and the target backup register corresponding to the target output direction are not empty, and the retransmission signal corresponding to the target output register is empty, writing the data packet into the target output register at a next time node.

[0121] In some embodiments, the read-write module 402 is further configured to:

[0122] in the case that both the target output register and the target backup register are not empty, and the retransmission signal corresponding to the target output register is not empty, sending a retransmission signal for the data packet to the upstream routing node.

[0123] In some embodiments, the transmission module 403 is further configured to:

[0124] in the case that the retransmission signal sent by the downstream routing node for the data packet is not received at a next time node, confirming that the downstream routing node receives the data packet, and discarding the data packet in the target backup register or the target output register.

[0125] In some embodiments, the read-write module 402 is further configured to:

[0126] in the case that the data packet is stored in the target output register and the target backup register is empty, transferring the data packet from the target output register to the target backup register;

[0127] in the case that the data packet is stored in the target output register and the target backup register is not empty, temporarily storing the data packet in the target output register;

[0128] in the case that the data packet is stored in the target backup register, temporarily storing the data packet in the target backup register.

[0129] In some embodiments, the processing module 401 is further configured to:

[0130] count the number of retransmissions of the target backup register by a counting register;

[0131] in a case where the number of retransmissions of the target backup register exceeds a threshold number, send a flag signal to the downstream routing node, the flag signal being used to instruct the downstream routing node to reject receiving other data packets before successfully receiving the data packet in the target backup register.

[0132] In some embodiments, the processing module 401 is further configured to:

[0133] add a number to the transmitted data packet;

[0134] in a case where the data packet to be transmitted has been transmitted, poll the cached data packet to the downstream routing node in the order of the number, wherein the number is used for the downstream routing node to perform a deduplication process on the data packet to be transmitted.

[0135] The embodiments of the present application coordinate the data communication between the routing nodes by using the slice component connected between the routing nodes. The backup flow control is achieved by the slice component dynamically managing the output register and the backup register. That is, the data backup and retransmission process are cooperatively performed by the output register and the backup register before the data packet is successfully received by the downstream routing node. Since the data packet sends a retransmission signal to the upstream routing node when the register of the slice component cannot write data, the upstream routing node attempts to write the data packet in the register of the slice component at a subsequent time point instead of directly writing the data packet in the register of the slice component. Therefore, the overflow phenomenon caused by forcibly writing the data packet in the register of the slice component when the register cannot write data is avoided. Since the slice component repeatedly sends the data packet stored in the register to the downstream routing node based on the retransmission signal of the downstream routing node, the flow interruption phenomenon caused by the register of the slice component or the downstream routing node being unable to receive the data packet is avoided. Efficient flow control is achieved by only two registers, which reduces the area and timing overhead of the slice component.

[0136] The above device embodiments are similar to the above method embodiments in terms of description, and have similar beneficial effects as the method embodiments. In some embodiments, the device provided by the embodiments of the present application has functions or includes modules that can be used to perform the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application.

[0137] It should be noted that, in the embodiments of the present application, if the above-mentioned data transmission method of the network-on-chip is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, which is stored in a storage medium, includes a number of instructions for causing a slice component (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ReadOnly Memory, ROM), a magnetic disk or an optical disk, and various storage media that can store program codes. Thus, the embodiments of the present application are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0138] The embodiments of the present application provide a slice component, which includes a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above-mentioned method when executing the program.

[0139] The embodiments of the present application provide a computer-readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all of the steps of the above-mentioned method. The computer-readable storage medium can be transitory or non-transitory.

[0140] The embodiments of the present application provide a computer program, which includes computer-readable code, and when the computer-readable code runs in a slice component, a processor in the slice component executes the computer-readable code to implement part or all of the steps of the above-mentioned method.

[0141] The embodiments of the present application provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, part or all of the steps of the above-mentioned method are implemented. The computer program product can be implemented by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0142] It should be noted that the above description of the various embodiments tends to emphasize differences between the various embodiments, and the same or similar parts can be referred to each other. The above description of the device, storage medium, computer program and computer program product embodiments is similar to the description of the method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the device, storage medium, computer program and computer program product embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0143] It should be noted that, Figure 6 A hardware entity diagram of a slice component in an embodiment of the present application is shown in FIG. 7, which includes one or more processors 701, a communication interface 702 and a memory 703, wherein: Figure 6

[0144] The processor 701 generally controls the overall operation of the slice component 700.

[0145] The communication interface 702 can enable the slice component to communicate with other terminals or servers through a network.

[0146] The memory 703 is configured to store instructions and applications executable by the processor 701, and can also cache data to be processed by the processor 701 and modules in the slice component 700 (for example, image data, audio data, voice communication data and video communication data) that have been processed or have been processed, which can be implemented by FLASH or RAM. The processor 701, the communication interface 702 and the memory 703 can transmit data through the bus 704. Each processor 701 includes one or more cores.

[0147] ​It should be noted that the slice component can include a plurality of processors 701, and each processor 701 can interact with each other through an aggregated communication mode such as all-to-all, allgather or allreduce. The processor 701 can be a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU), a data processing unit (DPU), an accelerated processing unit (APU), a floating processing unit (FPU), an application-specific integrated circuit (ASIC), or the like. The processor can also be a single-core processor or a multi-core processor. The processor can be a combination of a CPU and a hardware chip. The hardware chip can be an ASIC, a PLD, or a combination thereof. The PLD can be a complex programmable logic device (CPLD), an FPGA, a generic array logic (GAL), or any combination thereof. The processor can also be implemented by a logic device with built-in processing logic, such as an FPGA or a digital signal processor (DSP).

[0148] The communication interface 702 can be a wired interface or a wireless interface, used for communication with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), or the like. The wireless interface can be a cellular network interface or a wireless local area network interface, or the like.

[0149] The memory 703 can be a nonvolatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The memory 703 can also be a volatile memory, which can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synchlink DRAM (SLDRAM), and a direct rambus RAM (DRRAM), a direct rambus DRAM (DRDRAM), and a rambus DRAM.

[0150] The bus 704 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0151] It should be understood that every feature and combination of features that is described above in relation to one embodiment is applicable to at least one other embodiment, unless specifically stated otherwise. It should also be understood that every embodiment described above can be combined with any other embodiment unless specifically stated otherwise.

[0152] It should be noted that, as used in this application, the terms "comprises" or "comprising", or "includes" or "including" or "has" or "having" or "contains" or "containing" or variants thereof, mean "including but not limited to", so as to encompass the non-exclusive inclusion of a process, method, article, or apparatus that comprises an element or a plurality of elements, without excluding or dismissing other elements or a plurality of other elements.

[0153] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined, or can be integrated into another slice component, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interfaces, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0154] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; they can be located in one place or distributed on multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0155] In addition, each functional unit in each embodiment of the present application can be integrated into one processor, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0156] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program performs the method embodiments when executed; and the foregoing storage medium includes a mobile storage device, a read only memory (ROM), a magnetic disc or an optical disc, and various media that can store program codes.

[0157] Alternatively, the integrated units of the present application can be stored in a computer readable storage medium if they are realized in the form of software function modules and sold or used as independent products. Based on this understanding, the technical solutions of the present application or the parts that make contributions to the related art can be embodied in the form of software products, and the computer software products are stored in a storage medium, including a plurality of instructions for causing a slice assembly (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes a mobile storage device, a ROM, a magnetic disc or an optical disc, and various media that can store program codes.

[0158] The above is only an embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application.

Claims

1. A data transmission method of a network-on-chip, characterized by, A slice component applied to a network-on-chip, the slice component being connected between two routing nodes in the network-on-chip, the slice component being provided with corresponding output registers and backup registers in a plurality of different output directions, the method comprising: In a case where a data packet is received from an upstream routing node, confirming a target output direction of the data packet; According to a storage state of a target output register and a target backup register corresponding to the target output direction, writing the data packet into the target output register or the target backup register, or sending a retransmission signal for the data packet to the upstream routing node; Sending the data packet to a downstream routing node through the target output register or the target backup register, and temporarily storing the data packet in the target backup register or the target output register before confirming that the downstream routing node receives the data packet; In a case where a retransmission signal is received from the downstream routing node for the data packet, sending the data packet to the downstream routing node from the target output register or the target backup register.

2. The method of claim 1, wherein, The writing of the data packet into the target output register or the target backup register according to the storage state of the target output register and the target backup register corresponding to the target output direction, or the sending of the retransmission signal for the data packet to the upstream routing node, comprises: In a case where the target output register or the target backup register meets a write-in condition, writing the data packet into the target output register or the target backup register meeting the write-in condition; In a case where neither the target output register nor the target backup register meets the write-in condition, sending the retransmission signal for the data packet to the upstream routing node.

3. The method of claim 2, wherein, The writing of the data packet into the target output register or the target backup register meeting the write-in condition in a case where the target output register or the target backup register meets the write-in condition, comprises: In a case where the target output register corresponding to the target output direction is empty, writing the data packet into the target output register; In a case where the target output register corresponding to the target output direction is not empty and the target backup register is empty, writing the data packet into the target backup register; In a case where the target output register and the target backup register corresponding to the target output direction are both not empty, and the retransmission signal corresponding to the target output register is empty, writing the data packet into the target output register at a next time node.

4. The method of claim 3, wherein, The sending of the retransmission signal for the data packet to the upstream routing node in a case where neither the target output register nor the target backup register meets the write-in condition, comprises: In a case where the target output register and the target backup register are both not empty, and the retransmission signal corresponding to the target output register is not empty, sending the retransmission signal for the data packet to the upstream routing node.

5. The method according to any one of claims 1-4, characterized in that, The confirming of the reception of the data packet by the downstream routing node, comprises: In a case where a retransmission signal sent by the downstream routing node for the data packet is not received at the next time node, it is confirmed that the data packet is received by the downstream routing node, and the data packet in the target backup register or target output register is discarded.

6. The method according to any one of claims 1-4, characterized in that, The data packet is temporarily stored in the target backup register or the target output register, including: In a case where the data packet is stored in the target output register and the target backup register is empty, the data packet is transferred from the target output register to the target backup register; In a case where the data packet is stored in the target output register and the target backup register is not empty, the data packet is temporarily stored in the target output register; In a case where the data packet is stored in the target backup register, the data packet is continuously temporarily stored in the target backup register.

7. The method according to any one of claims 1 to 4, characterized in that, The method further includes: The number of retransmissions of the target backup register is counted by a counting register; In a case where the number of retransmissions of the target backup register exceeds a threshold, a flag signal is sent to the downstream routing node, and the flag signal is used to instruct the downstream routing node to reject to receive other data packets before successfully receiving the data packet in the target backup register.

8. The method according to any one of claims 1-4, characterized in that, The method further includes: A number is added to the sent data packet; In a case where the data packet to be sent has been sent, the cached data packet is polled to the downstream routing node in the order of the number, and the number is used for the downstream routing node to perform a de-duplication process on the data packet to be sent.

9. A data transfer apparatus of a network-on-chip, characterized by, A slice component applied to a network on a chip, the slice component being connected between two routing nodes in the network on a chip, the slice component being provided with corresponding output registers and backup registers in a plurality of different output directions, and the device including: A processing module configured to, in a case where a data packet is received from an upstream routing node, confirm a target output direction of the data packet; A read-write module configured to, according to a storage state of a target output register and a target backup register corresponding to the target output direction, write the data packet into the target output register or the target backup register, or send a retransmission signal for the data packet to the upstream routing node; send the data packet to a downstream routing node through the target output register or the target backup register, and temporarily store the data packet in the target backup register or the target output register before confirming that the data packet is received by the downstream routing node; A transmission module configured to, in a case where a retransmission signal sent by the downstream routing node for the data packet is received, send the data packet to the downstream routing node from the target output register or the target backup register.

10. A slicing assembly characterized by, The slice component is connected between two routing nodes in a network-on-chip, and the slice component comprises a processor, output registers corresponding to different output directions, and backup registers; the processor is configured to execute the steps in the data transmission method of the network-on-chip according to any one of claims 1 to 8.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement the steps in the data transmission method of the network-on-chip according to any one of claims 1 to 8.

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