Test structure and plasma damage test method
By designing experimental and control structures, and increasing the antenna structure to amplify plasma damage, the breakdown characteristics and failure time were tested. This solved the problem of plasma damage risk in three-dimensional devices, optimized the circuit layout, and reduced the damage risk to the process and products.
Patent Information
- Application Number
- CN202511588459.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-01-30
AI Technical Summary
As process nodes shrink, the contact area between three-dimensional device structures and plasma increases, leading to an increased risk of plasma damage. Existing technologies have failed to effectively assess damage to three-dimensional filling media and metals, affecting device reliability.
The experimental and control structures were designed. An antenna structure was added to the experimental structure to amplify plasma damage. By testing the breakdown characteristics and failure time of the structure, reliability risks were identified, and process optimization references were provided.
By comparing the breakdown voltage and lifetime of the experimental and control structures, the damage caused by plasma to three-dimensional filled dielectrics or metals can be identified, circuit layout can be optimized, and the risk of plasma damage to processes and products can be reduced.
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Figure CN121432115A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a test structure and a test method of plasma damage. BACKGROUND
[0002] The plasma damage mainly comes from the deposition (Plasma Chemical Vapor Deposition, PCVD) and dry etching process of the back-end-of-line metal layer. At present, the damage of plasma process to the thin gate oxide has been widely studied in the industry, but the influence of plasma process on the interconnection dielectric is rarely concerned. The main reason is that the mature node interconnection dielectric has high k value, good compactness and strong resistance to plasma damage. The influence on the gate oxide is mainly transmitted to the device through the metal layer step by step.
[0003] However, with the miniaturization of process nodes, the device is transformed from two-dimensional to three-dimensional, and the device gate presents a three-dimensional structure, which increases the contact area with the plasma and increases the damage risk. The complex structure leads to the deviation of ion direction during plasma etching or deposition, and the plasma transits bombardment or charge accumulation in the local area, so that it cannot dissipate anywhere. Moreover, the smaller the process size is, the lower the tolerance of plasma damage is. For example, when the distance between M1 and M0A is only 260A, M0A and substrate AA are easily damaged by M1 and subsequent interconnection process plasma, and the breakdown resistance characteristics also need to be further studied to ensure the stability of the back-end-of-line interconnection. SUMMARY
[0004] The purpose of the present application is to provide a test structure and a test method of plasma damage. By setting an experimental structure and a control structure, the experimental structure is provided with an antenna structure more than the control structure, the plasma damage in the middle / back-end-of-line interconnection process is aggravated and amplified, so as to understand the process window, and then provide a reference for optimizing the circuit layout and reducing the plasma damage of the process and product. In addition, by testing the breakdown characteristics and failure time of the test structure, the breakdown voltage or life of the experimental structure and the control structure is obtained and compared, the damage of plasma to the three-dimensional filling medium or metal is judged, and the reliability risk is identified.
[0005] To solve the above technical problems, the present application provides a test structure, comprising:
[0006] The experimental and control structures each include a substrate, a first M0 metal line, a first via, a first M1 metal line, a second M1 metal line, a third M1 metal line, a fourth M1 metal line, a first pad, a second pad, a third pad, and a fourth pad. The substrate includes an AA region and an STI region. The first M1 metal line covers the first M0 metal line in the AA region. The first M1 metal line is connected to the first pad via a metal stack or via stack to a redistribution layer. The second M1 metal line is connected to the first M0 metal line in the AA region via the first via. The second M1 metal line is connected to the second pad via a metal stack or via stack to a top metal layer. The third M1 metal line covers the first M0 metal line in the STI region. The third M1 metal line skips layers to the redistribution layer via a metal stack or via stack and connects to the third pad. The fourth M1 metal line connects to the first M0 metal line in the STI region via the first via. The fourth M1 metal line skips layers to the top metal layer via a metal stack or via stack and connects to the fourth pad. The experimental structure also includes an antenna structure, which includes a first antenna structure and a second antenna structure. The first M1 metal line in the experimental structure is connected to the first antenna structure via a metal stack or via stack, and the third M1 metal line in the experimental structure is connected to the second antenna structure via a metal stack or via stack.
[0007] Furthermore, both the experimental structure and the control structure further include a fifth M1 metal line, a sixth M1 metal line, a seventh M1 metal line, an eighth M1 metal line, a first diode, a second diode, a third diode, and a fourth diode; the first pad is connected to the first diode via a metal stack or via stack, and the second pad is connected to the second diode via a metal stack or via stack, and the third pad is connected to the third diode via a metal stack or via stack, and the fourth pad is connected to the fourth diode via a metal stack or via stack, and the fourth pad is connected to the fourth diode via a metal stack or via stack, and the fifth pad is connected to the fourth diode via a metal stack or via stack, and the sixth pad is connected to the fourth diode via a metal stack or via stack, and the fifth pad is connected to the fourth diode via a metal stack or via stack, and the sixth pad is connected to the fourth diode via a metal stack or via stack, and the seventh pad is connected to the fourth diode via a metal stack or via stack, and the eighth M1 metal line.
[0008] Furthermore, the antenna structure includes a metal antenna.
[0009] Furthermore, the antenna structure includes a single layer of M1~M top Metal layer.
[0010] Furthermore, the antenna structure includes M1~M top Metal stacking.
[0011] Furthermore, the area of the metal antenna is 0.5 to 5 times the design rule.
[0012] Furthermore, both the experimental structure and the control structure also include a second MO metal line, used to cut the first MO metal line to prevent the instantaneous large current during the breakdown test from flowing down through the AA substrate and causing severe high-temperature burn-out, which would affect the performance of other test structures.
[0013] Furthermore, both the experimental structure and the control structure include a first polycrystalline silicon and a second polycrystalline silicon, wherein the second polycrystalline silicon is used to cut the first polycrystalline silicon.
[0014] To address the aforementioned technical problems, the present invention also provides a method for testing plasma damage using the test structure described above, which may include at least the following steps:
[0015] High voltage V is applied to the first pad and the second pad in the experimental structure and the control structure, respectively. h and low voltage V l To measure the experimental current I test and the reference current I ref ;
[0016] Calculate the experimental current I test and the reference current I ref The current difference rate R, where R = |(I test -I ref ) / I ref x100%;
[0017] Compare the current difference rate R with the reliability standard difference rate R spec Compare, if R <= R spec If R > R, then it is considered to have passed the reliability standard certification; spec If so, it is believed that there is a plasma deterioration problem, and further investigation will be conducted to find the cause of the plasma deterioration.
[0018] To address the aforementioned technical problems, the present invention also provides a method for testing the breakdown voltage using the test structure described above, which may include at least the following steps:
[0019] A ramp high voltage V is applied to the third and fourth pads in the experimental and control structures, respectively. h_ramp and slope low voltage V l_ramp According to the curve changes of current I and voltage V, if the current changes abruptly under a certain voltage condition, then the voltage before the change is the breakdown voltage.
[0020] By comparing the breakdown voltage of the experimental structure and the control structure, the damage of plasma to the three-dimensional filling medium or metal can be determined, and reliability risks can be identified.
[0021] To address the aforementioned technical problems, the present invention also provides a method for testing the lifetime of a test structure as described above, which may include at least the following steps:
[0022] A fixed high voltage V is applied to the third and fourth pads in the experimental and control structures, respectively. h_fix and fixed low voltage V l_fix Based on the curve of current I versus time t, if the current changes abruptly at a certain point in time, record that moment as t. ttf ;
[0023] Multiple sets of t were obtained by applying the same voltage to a large number of samples. ttf The lifetime of the test structure was further obtained through statistical calculations.
[0024] By comparing the lifetimes of the experimental structure and the control structure, the damage caused by plasma to the three-dimensional filling medium or metal can be determined, and reliability risks can be identified.
[0025] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0026] Because the test structure and plasma damage testing method provided by this invention, by setting up an experimental structure and a control structure, with the experimental structure having an additional antenna structure compared to the control structure, amplifies and worsens the plasma damage in the mid / back-end interconnect process to understand the process window, thereby providing a reference for optimizing circuit layout and reducing the ability to reduce plasma damage in processes and products; in addition, by testing the breakdown characteristics and failure time of the test structure, the breakdown voltage or lifetime of the experimental structure and the control structure are obtained and compared to determine the damage of plasma to the three-dimensional filling medium or metal, and to identify reliability risks. Attached Figure Description
[0027] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0028] Figure 1 This is a schematic diagram of the control structure in the test structure of one embodiment of the present invention;
[0029] Figure 2 This is a schematic diagram of the experimental structure in the test structure of one embodiment of the present invention;
[0030] Figure 3 This is a flowchart of a plasma damage testing method in one embodiment of the present invention;
[0031] Figure 4 This is a flowchart of a breakdown voltage testing method according to an embodiment of the present invention;
[0032] Figure 5 This is a flowchart of a lifespan testing method in one embodiment of the present invention.
[0033] in, Figures 1-2 The specific reference numerals in the attached figures are as follows:
[0034] 101-First polysilicon; 102-Second polysilicon; 103-Active region; 104-First M0 metal line; 105-First via; 106-First M1 metal line; 107-Second M1 metal line; 108-Third M1 metal line; 109-Fourth M1 metal line; 110-Second M0 metal line; 111-First pad; 112-Second pad; 113-Third pad; 114-Fourth pad; 115-Fifth M1 metal line; 116-First diode; 117-Sixth M1 metal line; 118-Second diode; 119-Seventh M1 metal line; 120-Third diode; 121-Eighth M1 metal line; 122-Fourth diode; 130-First antenna structure; 131-Second antenna structure.
[0035] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0036] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0037] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the invention can be arbitrarily combined without conflict.
[0038] As described in the background section, with the miniaturization of process nodes, devices are transitioning from two-dimensional to three-dimensional. The device gate exhibits a three-dimensional structure, increasing the contact area with plasma and thus increasing the risk of damage. The complex structure makes it easier for ion orientation to deviate during plasma etching or deposition, leading to excessive plasma bombardment or charge accumulation in localized areas, which then has nowhere to dissipate. Furthermore, the smaller the process size, the lower the tolerance for plasma damage. For example, when the distance between M1 and M0A is only 260 Å, M0A and the substrate AA are easily damaged by plasma from M1 and subsequent interconnect processes, and their breakdown resistance characteristics warrant further investigation to ensure the stability of subsequent interconnects.
[0039] To address the above problems, this invention proposes an improved solution: by setting up an experimental structure and a control structure, the experimental structure having an additional antenna structure compared to the control structure, the plasma damage in the mid / back-end interconnect process is amplified and worsened to understand the process window, thereby providing a reference for optimizing circuit layout and reducing process and product plasma damage. Furthermore, by testing the breakdown characteristics and failure time of the test structure, the breakdown voltage or lifetime of the experimental structure and the control structure is obtained and compared to determine the damage of plasma to the three-dimensional filling medium or metal, and to identify reliability risks.
[0040] The test structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.
[0041] refer to Figures 1-2 As shown, Figure 1 This is a schematic diagram of the control structure in the test structure provided in the embodiments of the present invention. Figure 2 This is a schematic diagram of the experimental structure in the test structure provided in the embodiment of the present invention.
[0042] like Figures 1-2As shown, both the control structure and the experimental structure include a substrate, a first M0 metal line 104, a first via 105, a first M1 metal line 106, a second M1 metal line 107, a third M1 metal line 108, a fourth M1 metal line 109, a first pad 111, a second pad 112, a third pad 113, a fourth pad 114, a fifth M1 metal line 115, a sixth M1 metal line 117, a seventh M1 metal line 119, an eighth M1 metal line 121, a first diode 116, a second diode 118, a third diode 120, a fourth diode 122, a second M0 metal line 110, a first polysilicon 101, and a second polysilicon 102.
[0043] The substrate includes an AA region and an STI region. The first M1 metal line 106 covers the first M0 metal line 104 in the AA region. The first M1 metal line 106 jumps to the redistribution layer via a metal stack or via stack and connects to the first pad 111. The first pad 111 jumps to the fifth M1 metal line 115 via a metal stack or via stack and connects to the first diode 116. The second M1 metal line 107 connects to the first M0 metal line 104 in the AA region via the first via 105. The second M1 metal line 107 jumps to the top metal layer via a metal stack or via stack and connects to the second pad 112. The second pad 112 jumps to the sixth M1 metal line 117 via a metal stack or via stack and connects to the second diode 118. The third M1 metal line 108 covers the first M0 metal line 104 in the STI region. M1 metal line 108 is connected to the third pad 113 via a metal stack or via stack to the redistribution layer. The third pad 113 is connected to the third diode 120 via a metal stack or via stack to the seventh M1 metal line 119. The fourth M1 metal line 109 is connected to the first M0 metal line 104 in the STI region via the first via 105. The fourth M1 metal line 109 is connected to the fourth pad 114 via a metal stack or via stack to the top metal layer. The fourth pad 114 is connected to the fourth diode 122 via a metal stack or via stack to the eighth M1 metal line 121. The second M0 metal line 110 is used to cut the first M0 metal line 104 to prevent the instantaneous high current during breakdown testing from flowing down through the AA substrate and causing severe high-temperature burn-out, which would affect the performance of other test structures. The second polysilicon 102 is used to cut the first polysilicon 101.
[0044] The experimental structure also includes an antenna structure, which includes a first antenna structure 130 and a second antenna structure 131. The first M1 metal line 106 in the experimental structure is connected to the first antenna structure 130 through a metal stack or a through-hole stack, and the third M1 metal line 108 in the experimental structure is connected to the second antenna structure 131 through a metal stack or a through-hole stack.
[0045] The antenna structure can be a metal antenna, or a single-layer antenna M1~M1. top The metal layer can also be M1~M top Metal stacking is permitted, but not limited to. The area of the metal antenna is 0.5 to 5 times the design rule.
[0046] In other embodiments, the present invention also provides a method for testing plasma damage, using the test structure described above, with reference to... Figure 3 As shown, Figure 3 This is a flowchart of a plasma damage testing method provided in an embodiment of the present invention; wherein the plasma damage testing method may include the following steps:
[0047] Step S1: Apply a high voltage V to the first pad and the second pad in the experimental structure and the control structure, respectively. h and low voltage V l To measure the experimental current I test and the reference current I ref ;
[0048] Step S2, calculate the experimental current I test and the reference current I ref The current difference rate R, where R = |(I test -I ref ) / I ref x100%;
[0049] Step S3, compare the current difference rate R with the reliability standard difference rate R spec Compare, if R <= R spec If R > R, then it is considered to have passed the reliability standard certification; spec If so, it is believed that there is a plasma deterioration problem, and further investigation will be conducted to find the cause of the plasma deterioration.
[0050] See Figures 1-2 In step S1 above, a high voltage V is applied to the first pad 111 and the second pad 112 in the experimental structure and the control structure, respectively. h and low voltage V l To measure the experimental current I test and the reference current I ref .
[0051] In step S2 above, the experimental current I is calculated. test and the reference current I ref The current difference rate R, where R = |(I test -I ref ) / I ref x100%.
[0052] In step S3 above, the current difference rate R is compared with the reliability standard difference rate R. spec Compare, if R <= R spec If R > R, then it is considered to have passed the reliability standard certification; spec If so, it is believed that there is a plasma deterioration problem, and further investigation will be conducted to find the cause of the plasma deterioration.
[0053] In other embodiments, the present invention also provides a method for testing breakdown voltage, using the test structure described above, with reference to... Figure 4 As shown, Figure 4 This is a flowchart of a breakdown voltage testing method provided in an embodiment of the present invention; wherein the breakdown voltage testing method may include the following steps:
[0054] Step S10: Apply a ramp high voltage V to the third and fourth pads in the experimental structure and the control structure, respectively. h_ramp and slope low voltage V l_ramp According to the curve changes of current I and voltage V, if the current changes abruptly under a certain voltage condition, then the voltage before the change is the breakdown voltage.
[0055] Step S11: By comparing the breakdown voltage of the experimental structure and the control structure, the damage of plasma to the three-dimensional filling medium or metal is determined, and reliability risks are identified.
[0056] See Figures 1-2 In step S10 above, a ramp high voltage V is applied to the third pad 113 and the fourth pad 114 in the experimental structure and the control structure, respectively. h_ramp and slope low voltage V l_ramp Based on the curve changes of current I and voltage V, if the current changes abruptly under a certain voltage condition, then the voltage one step before the change is the breakdown voltage.
[0057] In step S11 above, by comparing the breakdown voltage of the experimental structure and the control structure, the damage of plasma to the three-dimensional filling medium or metal is determined, and reliability risks are identified.
[0058] In other embodiments, the present invention also provides a method for testing lifetime, using the test structure described above, with reference to...Figure 4 As shown, Figure 4 This is a flowchart of a lifetime testing method provided in an embodiment of the present invention; wherein the lifetime testing method may include the following steps:
[0059] Step S20: Apply a fixed high voltage V to the third and fourth pads in the experimental structure and the control structure, respectively. h_fix and fixed low voltage V l_fix Based on the curve of current I versus time t, if the current changes abruptly at a certain point in time, record that moment as t. ttf ;
[0060] Step S21: After applying the same voltage to a large number of samples, multiple sets of t are obtained. ttf The lifetime of the test structure was further obtained through statistical calculations.
[0061] Step S22: By comparing the lifetime of the experimental structure and the control structure, the damage of plasma to the three-dimensional filling medium or metal is determined, and reliability risks are identified.
[0062] See Figures 1-2 In step S20 above, a fixed high voltage V is applied to the third pad 113 and the fourth pad 114 in the experimental structure and the control structure, respectively. h_fix and fixed low voltage V l_fix Based on the curve of current I versus time t, if the current changes abruptly at a certain point in time, record that moment as t. ttf .
[0063] In step S21 above, multiple sets of t are obtained by applying the same voltage to a large number of samples. ttf The lifetime of the test structure was further obtained through statistical calculations.
[0064] In step S22 above, by comparing the lifetime of the experimental structure and the control structure, the damage of plasma to the three-dimensional filling medium or metal is determined, and reliability risks are identified.
[0065] In summary, the test structure and plasma damage testing method provided by this invention, by setting up an experimental structure and a control structure, with the experimental structure having an additional antenna structure compared to the control structure, amplifies and worsens plasma damage in the mid / back-end interconnect process to understand the process window, thereby providing a reference for optimizing circuit layout and reducing the ability to reduce plasma damage in processes and products; furthermore, by testing the breakdown characteristics and failure time of the test structure, the breakdown voltage or lifetime of the experimental structure and the control structure are obtained and compared to determine the damage of plasma to the three-dimensional filling medium or metal, and to identify reliability risks.
[0066] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
Claims
1. A test structure, characterized by, Comprising: The experimental structure and the control structure each include a substrate, a first M0 metal line, a first via, a first M1 metal line, a second M1 metal line, a third M1 metal line, a fourth M1 metal line, a first pad, a second pad, a third pad, and a fourth pad, the substrate includes an AA region and an STI region, the first M1 metal line covers the first M0 metal line of the AA region, the first M1 metal line is connected to the first pad by metal layer jump or via layer jump to the rewiring layer, the second M1 metal line is connected to the first M0 metal line of the AA region through the first via, the second M1 metal line is connected to the second pad by metal layer jump or via layer jump to the top metal layer, the third M1 metal line covers the first M0 metal line of the STI region, the third M1 metal line is connected to the third pad by metal layer jump or via layer jump to the rewiring layer, the fourth M1 metal line is connected to the first M0 metal line of the STI region through the first via, and the fourth M1 metal line is connected to the fourth pad by metal layer jump or via layer jump to the top metal layer; the experimental structure further includes an antenna structure, the antenna structure includes a first antenna structure and a second antenna structure, the first M1 metal line in the experimental structure is connected to the first antenna structure by metal layer or via layer, and the third M1 metal line in the experimental structure is connected to the second antenna structure by metal layer or via layer.
2. The test structure of claim 1, wherein, The experimental structure and the control structure each further include a fifth M1 metal line, a sixth M1 metal line, a seventh M1 metal line, an eighth M1 metal line, a first diode, a second diode, a third diode, and a fourth diode; the first pad is connected to the first diode by metal layer jump or via layer jump to the fifth M1 metal line, the second pad is connected to the second diode by metal layer jump or via layer jump to the sixth M1 metal line, the third pad is connected to the third diode by metal layer jump or via layer jump to the seventh M1 metal line, and the fourth pad is connected to the fourth diode by metal layer jump or via layer jump to the eighth M1 metal line.
3. The test structure of claim 1, wherein, The antenna structure includes a metal antenna.
4. The test structure of claim 3, wherein, The antenna structure comprises single-layer M1~M top metal layers.
5. The test structure of claim 3, wherein, The antenna structure includes M1~M top metallic stack.
6. The test structure of claim 3, wherein, The area of the metal antenna is 0.5 times to 5 times the design rule.
7. The test structure of claim 1, wherein, The experimental structure and the control structure each further include a second M0 metal line for cutting the first M0 metal line, so as to avoid the flow of large instantaneous current through the AA substrate downward during breakdown test, which causes relatively serious high-temperature burnout and affects the performance of other test structures.
8. The test structure of claim 1, wherein, The experimental structure and the control structure each include a first polysilicon and a second polysilicon, and the second polysilicon is used to cut the first polysilicon.
9. A method of testing plasma damage using a test structure as claimed in any one of claims 1 to 8, characterized in that, Comprising: applying a high voltage V h and a low voltage V l to the first and second pads in the experimental and control structures, respectively, to measure experimental and control currents I test and I ref , respectively; the experimental current I test and the control current I ref , where R = |(I test - I ref ) / I ref x 100%; The current difference rate R is compared with a reliability standard difference rate R spec If R <= R spec , it is considered that the authentication by the reliability standard is passed; if R > R spec , it is considered that there is a plasma deterioration problem, and further search for the plasma deterioration cause is made.
10. A method of testing the breakdown voltage using the test structure according to any one of claims 1 to 8, characterized in that, By comparing the breakdown voltages of the experimental structure and the control structure, the damage of plasma to the three-dimensional filling medium or metal is judged, and the reliability risk is identified. applying a ramp high voltage V on the third pad and the fourth pad in the experimental structure and the control structure, respectively h_ramp and a ramp low voltage V l_ramp According to the curve change of the current I and the voltage V, the current mutation under a certain voltage condition, then the voltage of the previous step is the breakdown voltage; Comprising:
11. A method of testing the lifetime of a test structure as claimed in any one of claims 1 to 8, characterized in that applying a fixed high voltage V on the third and fourth pads in the experimental and control structures, respectively h_fix and a fixed low voltage V l_fix According to the curve of current I and time t, the current suddenly changes at a certain time point, and the time at this moment is recorded as t ttf ; After applying the same voltage to a large number of samples, a plurality of t ttf The lifetime of the test structure is further obtained through statistical calculation. By comparing the lifetimes of the experimental structure and the control structure, the damage of the plasma to the three-dimensional filling medium or metal is judged, and the reliability risk is identified.