Graphics processor and instruction execution method, terminal device, media

Abstract

A graphics processing unit (GPU) and its instruction execution method, terminal device, and medium are disclosed. The GPU includes: an instruction cache coupled to a constant data cache; in response to receiving an instruction queue including a first instruction, identifying the first instruction; and in response to the identification result indicating that the first instruction is a target instruction, sending a constant data request to the constant data cache and dispatching the first instruction to a scheduler; the target instruction includes: a target register, a source register, a constant data cache view, and constant data cache view parameters; the constant data cache is adapted to output the target constant data indicated by the first instruction to the executor after receiving the constant data request; the scheduler is adapted to schedule the first instruction to the executor after receiving the first instruction; and the executor is adapted to execute the first instruction and send the execution result to the target register. This improves the instruction execution efficiency of the GPU.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a graphics processor and instruction execution method, terminal device, and medium. Background Technology

[0002] In the rendering process using a Graphics Processing Unit (GPU), constant data is a special data type used to transfer data between the Central Processing Unit (CPU) and the GPU. This data remains unchanged throughout the rendering cycle and is stored in the GPU's constant data buffer. It is suitable for transferring low-frequency changing parameters as constant data between the CPU and GPU, such as transformation matrices, lighting parameters, and material parameters.

[0003] When accessing constant data, a dedicated instruction is sent to the constant data cache to retrieve the target constant data, which is then sent to the executor. In this method, accessing constant data requires a separate instruction issue port, affecting the issuance of other instructions, increasing instruction execution latency, and reducing the GPU's instruction execution efficiency.

[0004] Therefore, how to improve instruction execution efficiency is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The objective of this invention is at least to provide a graphics processor that can improve the instruction execution efficiency during the rendering process using a GPU.

[0006] In a first aspect, embodiments of the present invention provide a graphics processor, comprising: an instruction cache, a constant data cache, a scheduler, and an executor; the instruction cache, coupled to the constant data cache, in response to receiving an instruction queue including a first instruction, identifies the first instruction; in response to the identification result indicating that the first instruction is a target instruction, sends a constant data request to the constant data cache and issues the first instruction to the scheduler; the target instruction includes: a target register, a source register, a constant data cache view, and constant data cache view parameters; the constant data cache is adapted to output the target constant data indicated by the first instruction to the executor after receiving the constant data request; the scheduler is adapted to schedule the first instruction to the executor after receiving the first instruction; the executor is adapted to execute the first instruction and send the execution result to the target register.

[0007] Optionally, the constant data cache view parameters include the number and offset of the constant data cache view used to store the target constant data.

[0008] Optionally, the offset is an immediate value, and the constant data cache, in response to receiving the constant data request and detecting that the target constant data exists in the constant data cache, outputs the target constant data to the actuator and sends a target constant data ready signal to the actuator.

[0009] Optionally, the offset is a register, and the constant data cache, in response to receiving the constant data request and detecting the existence of the target constant data in the constant data cache according to the register addressing method, outputs the target constant data to the actuator and sends a target constant data ready signal to the actuator.

[0010] Optionally, the graphics processor further includes an L0 cache coupled to the constant data cache, adapted to store constant data; the constant data cache is further configured to: send a constant data request to the L0 cache in response to the absence of the target constant data; acquire and save the target constant data returned by the L0 cache; output the target constant data to the actuator; and send a target constant data ready signal to the actuator.

[0011] Optionally, the actuator is further configured to: lock the first instruction in response to not receiving the target constant data ready signal; execute the next instruction in the instruction queue of the first instruction; and resume execution of the first instruction in response to receiving the target constant data ready signal.

[0012] Secondly, embodiments of the present invention provide a low-latency instruction execution method for acquiring constant data, including:

[0013] An instruction cache retrieves an instruction queue, the instruction queue including a first instruction. The first instruction is identified as a target instruction, a constant data request is sent to a constant data cache, and the first instruction is emitted to the scheduler. Upon receiving the constant data request, the constant data cache outputs the target constant data indicated by the first instruction to the executor. Upon receiving the first instruction, the scheduler schedules the first instruction to the executor. The executor executes the first instruction based on the received target constant data and sends the execution result to the target register. The target instruction includes: a target register, a source register, a constant data cache view, and constant data cache view parameters.

[0014] Optionally, after receiving the constant data request, the constant data cache outputs the target constant data indicated by the first instruction to the executor, including:

[0015] The system checks whether target constant data exists in the constant data cache. If it exists, the target constant data is sent to the executor, and a constant data ready signal is sent to the executor. If it does not exist, the constant data cache sends a constant data request to the L0 cache. In response to the L0 cache returning the target constant data, the system sends the target constant data to the executor, and a constant data ready signal is sent to the executor. The L0 cache is suitable for storing constant data.

[0016] Thirdly, the present invention also provides a terminal device including any of the graphics processors described above.

[0017] Fourthly, the present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, wherein the computer program is executed by a processor to perform the steps of the aforementioned low-latency instruction execution method for obtaining constant data.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0019] This invention improves instruction execution efficiency by modifying the instructions in a graphics processor that require constant data acquisition, adding constant data cache view and constant data cache view parameters to the instructions, thereby reducing the number of instructions required during execution and the number of instruction emission ports required during instruction execution.

[0020] Furthermore, in this embodiment of the invention, the instruction cache and the constant data cache are coupled. After identifying the instruction, the instruction cache sends a constant data request to the constant data cache. Upon receiving the constant data request, the constant data cache can detect whether the target constant data exists. Compared with the prior art, this advances the step of detecting whether the target constant data exists in the constant data cache, reducing the latency of obtaining the target constant data.

[0021] Furthermore, the constant data cache view parameters included in the instructions in this embodiment of the invention include immediate values ​​and registers, that is, the instructions support immediate addressing and register addressing, which improves the applicability of the invention. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a graphics processor in the prior art;

[0023] Figure 2This is a schematic diagram of the structure of a graphics processor according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of another graphics processor in an embodiment of the present invention;

[0025] Figure 4 This is a flowchart of a low-latency instruction execution method for acquiring constant data in an embodiment of the present invention. Detailed Implementation

[0026] As mentioned earlier, low-frequency changing parameters are suitable for being transferred between the CPU and GPU as constant data. These low-frequency changing parameters include transformation matrices, lighting parameters, and material parameters.

[0027] When accessing constant data, a dedicated instruction is sent to the constant data cache to retrieve the target constant data, which is then sent to the executor. In this method, accessing constant data requires a separate instruction issue port, affecting the issuance of other instructions, increasing instruction execution latency, and reducing the GPU's instruction execution efficiency.

[0028] Reference Figure 1 , Figure 1 A schematic diagram of the structure of a graphics processor 10 in the prior art is shown. The graphics processor 10 includes: an instruction cache 11, a scheduler 12, an arithmetic logic unit (ALU) 13, a register file 14, a constant data cache 15, and an L0 cache 16, wherein:

[0029] Instruction cache 11, coupled to scheduler 12, is suitable for storing ALU instructions and constant data load (CLD, ConstantLoad) instructions.

[0030] The ALU instructions include a first source register, a second source register, and a destination register. The CLD instructions include a first source register, a constant data cache view, and constant data cache view parameters, wherein the constant data cache view parameters include the number and offset of the constant data cache view used to store the destination constant data.

[0031] The scheduler 12, coupled to the arithmetic logic unit 13 and the constant data buffer 15, sends the received ALU instructions to the arithmetic logic unit 13 and the received CLD instructions to the constant data buffer 15.

[0032] Constant data cache 15, coupled to register file 14 and L0 cache 16, performs a hit test on the target constant data indicated by the CLD instruction in response to a received CLD instruction. If the target constant data exists in constant data cache 15, the target constant data is sent to register file 14. If the target constant data does not exist in constant data cache 15, a constant data request is sent to L0 cache 16.

[0033] L0 cache 16, in response to receiving a constant data request, retrieves the target constant data and sends it to constant data cache 15.

[0034] Register file 14, coupled to arithmetic logic unit 13, is adapted to store received target constant data and send the target constant data to arithmetic logic unit 13.

[0035] Arithmetic logic unit 13 is adapted to receive ALU instructions and target constant data, and execute the ALU instructions according to the target constant data.

[0036] In existing technology, when a graphics processing unit (GPU) executes ALU instructions that require constant data, it uses a separate CLD instruction to call the target constant data. The CLD instruction occupies a dedicated instruction issue port, affecting the issuance of other instructions and increasing instruction execution latency. Furthermore, the CLD instruction is fetched from instruction cache 11, decoded by instruction cache 11, and sent to scheduler 12. Scheduler 12 then schedules the CLD instruction to constant data cache 15 before performing a hit test on the target constant data in constant data cache 15.

[0037] In summary, existing technologies suffer from long runtime delays and low efficiency in acquiring target constant data.

[0038] In this embodiment of the invention, by modifying the instructions in the graphics processor that require obtaining constant data, the constant data cache view and constant data cache view parameters are added to the instructions. In other words, the instructions used in the prior art to obtain constant data are incorporated into this instruction, which reduces the number of instructions required during execution, reduces the number of instruction emission ports required during instruction execution, and improves instruction execution efficiency.

[0039] Furthermore, in this embodiment of the invention, by coupling the instruction cache and the constant data cache, after the instruction cache identifies the instruction, the instruction cache sends a constant data request to the constant data cache. Upon receiving the constant data request, the constant data cache can detect whether the target constant data exists. This advances the step of detecting the existence of the target constant data in the constant data cache, reducing the latency of obtaining the target constant data.

[0040] Reference Figure 2 The diagram illustrates a schematic of a graphics processor 20 according to an embodiment of the present invention. The graphics processor 20 includes: an instruction cache 21, a constant data cache 22, a scheduler 23, and an executor 24.

[0041] In specific implementation, instruction cache 21 is coupled to constant data cache 22. When an instruction queue is received and the instruction queue includes a first instruction, the first instruction is identified. When the identification result indicates that the first instruction is the target instruction, a constant data request is sent to constant data cache 22, and the first instruction is sent to scheduler 23.

[0042] In some embodiments, the target instruction may include: a target register, a source register, a constant data cache view, and constant data cache view parameters.

[0043] In a specific implementation, the constant data buffer 22 is adapted to output the target constant data indicated by the first instruction to the executor 24 after receiving a constant data request. The scheduler 23 is adapted to schedule the first instruction to the executor 24 after receiving the first instruction. The executor 24 is adapted to execute the first instruction and send the execution result to the target register. The aforementioned target constant data represents the constant data indicated by the first instruction to be used for performing arithmetic and logical operations.

[0044] In a specific implementation, the graphics processor 20 may further include: an instruction compiler, coupled to the instruction cache 21, adapted to generate target instructions according to a preset instruction set.

[0045] Optionally, the instructions generated by the instruction compiler include arithmetic logic instructions, which in turn include target instructions.

[0046] The constant data buffer view parameters include the number and offset of the constant data buffer view (CBV) used to store the target constant data. The number and offset of the constant data buffer view indicate the storage location of the target constant data.

[0047] Furthermore, the instruction compiler assembles the generated instructions into an instruction queue and sends the instruction queue to the instruction cache 21.

[0048] In a non-restrictive example, the constant data cache view parameters include [CBV_id][offset], where CBV_id refers to the number of the constant data cache view and offset refers to the offset of the corresponding CBV.

[0049] The first instruction can be: FADD r5, r8, CBV[0]

[10] . This first instruction means adding the target constant data stored in CBV[0]

[10] to the data in register r8, and storing the result in register r5. Here, FADD indicates that the arithmetic logic operation type of the first instruction is floating-point addition, r5 represents the target register used to store the result of the arithmetic logic operation, r8 represents the source register, and CBV[0]

[10] represents the constant data cache view and constant data cache view parameters.

[0050] Wherein, CBV[0]

[10] represents the offset of 10 bytes between the storage location of the target constant data and CBV[0]. Wherein, CBV[0] represents the starting address of the 0th constant data cache view.

[0051] In some embodiments, the offset is an immediate value. When the constant data cache 22 receives a constant data request and detects that the target constant data exists in the constant data cache 22, it outputs the target constant data to the actuator 24 and sends a target constant data ready signal to the actuator 24. After receiving the constant data request, the constant data cache 22 can perform a hit test according to the target constant data indicated in the first instruction to detect whether the target constant data exists in the constant data cache 22.

[0052] In another non-limiting example, the offset is a register. When the constant data cache 22 receives a constant data request and detects the existence of target constant data in the constant data cache 22 according to the register addressing method, it outputs the target constant data to the executor 24 and sends a target constant data ready signal to the executor 24. Specifically, the constant data cache 22 obtains the specific value of the offset according to the register addressing method and performs a hit test based on the constant data cache view number and the specific offset value to detect whether the target constant data exists in the constant data cache 22. The constant data cache view number and the specific offset value represent the storage location of the target constant data.

[0053] When the offset is an immediate value, this embodiment of the invention modifies the ALU instructions, combining the CLD instructions used in the prior art for calling constant data with the ALU instructions. This reduces the number of instructions, reduces the occupancy of the instruction issue port, and improves instruction execution efficiency.

[0054] In some embodiments, by coupling the constant data cache 22 to the instruction cache 21, the constant data cache 22 can detect the presence of target constant data after the instruction cache 21 identifies the instruction. Compared with the prior art, the step of detecting the presence of target constant data in the constant data cache is advanced, reducing the latency of obtaining the target constant data.

[0055] When the offset is a register, this embodiment of the invention couples the constant data cache 22 with the instruction cache 21, enabling the constant data cache 22 to detect the presence of target constant data after the instruction cache 21 identifies the instruction. Compared with the prior art, the step of detecting the presence of target constant data in the constant data cache is advanced, reducing the latency of obtaining the target constant data.

[0056] In practice, the target constant data may not be stored in the constant data cache 22. That is, when performing a hit or miss test, the target constant data is not hit in the constant data cache.

[0057] In this embodiment of the invention, the image processor may also include an L0 cache 25. (See reference...) Figure 3 , Figure 3 exist Figure 2 Based on this, an L0 cache 25 was added, which is coupled to the constant data cache 22 and is suitable for storing constant data.

[0058] In some specific implementations, when the target constant data is not present in the constant data cache 22, the constant data cache 22 sends a constant data request to the L0 cache 25. The target constant data returned by the L0 cache 25 is retrieved and saved, and then output to the executor 24. Specifically, after receiving the constant data request, the L0 cache 25 performs a hit test based on the target constant data indicated in the request, checking whether the target constant data exists in the L0 cache 25. If the test result indicates that the target constant data exists, it is sent to the constant data cache 22.

[0059] Optionally, if the detection result is that the target constant data does not exist, L0 cache 25 sends a constant data request to the next-level storage unit. This storage unit performs a hit test based on the target constant data indicated by the constant data request to check whether the target constant data is stored in the storage unit. If the detection result is that the target constant data exists, the target constant data is sent to constant data cache 22. If the detection result is that the target constant data does not exist, a constant data request is sent to the next-lower-level storage unit to retrieve the target constant data.

[0060] Optionally, when the target constant data is not present in the constant data cache 22, the constant data cache 22 will not send a target constant data ready signal to the executor 24.

[0061] If the constant data buffer 22 does not receive the target constant data ready signal, it can lock the first instruction and execute the next instruction in the instruction queue that follows the first instruction. When the constant data buffer 22 receives the target constant data ready signal, it resumes execution of the first instruction.

[0062] In some embodiments, when the target constant data is not present in the constant data cache 22, a constant data request needs to be sent to the L0 cache 25. If the target constant data is present in the L0 cache 25, the executor 24 needs to wait for the L0 cache 25 to return the target constant data to the constant data cache 22. The constant data cache 22 then retrieves the target constant data and sends it to the executor 24, allowing the executor 24 to continue executing the first instruction. If the target constant data is not present in the L0 cache 25, it may be necessary to access multiple levels of storage units to obtain the target constant data. In this case, the acquisition time for the target constant data is long and uncontrollable. Therefore, when the target constant data is not present in the constant data cache 22, the executor 24 locks the first instruction, executes the next instruction in the instruction queue, and resumes execution of the first instruction upon receiving the target constant data ready signal. This improves the overall efficiency of the graphics processor 30 in executing instructions.

[0063] Reference Figure 4 This invention also provides a method for low-latency acquisition of constant data through instruction execution, which will be described in detail below through specific steps.

[0064] Step S401: Obtain instruction queue from instruction cache. Instruction queue includes first instruction. Identify first instruction. If first instruction is identified as target instruction, send constant data request to constant data cache and send first instruction to scheduler.

[0065] In step S402, after receiving a constant data request, the constant data cache outputs the target constant data indicated by the first instruction to the executor.

[0066] In step S403, after receiving the first instruction, the scheduler schedules the first instruction to the executor.

[0067] In step S404, the executor executes the first instruction based on the received target constant data and sends the execution result to the target register.

[0068] The target instruction includes: target register, source register, constant data cache view, and constant data cache view parameters.

[0069] Optionally, in a specific implementation of step S403, the constant data cache, upon receiving a constant data request, outputs the target constant data indicated by the first instruction to the executor, including:

[0070] The system checks if the target constant data exists in the constant data cache. If it does, it sends the target constant data to the executor and sends a constant data ready signal to the executor. If it does not exist, the constant data cache sends a constant data request to the L0 cache. After receiving the target constant data returned by the L0 cache, the constant data cache sends the target constant data to the executor and sends a constant data ready signal to the executor. The L0 cache is suitable for storing constant data.

[0071] The low-latency instruction execution method for acquiring constant data described in this embodiment can be derived from the above. Figure 2 The graphics processor 20 or shown in the embodiment Figure 3 The graphics processor 30 described in the illustrated embodiment executes.

[0072] In specific implementation, the specific execution process of steps S401 to S404 can be referred to the relevant content in the above embodiments, and will not be repeated here.

[0073] This invention also provides a terminal device, including the graphics processor provided in any of the above embodiments.

[0074] This invention also provides a computer-readable storage medium, which is a non-volatile or non-transient storage medium, storing a computer program thereon. When the computer program is run by a processor, it executes the steps of the aforementioned low-latency instruction execution method for obtaining constant data.

[0075] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include ROM, RAM, disk, or optical disk, etc.

[0076] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.

Claims

1. A graphics processor, characterized in that, include: Instruction cache, constant data cache, scheduler, executor; The instruction cache, coupled with the constant data cache, responds to receiving an instruction queue that includes a first instruction, identifies the first instruction, and responds to the identification result that the first instruction is the target instruction, sends a constant data request to the constant data cache, and issues the first instruction to the scheduler; The target instruction includes: the target register, the source register, the constant data cache view, and the constant data cache view parameters; A constant data cache is suitable for outputting the target constant data indicated by the first instruction to the executor after receiving a constant data request; A scheduler, adapted to schedule a first instruction to an executor upon receiving a first instruction; The executor is adapted to execute the first instruction and send the execution result to the destination register; The constant data cache detects whether target constant data exists in the constant data cache. If it exists, the target constant data is sent to the executor, and a target constant data ready signal is sent to the executor. The actuator is also used for: In response to the absence of a target constant data readiness signal, the first instruction is locked; Execute the next instruction in the instruction queue following the first instruction; Upon receiving the target constant data ready signal, execution of the first instruction resumes.

2. The graphics processor of claim 1, wherein, The constant data cache view parameters include the number and offset of the constant data cache view used to store the target constant data.

3. The graphics processor of claim 2, wherein, The offset is an immediate value. The constant data cache, in response to receiving the constant data request and detecting that the target constant data exists in the constant data cache, outputs the target constant data to the actuator and sends a target constant data ready signal to the actuator.

4. The graphics processor of claim 2, wherein, The offset is a register. The constant data cache, in response to receiving the constant data request and detecting the existence of the target constant data in the constant data cache according to the register addressing method, outputs the target constant data to the actuator and sends a target constant data ready signal to the actuator.

5. The graphics processor of claim 3 or 4, wherein, The graphics processor also includes an L0 cache, coupled to the constant data cache, which is suitable for storing constant data; The constant data cache is also used to: send a constant data request to the L0 cache in response to the absence of the target constant data; The target constant data returned by the L0 cache is obtained and saved, the target constant data is output to the actuator, and a target constant data ready signal is sent to the actuator.

6. A method of low-latency instruction execution for retrieving constant data, comprising: include: The instruction cache retrieves the instruction queue, which includes a first instruction. The first instruction is identified, and if it is identified as a target instruction, a constant data request is sent to the constant data cache, and the first instruction is sent to the scheduler. Upon receiving the constant data request, the constant data cache outputs the target constant data indicated by the first instruction to the executor. After receiving the first instruction, the scheduler schedules the first instruction to the executor; The executor executes the first instruction based on the received target constant data and sends the execution result to the target register; The target instruction includes: a target register, a source register, a constant data cache view, and constant data cache view parameters; Wherein, after receiving the constant data request, the constant data cache outputs the target constant data indicated by the first instruction to the executor, which includes: detecting whether the target constant data exists in the constant data cache; if it exists, sending the target constant data to the executor and sending a target constant data ready signal to the executor; The actuator also locks the first instruction in response to not receiving the target constant data ready signal; executes the next instruction in the instruction queue of the first instruction; and resumes execution of the first instruction in response to receiving the target constant data ready signal.

7. The method of claim 6 wherein the low latency fetch constant data instruction is executed by the processor by: After receiving the constant data request, the constant data cache further includes outputting the target constant data indicated by the first instruction to the executor. ​ If the target constant data does not exist, the constant data cache sends a constant data request to the L0 cache. In response to the L0 cache returning the target constant data, the target constant data is sent to the executor, and a constant data ready signal is sent to the executor. The L0 cache is suitable for storing constant data.

8. A terminal device, comprising: Includes the graphics processor as described in any one of claims 1 to 5.

9. A computer-readable storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and a computer program is stored thereon, characterized in that, The computer program is executed by the processor to perform the steps of the low-latency instruction execution method for acquiring constant data as described in claim 6 or 7.

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