Wafer cutting method

Abstract

The invention provides a wafer cutting method, and relates to the technical field of wafer cutting. The wafer cutting method comprises the steps that a wafer is provided, a cutting channel is marked on the first surface of the wafer, and the key size of the cutting channel is more than two times of the maximum diameter of a laser beam; a stripping layer with a notch is formed on the second surface of the wafer, the second surface is opposite to the first surface, the notch exposes the cutting channel, and the edge of the notch completely coincides with the edge of the cutting channel; forming a non-stripping layer in the gap; providing a supporting film, and adhering the stripping layer and the non-stripping layer to the surface of the supporting film; cutting along the edge of the cutting channel by using a laser beam so as to cut the wafer into a plurality of chips; and releasing the adhesion between the stripping layer and the supporting film, and taking out the chip on the stripping layer. According to the wafer cutting method, the cutting channels can be prevented from being brought out together when the chip is taken down after cutting is completed.

Description

Technical Field

[0001] This application relates to the field of wafer dicing technology, and more specifically, to a wafer dicing method. Background Technology

[0002] Laser cutting technology is widely used in the wafer dicing field due to its advantages such as high efficiency, high precision, and non-destructive operation. Before laser cutting a wafer, dicing tracks need to be marked on the wafer to pre-mark the cutting path and provide guidance for laser cutting. During cutting, the laser beam only needs to cut along the dicing tracks to divide the entire wafer into multiple independent grains.

[0003] However, the diameter of the laser beam is limited. When the critical dimension (CD) of the dicing track on the wafer exceeds the maximum diameter of the laser beam, a single cut cannot remove the entire track. To address this issue, existing technologies employ a two-step cutting method for the same track: first cutting along one edge of the track, then cutting along the opposite edge. However, when removing the chip after cutting, the middle dicing track is easily carried out with it, leading to poor chip performance or interference with chip bonding. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a wafer dicing method that avoids the dicing track being carried out along with the chip when it is removed after dicing.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: This application provides a wafer dicing method, comprising: providing a wafer, wherein a first surface of the wafer is etched with dicing tracks, the critical dimension of which is more than twice the maximum diameter of a laser beam; forming a release layer with a notch on a second surface of the wafer, wherein the second surface is opposite to the first surface, the notch exposes the dicing tracks, and the edge of the notch completely coincides with the edge of the dicing tracks; forming a non-release layer within the notch; providing a support film and adhering the release layer and non-release layer to the surface of the support film; using a laser beam to dice along the edge of the dicing tracks to dice the wafer into multiple chips; detaching the release layer from the support film and removing the chips from the release layer.

[0006] Optionally, the support film, the release layer, and the non-release layer are all adhesive; removing the release layer from the support film includes: irradiating the release layer with a laser on the side of the support film to make the release layer lose its adhesiveness.

[0007] Optionally, detaching the release layer from the support film and removing the chip from the release layer includes: detaching the release layer from the support film; stretching the support film to loosen the chip from the support film; and removing the chip.

[0008] Optionally, removing the chip from the release layer includes: lifting the chip on the side of the support film away from the release layer and removing the chip.

[0009] Optionally, after removing the chip from the release layer, the wafer dicing method further includes removing the release layer.

[0010] Optionally, forming a release layer with notches on the second surface of the wafer includes: depositing a release material on the second surface of the wafer to form a complete release film; and etching the release film to form notches on the release film.

[0011] Optionally, forming a non-peeling layer within the gap includes: depositing a non-peeling material on the peeling layer, the non-peeling material filling the gap; and removing the non-peeling material outside the gap to form a non-peeling layer filling the gap.

[0012] Optionally, cutting along the edge of the cutting track using a laser beam includes: simultaneously cutting two opposite edges of the cutting track using two laser beams.

[0013] Optionally, before forming a release layer on the second surface of the wafer, the wafer dicing method further includes thinning the wafer on the side of the wafer away from the dicing track, with the thinning stopping at the substrate of the wafer.

[0014] Optionally, before forming a notched release layer on the second surface of the wafer, the wafer dicing method further includes: forming a protective layer on the first surface of the wafer, wherein the protective layer completely covers the first surface; and before dicing along the edge of the dicing track using a laser beam, the wafer dicing method further includes: removing the protective layer.

[0015] The beneficial effects of this application include: This application provides a wafer dicing method, comprising: providing a wafer, wherein a first surface of the wafer is etched with dicing tracks, the critical dimension of which is more than twice the maximum diameter of a laser beam; forming a release layer with a notch on a second surface of the wafer, wherein the second surface is opposite to the first surface, the notch exposes the dicing tracks, and the edge of the notch completely coincides with the edge of the dicing tracks; forming a non-release layer within the notch; providing a support film and adhering the release layer and non-release layer to the surface of the support film; using a laser beam to dice along the edge of the dicing tracks to dice the wafer into multiple chips; detaching the release layer from the support film and removing the chips from the release layer. This wafer dicing method utilizes a non-release layer to adhere the dicing tracks to the support film, which avoids the dicing tracks being carried out with the chips when they are removed after dicing, thereby avoiding chip performance degradation or interference with chip bonding caused by the dicing tracks. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the schematic diagrams of the wafer structure provided in the embodiments of this application; Figure 2 A flowchart of a wafer dicing method provided in an embodiment of this application; Figure 3 This is a second schematic diagram of the wafer structure provided in the embodiments of this application; Figure 4 This is one of the process diagrams of the wafer dicing method provided in the embodiments of this application; Figure 5 This is the second schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 6 This is the third schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 7 Fourth schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 8 Fifth schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 9 This is the sixth schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 10 Seventh schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 11Eighth schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 12 Schematic diagram nine of the wafer dicing method provided in the embodiments of this application; Figure 13 This is the tenth schematic diagram of the wafer dicing method provided in the embodiments of this application; Figure 14 This is a schematic diagram of the bonding of a chip to other wafers provided in an embodiment of this application.

[0018] Icons: 10-Wafer; 11-Substrate; 12-Metal Structure Layer; 20-Deviation Track; 30-Chip; 40-Protective Layer; 51-Release Layer; 511-Notch; 52-Non-Release Layer; 60-Support Film; 71-Release Material; 72-Non-Release Material; 80-Other Wafers. Detailed Implementation

[0019] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims. It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending over another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless expressly defined herein. Please refer to Figure 1 While the diameter of the laser beam used in laser cutting can be adjusted within a certain range, it cannot be infinitely expanded. Therefore, when the critical dimension of the cutting path 20 exceeds the maximum diameter of the laser beam, a single cut cannot remove the entire cutting path 20. To address this issue, existing technologies employ a method of cutting the same cutting path 20 twice: first cutting along one edge of the cutting path 20, and then cutting along the opposite edge of the cutting path 20. Figure 1 The red dashed line in the diagram represents the edge of the cutting path 20, and the yellow straight line represents the cutting path of the laser beam. However, when removing the chip 30 after cutting, the cutting path 20 in the middle is easily carried out with it, which can lead to poor performance of the chip 30 or interference with the bonding of the chip 30.

[0020] To address the aforementioned technical problems, this application provides a wafer dicing method applicable to dicing wafers 10 whose critical dimension of the dicing channel 20 is more than twice the maximum diameter of the laser beam, and particularly applicable to dicing wafers 10 whose critical dimension of the dicing channel 20 is significantly larger than the maximum diameter of the laser beam.

[0021] Please refer to Figure 2 Wafer dicing methods include: S100: Provides a wafer in which a first surface of the wafer is etched with a scribe line, the critical dimension of which is more than twice the maximum diameter of the laser beam.

[0022] Please refer to the reference. Figure 1 The wafer 10 to be cut is provided. The wafer 10 has a first surface and a second surface opposite to each other. The first surface has a cleaving 20. The critical dimension of the cleaving 20 is more than twice the maximum diameter of the laser beam to be used for cutting. That is to say, when cutting with a laser beam, even if the diameter of the laser beam is adjusted to the maximum, the cleaving 20 cannot be completely eliminated by a single cut or two cuts.

[0023] For example, please refer to the reference. Figure 3The wafer 10 includes a substrate 11 and a metal structure layer 12 disposed on the substrate 11. The surface of the substrate 11 facing away from the metal structure layer 12 is the second surface of the wafer 10, and the surface of the metal structure layer 12 facing away from the substrate 11 is the first surface of the wafer 10. The metal structure layer 12 includes multiple layers of metal wiring to ensure signal transmission.

[0024] S200: A release layer with a notch is formed on the second surface of the wafer, wherein the second surface is opposite to the first surface, the notch exposes the dicing channel, and the edge of the notch completely coincides with the edge of the dicing channel.

[0025] Please refer to the reference. Figure 4 and Figure 5 A release layer 51 covers the second surface of the wafer 10. A through-hole 511 is formed on the release layer 51, which is located above the dicing track 20 and exposes the dicing track 20. The edge of the dicing track 20 is completely coincident with the edge of the dicing track 20. That is, the outer edge of the orthographic projection of the dicing track 20 onto the first surface of the wafer 10 is completely coincident.

[0026] It is understood that the perfect overlap described in this embodiment is an ideal state. In practical applications, a certain degree of error is allowed. The existence of this error should not affect the performance or bonding of chip 30.

[0027] Before forming the release layer 52 with notch 511, the wafer 10 is typically placed on a table with its second surface facing up and its first surface facing down for ease of handling. This operation may damage the first surface of the wafer 10. To protect the wafer 10, the wafer dicing method may optionally further include forming a protective layer 40 on the first surface of the wafer 10 before forming the release layer 52 with notch 511 on the second surface of the wafer 10, wherein the protective layer 40 completely covers the first surface.

[0028] S300: A non-peelable layer is formed within the notch.

[0029] Please refer to the reference. Figure 6 A non-stripping layer 52 is formed within the notch 511. It can be understood that the stripping layer 51 is located directly above the area on the wafer 10 used to form the chip 30, and the non-stripping layer 52 is located directly above the dicing track 20 of the wafer 10.

[0030] Preferably, the surface of the non-stripping layer 52 facing away from the wafer 10 is flush with the surface of the stripping layer 51 facing away from the wafer 10, to facilitate the next step.

[0031] S400: Provides a support membrane and adheres the release layer and non-release layer to the surface of the support membrane.

[0032] Please refer to the reference. Figure 7The surfaces of the release layer 51 and the non-release layer 52 that are away from the wafer 10 are adhered to the surface of the support film 60, thereby achieving fixation between the release layer 51 and the support film 60, and between the non-release layer 52 and the support film 60.

[0033] S500: Uses a laser beam to cut along the edge of the kerf to cut a wafer into multiple chips.

[0034] Please refer to the reference. Figure 8 and Figure 1 The protective layer 40 covering the first surface of the wafer 10 is removed, exposing the dicing track 20. A laser beam is used to cut along the two opposite edges of the dicing track 20, thereby separating the dicing track 20 from the wafer 10 to obtain multiple individual chips 30.

[0035] If a protective layer 40 is formed on the first surface of the wafer 10 before a release layer 52 with a notch 511 is formed on the second surface of the wafer 10, the wafer cutting method further includes removing the protective layer 40 to expose the dicing track 20 before cutting along the edge of the dicing track 20 using a laser beam.

[0036] S600: De-adheres the release layer from the support film and removes the chip from the release layer.

[0037] Please refer to the reference. Figure 9 After dicing, both chip 30 and dicing track 20 adhere to the support film 60. To obtain chip 30, the release layer 51 needs to be removed from the support film 60, allowing chip 30 to be removed from the support film 60. Since dicing track 20 remains adhered to the support film 60, it will not be pulled out when chip 30 is removed.

[0038] The above wafer dicing method uses a non-stripping layer 52 to adhere the dicing path 20 to the support film 60, which can prevent the dicing path 20 from being carried out with the chip 30 when the dicing is completed and the chip 30 is removed. This avoids the performance degradation of the chip 30 or interference with the bonding of the chip 30 caused by the dicing path 20.

[0039] Alternatively, please refer to Figure 10 The support film 60, the release layer 51, and the non-release layer 52 all have adhesive properties.

[0040] Thus, when the release layer 51 comes into contact with the support film 60, the two adhere together. Similarly, when the non-release layer 52 comes into contact with the support film 60, the two also adhere together. For example, the support film 60 is a UV film.

[0041] At this point, detaching the release layer from the support film includes: S610: The release layer is irradiated with a laser on the side of the support film to make the release layer lose its adhesiveness.

[0042] A laser is used to irradiate the release layer 51 through the support film 60 on the side of the support film 60 away from the release layer 51. The laser causes the release layer 51 to lose its adhesiveness, thereby releasing the adhesion between the release layer 51 and the support film 60.

[0043] It should be noted that the laser irradiation should not affect the adhesion of the support film 60 and the non-peeling layer 52, thereby ensuring that the cutting path 20 can continue to adhere to the support film 60 through the non-peeling layer 52.

[0044] Optionally, detaching the release layer from the support film and removing the chip from the release layer includes: S620: Removes the adhesion between the release layer and the support film.

[0045] S630: Stretch the support film to loosen the chip from the support film.

[0046] S640: Remove the chip.

[0047] Please refer to Figure 9 First, the adhesion between the release layer 51 and the support film 60 is released. At this time, the non-release layer 52 is still adhered to the support film 60. Then, the support film 60 is stretched. During the stretching, the surface of the support film 60 vibrates, which will loosen the chip 30 that has been de-adheded from the support film 60, making it easier to remove.

[0048] Optionally, removing the chip from the peeling layer includes: S650: Lift the chip off the side of the support film away from the release layer and remove the chip.

[0049] The raised chip 30 is positioned at a higher level than the cutting channel 20, making it easier to remove the chip 30. For example, a push pin is used to lift the chip 30.

[0050] Optionally, please refer to again Figure 2 After removing the chip from the release layer, the wafer dicing method also includes: S700: Remove the peeling layer.

[0051] Please refer to the reference. Figure 9 If the release layer 51 is not completely removed when releasing the adhesion between the release layer 51 and the support film 60, the release layer 51 can be removed from the chip 30 after it is taken out, thereby avoiding any impact of the release layer 51 on the chip 30. Removal methods may include laser irradiation, dissolution with an etchant, etc.

[0052] Optionally, forming a notched release layer on the second surface of the wafer includes: S210: Deposit a layer of release material on the second surface of the wafer to form a complete release film.

[0053] Please refer to Figure 11 A layer of release material 71 is deposited on the second surface of wafer 10, and the release film formed by the release material 71 completely covers the second surface.

[0054] S220: Etch the release film to form a notch on the release film.

[0055] Please refer to the reference. Figure 5 The release film is etched to remove the release material 71 above the cutting channel 20, thereby forming a release layer 51 with a notch 511.

[0056] Optionally, forming a non-peelable layer within the notch includes: S310: A layer of non-peeling material is deposited on the peeling layer, and the non-peeling material fills the gap.

[0057] Please refer to Figure 12 A layer of non-peeling material 72 is deposited on the surface of the peeling layer 51, and the non-peeling material 72 will naturally enter the notch 511. In order to ensure that the non-peeling material 72 can fill the notch 511, the deposition thickness of the non-peeling material 72 should be greater than or equal to the depth of the notch 511.

[0058] S320: Remove the non-peel material located outside the gap to form a non-peel layer that fills the gap.

[0059] After the non-peeling material 72 fills the gap 511, the non-peeling material 72 located outside the gap 511 is removed, and a non-peeling layer 52 located only inside the gap 511 and filling the gap 511 is obtained.

[0060] For example, a surface planarization process is used to remove the non-peeling material 72 located outside the notch 511. In this way, not only can a non-peeling layer 52 be obtained that is located only within the notch 511 and fills the notch 511, but the upper surface of the peeling layer 51 is also flush with the upper surface of the non-peeling layer 52, so as to facilitate adhesion to the support film 60 in subsequent steps.

[0061] Optionally, using a laser beam to cut along the edge of the cutting path includes: S510: Uses two laser beams to simultaneously cut the two opposite edges of the cutting path.

[0062] Please refer to Figure 1 and Figure 8 Using two laser beams to cut the cutting track 20 simultaneously, with one laser beam cutting one edge of the cutting track 20 and the other laser beam cutting the other edge of the cutting track 20, can significantly improve cutting efficiency.

[0063] Alternatively, please refer to Figure 2 After cutting along the edge of the kerf using a laser beam, wafer dicing methods also include: S800: Cleans the cut wafers.

[0064] Please refer to the reference. Figure 8 After laser cutting, the cut wafer 10 is cleaned to remove impurities generated during laser cutting, keeping the chip 30 clean and preventing impurities from affecting it. This cleaning step can be performed before or after the chip 30 is removed.

[0065] Alternatively, please refer to Figure 2 Before forming a release layer on the second surface of the wafer, the wafer dicing method further includes: S900: Thinning of the wafer is performed on the side of the wafer away from the dicing track, and the thinning stops at the substrate of the wafer.

[0066] Please refer to the reference. Figure 4 and Figure 13 Thinning the substrate 11 of the wafer 10 can reduce the thickness of the wafer 10 without affecting its function, thereby obtaining a chip 30 with a smaller thickness in subsequent steps.

[0067] Please refer to Figure 14 After obtaining chip 30, the diced chip 30 can be bonded to other wafers 80, i.e., chip-to-wafer (C2W) bonding.

[0068] It should be understood that although the steps in the flowchart are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A wafer cutting method characterized by, The wafer cutting method comprises: providing a wafer, wherein a first surface of the wafer is scribed with a scribe line, a critical dimension of the scribe line is more than twice a maximum diameter of a laser beam; forming a release layer with a gap on a second surface of the wafer, wherein the second surface is opposite to the first surface, the gap exposes the scribe line, and edges of the gap completely coincide with edges of the scribe line; forming a non-release layer in the gap; providing a support film, and adhering the release layer and the non-release layer to a surface of the support film; cutting along edges of the scribe line using the laser beam to cut the wafer into a plurality of chips; releasing the release layer from the support film, and taking out the chips on the release layer.

2. The wafer cutting method according to claim 1, wherein The support film, the release layer and the non-release layer all have adhesion; The releasing the release layer from the support film comprises: irradiating the release layer with a laser from a side of the support film to make the release layer lose adhesion.

3. The wafer cutting method according to claim 1, wherein The releasing the release layer from the support film, and taking out the chips on the release layer comprises: releasing the release layer from the support film; stretching the support film to loosen the chips from the support film; taking out the chips.

4. The wafer cutting method according to claim 1, wherein The taking out the chips on the release layer comprises: lifting the chips on the side of the support film away from the release layer to take out the chips.

5. The wafer cutting method according to claim 1, wherein After the taking out the chips on the release layer, the wafer cutting method further comprises: removing the release layer.

6. The wafer cutting method according to claim 1, wherein The forming a release layer with a gap on a second surface of the wafer comprises: depositing a layer of release material on the second surface of the wafer to form a complete release film; etching the release film to form a gap in the release film.

7. The wafer cutting method according to Claim 1, wherein The forming a non-release layer in the gap comprises: depositing a layer of non-release material on the release layer, the non-release material filling the gap; removing the non-release material outside the gap to form a non-release layer filling the gap.

8. The wafer cutting method according to Claim 1, wherein The cutting along edges of the scribe line using the laser beam comprises: simultaneously cutting two opposite edges of the scribe line using two laser beams.

9. The wafer cutting method according to Claim 1, wherein Before the forming a release layer with a gap on a second surface of the wafer, the wafer cutting method further comprises: thinning the wafer on a side of the wafer away from the scribe line, and stopping the thinning at a substrate of the wafer.

10. The wafer cutting method according to Claim 1, wherein Before the forming a release layer with a gap on a second surface of the wafer, the wafer cutting method further comprises: forming a protective layer on the first surface of the wafer, wherein the protective layer completely covers the first surface; Before the cutting along edges of the scribe line using the laser beam, the wafer cutting method further comprises: removing the protective layer.

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