System-on-chip diagnosis system and method, electronic equipment and program product

Abstract

The embodiment of the invention provides a system-on-chip diagnosis system and method, electronic equipment and a program product, and the system comprises a debugging signal module which is used for generating a control signal, and the control signal comprises a Debug debugging signal and a testability design DFT test signal; and the mode switching module is used for switching between a Debug debugging mode and a DFT test mode according to the control signal so as to debug the chip. According to the technical scheme, a powerful diagnosis means can be effectively provided for deep and hidden hardware faults, the fault positioning accuracy is greatly improved, and the technical problems that in the prior art, complex chip faults are difficult to position, and system-level function debugging is limited are solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and more specifically, to a system-on-a-chip diagnostic system, method, electronic device, and program product. Background Technology

[0002] Traditional system-on-chip (SoC) debugging mainly relies on the Joint Test Action Group (JTAG) interface and the debugging module inside the SoC. This method plays a fundamental supporting role in the chip development and verification process.

[0003] In current technical practices, debugging and DFT scanning are treated as two separate domains, maintained and used by different toolchains and engineering teams. This makes it difficult for engineers to efficiently leverage the strengths of both when dealing with complex problems. For example, when encountering a difficult-to-locate system bug, a software debugging engineer may need to attempt to reproduce the problem multiple times and add logs or breakpoints incrementally, but their limited access to resources makes it difficult to comprehensively and deeply diagnose complex hardware faults. Meanwhile, while DFT test engineers possess the ability to capture the entire register state through the scan chain, this capability is ineffective in the functional debugging process because it is typically only enabled during production testing.

[0004] Therefore, as the complexity of SoCs continues to rise, the industry still relies on limited resource access capabilities for fault localization of complex SoCs. As a result, the limitations of traditional debugging techniques are becoming increasingly apparent, especially in locating deep-seated and hidden hardware faults, which poses a significant challenge to product development cycles and quality control. Summary of the Invention

[0005] This application provides a system-on-a-chip diagnostic system, method, electronic device, and program product to at least address the significant obstacles in locating deep-seated, hidden hardware faults in the prior art.

[0006] According to one embodiment of this application, a system-on-a-chip diagnostic system is provided, comprising:

[0007] A debug signal module is used to generate control signals, wherein the control signals include debug signals and design-for-test (DFT) test signals;

[0008] The mode switching module is used to switch between Debug mode and DFT test mode according to the control signal to debug the chip.

[0009] In one embodiment of this application, the mode switching module is further configured to switch to the Debug mode to debug the chip when the control signal is the Debug signal; and to switch to the DFT test mode to debug the chip when the control signal is the DFT test signal.

[0010] In one embodiment of this application, it further includes: a DFT test mode switching module, used to generate the Design for Testability (DFT) test signal so that the mode switching module switches to the DFT test mode when the Debug mode fails or the system is in a fault state.

[0011] In one embodiment of this application, the debugging signal module includes:

[0012] The debugger is used to generate the debug signals.

[0013] The DFT control module is used to generate the DFT test signal and generate a fault analysis report of the chip based on the received status information of each register of the chip. The fault analysis report includes the values ​​of each register at the moment of the fault.

[0014] In one embodiment of this application, a DFT scan controller is further included, which is used to capture the status information of each register of the chip according to the DFT test signal in the DFT test mode, and transmit the status information of each register to the DFT control module.

[0015] In one embodiment of this application, an interaction module is further included, which is used to receive external input through a debugging interface and trigger a command to generate the control signal based on the external input to the debugging signal module.

[0016] In one embodiment of this application, a system recovery module is further included, which is used to perform a system restart operation after the fault analysis report is generated based on the status information of each received register; the system restart operation includes one of the following: cold start operation; power-on reset.

[0017] One aspect of this application provides a system-on-a-chip diagnostic method, which is executed by the aforementioned system-on-a-chip diagnostic system, including: generating control signals, wherein the control signals include debug signals and design-for-test (DFT) test signals;

[0018] The chip is debugged by switching between Debug mode and DFT test mode according to the control signal.

[0019] In one embodiment of this application, it further includes:

[0020] When the debug mode fails or the system is in a fault state, the design for testability (DFT) test signal is generated to switch to the DFT test mode.

[0021] In one embodiment of this application, it further includes:

[0022] In the DFT test mode, the state information of each register of the chip is captured according to the DFT test signal;

[0023] A fault analysis report for the chip is generated based on the status information of each register. The fault analysis report includes the values ​​of each register at the moment of the fault.

[0024] In one embodiment of this application, after generating the fault analysis report of the chip based on the status information of each register, the method further includes:

[0025] Perform a system restart operation; the system restart operation includes one of the following: cold start operation; power-on reset.

[0026] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0027] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0028] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0029] In the embodiments described above, the system-on-a-chip diagnostic system generates control signals, including debug signals and DFT test signals, through an integrated debug signal module, enabling comprehensive access to the internal state of the chip. The mode switching module dynamically switches between debug mode and DFT test mode based on these control signals. This allows for rapid switching to DFT test mode when encountering complex chip faults, providing a powerful diagnostic tool for deep-seated and hidden hardware faults. It significantly improves the accuracy and speed of fault location, solving the technical problems of difficult complex chip fault location and limited system-level function debugging in existing technologies. Attached Figure Description

[0030] Figure 1This is a structural block diagram of a system-on-a-chip diagnostic system according to an embodiment of this application;

[0031] Figure 2 This is a hardware debugging architecture diagram of a system-on-a-chip diagnostic system according to an embodiment of this application;

[0032] Figure 3 This is a structural block diagram of another system-on-a-chip diagnostic system according to an embodiment of this application;

[0033] Figure 4 This is a flowchart of a system-on-a-chip diagnostic method according to an embodiment of this application;

[0034] Figure 5 This is an example diagram of a system-on-a-chip diagnostic method according to an embodiment of this application;

[0035] Figure 6 This is a structural block diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0036] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0038] To facilitate understanding of the technical solutions in this application, a brief introduction to the technologies involved in this solution is provided.

[0039] JTAG debugging technology provides debuggers with a partial view of the hardware state by accessing a pre-defined set of registers (such as CPU core registers and peripheral control registers). However, when faced with complex system bugs, such as race conditions between multi-core processors, low-probability timing violations, power management state machine deadlocks, or faults related to specific non-debug peripherals, JTAG debugging often falls short. The problem is that JTAG debugging heavily relies on pre-designed debugging resources. When these resources are insufficient to cover all relevant hardware at the fault location, debuggers must employ tedious iterative debugging strategies, which are not only time-consuming but also have limited success rates. On the other hand, the scan chain in Design for Test (DFT) technology is a powerful feature primarily used to detect manufacturing defects during chip production. It chains the internal registers of the chip, allowing test vectors to be injected and responses captured in test mode. This technique provides a global snapshot of the chip's internal registers, but because it has traditionally been considered only suitable for production testing, its potential for system-level functional debugging has not been fully explored. Furthermore, DFT scans are often accompanied by changes to the internal state of the chip, which is considered an unacceptable risk in traditional functional debugging, as the debugging process relies on maintaining the integrity of the fault scene.

[0040] This embodiment provides a system-on-a-chip diagnostic system. Figure 1 This is a structural block diagram of a system-on-a-chip diagnostic system according to an embodiment of this application, such as... Figure 1 As shown, the system-on-a-chip diagnostic system 10 includes:

[0041] The debug signal module 101 is used to generate control signals, including debug signals and design-for-test (DFT) test signals.

[0042] In this embodiment, the debug signal module 101 is a software module responsible for generating and sending debug signals, typically integrated into the debugger software on the host side. In this invention, control signals refer to signals used to control the mode switching module 102 to dynamically switch between debug mode and DFT test mode. A debug signal is a control signal that follows a specific debugging protocol (such as the RISC-V debug architecture) and is used to access and control the chip's processor core, memory, and peripherals for functional-level debugging. A Design for Testability (DFT) test signal is a control signal that follows the DFT protocol and is used in test mode to capture the state of the chip's internal registers or perform test stimuli through a scan chain to identify manufacturing defects.

[0043] In this embodiment, Figure 2 This is a hardware debugging architecture diagram of a system-on-a-chip diagnostic system according to an embodiment of this application, such as... Figure 2 As shown, control signals are output via USB or other communication interfaces, converted into JTAG commands after passing through a protocol bridge, and then accessed by the SoC. The protocol bridge acts as a hardware accelerator; its firmware converts commands sent from the host into low-level JTAG commands and sends them to the SoC. The SoC-side hardware includes three parts: a mode switching module 102, a debug subsystem, and a DFT subsystem. The JTAG signal is connected to the `mode_sel` signal in the Pinmux mode switching debug signal and the Design for Testable (DFT) test signal for mode selection. When `mode_sel=0` in the debug signal, the debug subsystem is selected; when `mode_sel=1` in the DFT test signal, the DFT subsystem is selected. This design offers significant advantages in saving chip bump / pin resources, improving test access flexibility, and enhancing system reliability.

[0044] Optionally, the debug signal module 101 includes: a debugger for generating debug signals; and a DFT control module for generating DFT test signals and generating a fault analysis report of the chip based on the received status information of each register of the chip, the fault analysis report including the value of each register at the moment of the fault.

[0045] In this embodiment, the debug signal module 101 integrates the functions of both the debugger and the DFT control module, forming a key component of the normalized debugging system. The debugger is responsible for generating debug signals to support functional access and debugging of the chip; while the DFT control module focuses on generating DFT test signals. In particular, it can automatically generate a detailed chip fault analysis report based on the received state information of each chip register, which meticulously records the specific values ​​of each register at the moment of the fault. This integrated design allows debuggers to flexibly switch to DFT mode and perform Scandump operations when encountering complex system bugs, thereby quickly capturing a comprehensive snapshot of the internal state for in-depth analysis and root cause location of the problem.

[0046] The mode switching module 102 is used to switch between Debug mode and DFT test mode according to control signals to debug the chip.

[0047] In this embodiment, Debug mode is a chip operation mode that allows an external debugger to access the chip's internal state for functional-level debugging, such as setting breakpoints, single-stepping, and reading / writing registers. DFT test mode is a chip operation mode primarily used for structural testing of the chip during the production phase. It uses scan chain technology to obtain or modify the state of the chip's internal registers to detect potential defects that may occur during the manufacturing process.

[0048] Optionally, the mode switching module 102 is also used to switch to Debug mode to debug the chip when the control signal is a Debug signal, and to switch to DFT test mode to debug the chip when the control signal is a DFT test signal.

[0049] In this embodiment, the mode switching module 102 can dynamically switch between Debug mode and DFT test mode when receiving different control signals. When a Debug signal is received, the mode switching module 102 configures the system in Debug mode. In this mode, the debugger can access and control various preset debug points on the chip, performing debugging operations such as breakpoint setting, single-step execution, and register read / write to locate and resolve functional problems at the software level. When a DFT test signal is received, the mode switching module 102 switches the system to DFT test mode. In this mode, the DFT vector generation and parsing software comes into play, using the JTAG interface and scan chain technology to capture a one-time snapshot of all registers inside the chip. This process not only covers chip areas inaccessible by traditional debugging methods but also, by parsing the scanned data stream, obtains the complete internal state of the chip at a specific moment, thereby assisting engineers in in-depth analysis and location of complex hardware faults. The flexible switching between the two modes not only fully utilizes the chip's internal resources but also greatly improves the efficiency and accuracy of fault diagnosis, especially when facing system-level problems that are difficult to capture using conventional debugging methods, demonstrating significant advantages.

[0050] Applying the technical solution of this embodiment, the system-on-a-chip diagnostic system 10 generates control signals, including Debug signals and DFT test signals, through the integrated debug signal module 101, achieving comprehensive access to the internal state of the chip. The mode switching module 102 dynamically switches between Debug mode and DFT test mode based on these control signals, enabling rapid switching to DFT test mode and executing a Scandump operation when encountering complex chip faults, thereby obtaining a complete snapshot of the state of all registers within the chip. This operation overcomes the bottleneck of limited access range in conventional debugging techniques, providing a powerful diagnostic tool for deep-seated and hidden hardware faults, and greatly improving the accuracy and speed of fault location. By integrating the DFT's panoramic register scanning capability into the debugging process, this invention eliminates blind spots in system-level functional debugging, enhances chip problem location capabilities, and solves the technical problems of difficult complex chip fault location and limited system-level functional debugging in existing technologies. This approach achieves a seamless transition from functional debugging to structural testing without changing physical connections, providing chip developers with a new and efficient fault diagnosis and debugging tool.

[0051] Figure 3 This is a structural block diagram of another system-on-a-chip diagnostic system according to an embodiment of this application, such as... Figure 3 As shown, the system-on-a-chip diagnostic system 10 also includes:

[0052] The DFT test mode switching module 103 is used to generate a Design for Testability (DFT) test signal by the debug signal module 101 when debugging in Debug mode fails or the system is in a fault state, so that the mode switching module 102 switches to DFT test mode.

[0053] In this embodiment, when functional debugging in Debug mode encounters bottlenecks, such as the inability to locate deep hardware faults or a system crash, the host-side debugger software automatically or manually triggers a DFT test mode switch. By generating a specific DFT test signal, the debug signal module 101 prompts the Pinmuux mode switching module 102 to switch the JTAG signal path from the Debug module to the DFT subsystem, achieving an instantaneous transition from debug to test mode. This transition process does not require physical disassembly or reconfiguration of the JTAG interface, maintaining the continuity and efficiency of the debugging process. In DFT mode, through the Scandump operation, the SoC can quickly capture the state of all registers inside the chip, providing the debugger with a comprehensive hardware view and accelerating the location and resolution of complex problems. The Scandump operation after switching to DFT mode is like taking a deep-field photograph at the system failure site, capturing all hardware states of the chip at the moment of failure, providing detailed data support for subsequent fault analysis.

[0054] The system-on-a-chip diagnostic system also includes a signal conversion module 104, which converts control signals into Joint Test Team (JTAG) commands and transmits the JTAG commands within the chip to be debugged via the same link.

[0055] In this embodiment, the signal conversion module 104, as a key component, converts control signals from general, high-level debug commands or scandump command formats into low-level instruction sequences conforming to the JTAG protocol. This process ensures that commands issued from the host can be correctly parsed and executed by the chip being debugged. Through the intervention of the signal conversion module, seamless integration of different command formats is achieved, enabling a unified communication link to carry diverse instruction sets. This includes not only traditional debugger instructions but also the special JTAG operations required for DFT Scandump. This design not only simplifies the communication architecture between the host and the chip, avoiding the complexity caused by multiple parallel interfaces, but also maintains the testability and debuggability of the chip, providing a flexible and powerful interface for in-depth chip diagnostics. In practical implementation, the flexibility of the signal conversion module is also reflected in its ability to support different types of chips. Whether using a RISC-V debug architecture or an ARM CoreSight debug architecture SoC, efficient and accurate debugging or testing operations can be performed through a unified JTAG interface, greatly improving the system's compatibility and practicality.

[0056] The system-on-a-chip diagnostic system also includes: a DFT scan controller 105, which is used to capture the status information of each register of the chip according to the DFT test signal in DFT test mode, and transmit the status information of each register to the DFT control module.

[0057] In this embodiment, the DFT scan controller 105, as a key component of the system, receives DFT test signals from the DFT control module in DFT test mode, thereby capturing real-time status information of various registers within the chip. The DFT scan controller 105 controls the scan chain, allowing the states of all registers within the chip to be moved out and collected one by one, forming a detailed snapshot of the chip's internal state. This state information is then transmitted back to the DFT control module for further parsing and analysis, providing debuggers with a panoramic view of the chip's internal hardware state, helping to locate various problems, including but not limited to manufacturing defects, circuit design issues, and runtime hardware failures. This design not only enhances the depth and breadth of chip testing but also simplifies the test data acquisition process and improves diagnostic efficiency. When the system recovers from DFT test mode to normal operation mode, the DFT scan controller ensures minimal impact of all test operations on chip functionality, maintaining system stability and recoverability. In other embodiments not shown, the function of the DFT scan controller can be implemented through software algorithms or integrated more deeply with other control logic of the chip to further optimize the processing speed and efficiency of the DFT test signal, providing the system with more flexible and efficient testing and debugging capabilities.

[0058] The system-on-a-chip diagnostic system also includes an interaction module 103, which receives external input through a debugging interface and triggers a command to generate control signals to the debugging signal module 101 based on the external input.

[0059] In this embodiment, the interaction module 106 effectively enhances the interactivity between the user and the system. Debuggers can initiate complex control commands, such as switching debug modes or performing scrandump operations in DFT, through a user-friendly graphical user interface or command-line interface. Based on external input, the interaction module can respond instantly, triggering and generating precise control signals to the debug signal module 101, enabling real-time capture and analysis of the chip's internal state.

[0060] The system-on-a-chip diagnostic system also includes a system recovery module 107, which is used to perform a system restart operation after generating a fault analysis report based on the status information of each received register; the system restart operation includes one of the following: cold start operation; power-on reset.

[0061] In this embodiment, after the fault analysis report is generated based on the register status information obtained from the DFT Scandump operation, the system recovery module 107 is immediately started to perform a system restart operation, including but not limited to a cold start or power-on reset. This step ensures that the system state after the Scandump operation is restored, avoiding unavailability caused by the destructive impact of the Scandump process on the system state, thereby maintaining the continuity and repeatability of the debugging process. The cold start operation, through thorough hardware initialization, clears the temporary states of all registers, returning the system to a known safe state, providing a clean starting point for subsequent debugging or production testing. Power-on reset is a fast system restart method that resets the system by reapplying a power signal. It is suitable for scenarios that require rapid restoration of the debugging environment, while reducing non-debugging time in the debugging cycle and improving debugging efficiency. The existence of the system recovery module enables the entire debugging process to not only efficiently locate faults but also ensure that the system can automatically recover after diagnosis, providing chip developers with a more complete and efficient debugging toolchain.

[0062] This embodiment provides a system-level chip diagnostic method, which is executed by the aforementioned system-level chip diagnostic system. Figure 4 This is a flowchart of a system-on-a-chip diagnostic method according to an embodiment of this application, such as... Figure 4 As shown, the method includes:

[0063] S402. Generate control signals, including debug signals and design-for-test (DFT) test signals.

[0064] S404 switches between Debug mode and DFT test mode according to control signals to debug the chip.

[0065] This application provides a system-level chip diagnostic method. This method generates control signals containing both Debug and DFT test signals, enabling dynamic switching between Debug and DFT test modes for comprehensive chip debugging. By uniformly generating control signals at the software level, it can selectively switch to DFT test mode to execute Scandump operations, instantly capturing the state of all registers within the chip. This allows for rapid location and analysis of complex system faults, overcoming the resource access limitations of traditional debugging methods and improving the efficiency and problem-solving capabilities of chip debugging. This method solves the technical problem of incomplete information when debugging deep hardware issues due to the independence of debug and DFT test modes in existing technologies, achieving the technical effect of obtaining a full-state snapshot during chip debugging.

[0066] Optionally, system-on-chip diagnostic methods may also include: generating a Design for Testability (DFT) test signal to switch to DFT test mode when debugging in Debug mode fails or the system is in a fault state.

[0067] In this embodiment, when debugging in debug mode fails or the system is in a fault state, the method further includes generating a Design for Testability (DFT) test signal to dynamically switch to DFT test mode. This mechanism allows the system to automatically or manually trigger a DFT vector when encountering difficult-to-locate problems, causing the chip to enter scan mode.

[0068] Optionally, the system-level chip diagnostic method also includes: capturing the status information of each register of the chip according to the DFT test signal in DFT test mode; generating a fault analysis report of the chip based on the status information of each register, the fault analysis report including the value of each register at the moment of the fault.

[0069] In this embodiment, when the chip is in DFT mode, the DFT vector generation and parsing software sends customized test vectors to the chip via the JTAG interface, triggering a Scandump operation. This process sequentially removes and records the states of all registers within the chip. This operation provides a complete register snapshot of the chip at the moment of failure, offering crucial first-hand data for subsequent fault analysis. Based on the state information of each register, the software automatically generates a detailed chip fault analysis report. The report details the precise values ​​of each register at the time of the fault, providing engineers with a panoramic view for locating complex and hidden hardware faults, greatly improving problem-solving efficiency. The generation of the fault analysis report not only relies on the raw data from the DFT Scandump but also incorporates the chip's netlist information for parsing and mapping, ensuring data readability and the effectiveness of the analysis.

[0070] Optionally, after generating a fault analysis report for the chip based on the status information of each register, the system may also include: performing a system restart operation; the system restart operation includes one of the following: cold start operation; power-on reset.

[0071] In this embodiment, after generating a fault analysis report for the chip based on the status information of each register, a system restart operation is also performed to restore the chip to its initial state, ensuring the reliability of subsequent debugging or normal operation. The system restart operation can be either a cold start or a power-on reset. A cold start operation refers to powering on the chip after it has been completely powered off to clear all status information and restore it to its initial state. A power-on reset, on the other hand, performs a reset while maintaining power to the chip to quickly restore it to a predetermined initial operating state.

[0072] Figure 5 This is an example diagram of a system-on-a-chip diagnostic method according to an embodiment of this application, such as... Figure 5 As shown, for example, the debugging process for Scandump accessibility features is as follows.

[0073] Step 1: Initialization and Regular Debugging. The host establishes a debug connection with the SoC via JTAG, allowing the debugger to perform basic debugging functions.

[0074] Step 2: Problem Triggering and Initial Analysis Failed. The system remains in a fault state (e.g., frozen). This is a prerequisite for executing subsequent Scandump.

[0075] Step 3: Decision Making and Mode Switching. The debugger clicks the "Scandump" button in the GUI. The host software then performs a series of operations:

[0076] 1) Pause the debugging session.

[0077] 2) Configure the SoC to "DFT mode" by switching mode_sel=1.

[0078] Step 4: Execute Scandump. The software-side DFT vector generation software issues a JTAG stimulus, applies a clock to the scan chain, and shifts all registers (i.e., the states of all registers) bit by bit out of the scan chain to the TDO pin.

[0079] Step 5: Data Parsing and Status Analysis. The DFT vector generation software "translates" the shifted binary data stream into a readable report, indicating the value of each register at the moment of the fault. Engineers locate the anomaly by comparing the value with the expected value.

[0080] Step 6: System Recovery. Since the site has been damaged, a system restart is necessary (preferably a cold boot / power-on reset). This is a mandatory, defined step in this procedure to ensure system recoverability.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0082] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps in any of the above method embodiments.

[0083] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0084] Figure 6 This is a structural block diagram of an electronic device according to an embodiment of this application, such as... Figure 6As shown, embodiments of this application also provide an electronic device 600, including a processor 601 and a memory 602, wherein the memory 602 stores a computer program, and the processor 601 is configured to run the computer program to perform the steps in any of the above method embodiments.

[0085] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0086] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0087] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0088] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular hardware and software combination.

[0089] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A system-on-a-chip diagnostic system, characterized in that, The system includes: A debug signal module is used to generate control signals, wherein the control signals include debug signals and design-for-test (DFT) test signals; The mode switching module is used to switch between Debug mode and DFT test mode according to the control signal to debug the chip.

2. The system according to claim 1, characterized in that, The mode switching module is further configured to switch to the Debug mode to debug the chip when the control signal is the Debug signal, and to switch to the DFT test mode to debug the chip when the control signal is the DFT test signal.

3. The system according to claim 1, characterized in that, Also includes: The DFT test mode switching module is used to switch the mode switching module to the DFT test mode when the debug mode fails or the system is in a fault state. The debug signal module generates the Design for Testability (DFT) test signal.

4. The system according to claim 1, characterized in that, The debugging signal module includes: The debugger is used to generate the debug signals. The DFT control module is used to generate the DFT test signal and generate a fault analysis report of the chip based on the received status information of each register of the chip. The fault analysis report includes the values ​​of each register at the moment of the fault.

5. The system according to claim 1, characterized in that, Also includes: The signal conversion module is used to convert the control signal into Joint Test Team JTAG commands and transmit the JTAG commands within the chip to be debugged through the same link.

6. The system according to claim 4, characterized in that, Also includes: The DFT scan controller is used to capture the status information of each register of the chip according to the DFT test signal in the DFT test mode, and transmit the status information of each register to the DFT control module.

7. The system according to claim 1, characterized in that: Also includes: The interaction module is used to receive external input through the debugging interface and, based on the external input, trigger a command to generate the control signal to the debugging signal module.

8. The system according to claim 4, characterized in that, Also includes: The system recovery module is used to perform a system restart operation after generating a fault analysis report based on the status information of each received register; the system restart operation includes one of the following: cold start operation; power-on reset.

9. A system-on-a-chip diagnostic method, characterized in that, The method is performed by the system-on-a-chip diagnostic system according to any one of claims 1 to 7, comprising: Generate control signals, wherein the control signals include debug signals and DFT test signals; The chip is debugged by switching between Debug mode and DFT test mode according to the control signal.

10. The method according to claim 9, characterized in that, Also includes: When the debug test mode fails or the system is in a fault state, the design for testability (DFT) test signal is generated to switch to the DFT test mode.

11. The method according to claim 9, characterized in that, Also includes: In the DFT test mode, the state information of each register of the chip is captured according to the DFT test signal; A fault analysis report for the chip is generated based on the status information of each register. The fault analysis report includes the values ​​of each register at the moment of the fault.

12. The method according to claim 10, characterized in that, After generating the chip's fault analysis report based on the status information of each register, the process further includes: Perform a system restart operation; the system restart operation includes one of the following: cold start operation; power-on reset.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 9 to 12.

14. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 9 to 12.

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