An on-chip signal level conversion circuit and method

Abstract

The application belongs to the technical field of integrated circuits, and discloses an on-chip signal level conversion circuit and method. The on-chip signal level conversion circuit comprises an isolation unit, an auxiliary circuit unit and a latch unit; the isolation unit is connected with an input signal of a first voltage domain, is used for realizing electrical isolation between the first voltage domain and a second voltage domain, and coupling and transmitting the input signal of the first voltage domain to an intermediate node; the auxiliary circuit unit is connected to the intermediate node, is used for enhancing the coupling signal of the intermediate node, and stabilizing the potential of the intermediate node during signal stabilization; the latch unit works in the second voltage domain, and an input end is connected to the intermediate node, is used for inverting and maintaining the output state according to the coupling signal of the intermediate node, and outputs an output signal of the second voltage domain. The circuit structure of the application is simple, is easy to integrate into a chip, and realizes electrical isolation between different voltage domains, low-power signal transmission and high-speed conversion of signals.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an on-chip signal level conversion circuit and method. Background Technology

[0002] In modern integrated circuit systems, different functional modules often operate in different voltage domains. To amplify the signal swing, some circuits use negative voltage charge pumps to generate negative voltage sources, allowing the signal swing range to extend from the negative voltage source to the positive voltage source. In this case, some circuits operate between the negative voltage source and ground, while other circuits operate between ground and the positive voltage source. Therefore, it is necessary to convert the signal from the negative voltage domain to the positive voltage domain for subsequent circuit processing.

[0003] Most current technical solutions focus on the conversion from the positive voltage domain to the negative voltage domain, which is relatively simple and can be directly implemented using MOS switches. However, the conversion from the negative voltage domain to the positive voltage domain faces greater challenges. Traditional negative-to-positive signal conversion schemes typically employ off-chip implementations consisting of an inverting amplifier, signal shaping circuit, and voltage regulator circuit. These circuits suffer from high power consumption and slow speed. Alternatively, there are schemes using optocouplers or isolators to achieve negative-to-positive signal conversion, but these are costly to implement and difficult to integrate onto a single chip.

[0004] While capacitively coupled level shifting schemes offer the possibility of on-chip integration, they face the problem of unstable intermediate node voltage in practical applications. When the signal remains stable, the voltage difference across the isolation capacitor gradually disappears, causing voltage drift at the intermediate node. This drift can lead to false triggering of subsequent latching circuits. Particularly in applications involving transitions from negative to positive voltage domains, the intermediate node is susceptible to interference from negative voltage sources, exacerbating voltage instability and thus affecting circuit reliability. Summary of the Invention

[0005] The purpose of this invention is to provide an on-chip signal level conversion circuit and an on-chip signal level conversion method, which solves the problems of difficulty in on-chip integration of negative voltage domain to positive voltage domain signal conversion, as well as high power consumption and slow speed.

[0006] To address the aforementioned technical problems, this invention provides an on-chip signal level conversion circuit for converting an input signal in a first voltage domain into an output signal in a second voltage domain, comprising:

[0007] An isolation unit is connected to the input signal of the first voltage domain to achieve electrical isolation between the first voltage domain and the second voltage domain, and to couple the input signal of the first voltage domain to the intermediate node;

[0008] An auxiliary circuit unit, connected to the intermediate node, is used to enhance the coupling signal of the intermediate node and stabilize the potential of the intermediate node during signal stabilization.

[0009] The latch unit operates in the second voltage domain, with its input terminal connected to the intermediate node. It is used to flip and maintain the output state according to the coupling signal of the intermediate node, and output the output signal of the second voltage domain.

[0010] Furthermore, the auxiliary circuit unit includes:

[0011] At least one auxiliary capacitor, one end of which is connected to the voltage source of the first voltage domain and the other end of which is connected to the intermediate node;

[0012] At least one N-type MOS transistor is connected between the intermediate node and ground to provide a discharge path to ground for the intermediate node during signal stabilization.

[0013] Furthermore, the isolation unit includes at least one isolation capacitor; one end of the isolation capacitor is connected to the input signal of the first voltage domain, and the other end is connected to the intermediate node.

[0014] Furthermore, the load capacitance of the intermediate node includes the auxiliary capacitor, the input capacitor of the latch unit, and the parasitic capacitance of the intermediate node; the ratio of the capacitance value of the isolation capacitor to the capacitance value of the load capacitor is greater than or equal to 10.

[0015] Furthermore, the latching unit is connected between the power supply terminal and ground of the second voltage domain.

[0016] Furthermore, the latching unit adopts a latching structure.

[0017] Furthermore, it also includes a signal conversion unit; the signal conversion unit operates in the first voltage domain and is connected between the power supply terminal and ground of the first voltage domain, and is used to convert a single-ended input signal into a differential input signal in the first voltage domain.

[0018] Furthermore, the isolation unit includes two isolation capacitors, which respectively receive the input signal of the differential first voltage domain; the auxiliary circuit unit includes a first auxiliary circuit and a second auxiliary circuit respectively; the latch unit is a differential latch, which receives the voltage of the two intermediate nodes and outputs the differential signal of the second voltage domain.

[0019] Furthermore, the voltage range of the first voltage domain includes a negative voltage domain, and the voltage range of the second voltage domain includes a positive voltage domain.

[0020] On the other hand, the present invention also provides an on-chip signal level conversion method, comprising the following steps:

[0021] The processed input signal of the first voltage domain is input to the isolation unit;

[0022] The input signal of the first voltage domain is coupled and output to the intermediate node through the isolation unit;

[0023] The auxiliary circuit unit superimposes and enhances the coupling signal of the intermediate node;

[0024] The latching unit flips and maintains the output state according to the signal coupling of the intermediate node, and outputs the output signal of the second voltage domain.

[0025] Compared with the prior art, the present invention has at least the following beneficial effects:

[0026] The on-chip signal level conversion circuit provided by this invention achieves electrical isolation between different voltage domains through an isolation unit, and transmits signals using capacitive coupling, avoiding the high power consumption problem of traditional solutions. It enhances the coupling signal of intermediate nodes and stabilizes their potential through auxiliary circuit units, solving the false triggering problem caused by voltage drift at intermediate nodes in capacitive coupling schemes. High-speed signal conversion is achieved through rapid switching and maintaining the output state by a latch unit. The overall circuit structure is simple, the signal conversion speed is fast, and it is easy to integrate onto a chip. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the on-chip signal level conversion circuit in one embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the on-chip signal level conversion circuit in another embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of an on-chip signal level conversion method in one embodiment of the present invention.

[0030] Reference numerals: C1, First isolation capacitor; C2, First auxiliary capacitor; C3, Second isolation capacitor; C4, Third isolation capacitor; C5, Second auxiliary capacitor; C6, Third auxiliary capacitor; M1, First N-type MOSFET; M2, Second N-type MOSFET; M3, Third N-type MOSFET; Sp, First differential signal; Sn, Second differential signal; VNEG, Negative voltage source in the first voltage domain; VDD, Positive voltage source in the second voltage domain; Sin, Input signal in the first voltage domain; Sop, Output signal in the second voltage domain. Detailed Implementation

[0031] Based on the teachings of this specification, those skilled in the art can form new technical solutions by combining different implementation methods without creating technical contradictions. Such variations should be considered to fall within the protection scope of this application.

[0032] The following is a more detailed description of an on-chip signal level conversion circuit and method of the present invention with reference to schematic diagrams, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0033] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0034] Example 1

[0035] This invention provides an on-chip signal level conversion circuit for converting an input signal in a first voltage domain into an output signal in a second voltage domain, comprising an isolation unit, an auxiliary circuit unit, and a latch unit.

[0036] The isolation unit is connected to the input signal of the first voltage domain to achieve electrical isolation between the first voltage domain and the second voltage domain, and to couple the input signal of the first voltage domain to the intermediate node. By setting up the isolation unit, effective electrical isolation can be formed between different voltage domains, avoiding circuit damage or functional abnormalities caused by direct electrical connections between different voltage domains.

[0037] The auxiliary circuit unit is connected to the intermediate node to enhance the coupling signal of the intermediate node and stabilize the potential of the intermediate node during signal stabilization. The auxiliary circuit unit enhances the voltage change amplitude of the intermediate node during signal transitions, improving signal sensing speed and reliability; when the signal remains stable, the auxiliary circuit unit stabilizes the potential of the intermediate node, preventing voltage drift at the intermediate node from causing false triggering of subsequent latching units.

[0038] The latch unit operates in the second voltage domain, with its input connected to the intermediate node. It flips and maintains the output state based on the coupling signal of the intermediate node, outputting an output signal in the second voltage domain. The latch unit can quickly respond to voltage changes at the intermediate node. When the intermediate node voltage reaches the latch unit's flipping threshold, the latch unit rapidly flips and maintains the new output state, thus completing the signal conversion from the first voltage domain to the second voltage domain. The latch unit ensures that even if the intermediate node voltage fluctuates slightly after the signal has stabilized, the output signal remains stable, thereby improving the circuit's anti-interference capability.

[0039] In this embodiment, the auxiliary circuit unit includes at least one auxiliary capacitor and at least one N-type MOSFET. One end of the auxiliary capacitor is connected to the voltage source of the first voltage domain, and the other end is connected to the intermediate node; the N-type MOSFET is connected between the intermediate node and ground to provide a discharge path to ground for the intermediate node during signal stabilization.

[0040] The auxiliary capacitor utilizes the voltage coupling characteristics of capacitors. During signal conversion, the auxiliary capacitor can quickly provide or absorb charge at intermediate nodes, effectively reducing the charging and discharging time of the isolation capacitor and significantly improving the response speed of signal transmission across voltage domains. Simultaneously, by coupling the stable voltage of the first voltage domain, the auxiliary capacitor provides a potential anchor point for intermediate nodes, reducing potential drift and enhancing signal anti-interference capabilities. Furthermore, the synergistic coupling between the auxiliary and isolation capacitors enhances signal driving capability, reduces the driving current requirement of the isolation capacitor, and achieves efficient signal transmission without the need for additional amplification circuitry. This further optimizes the circuit's energy efficiency without significantly increasing hardware costs, thus meeting on-chip integration requirements.

[0041] During signal stabilization, the N-type MOSFET conducts to form a low-impedance discharge path, quickly releasing residual charge at intermediate nodes and preventing node potential shifts caused by charge accumulation. This ensures a consistent initial state for the next signal transition, effectively preventing threshold drift and signal distortion, and guaranteeing the long-term accuracy of the circuit. The N-type MOSFET's conduction and cutoff are adaptively linked to the signal transition timing, automatically cutting off during signal transitions without interfering with the charge transfer process. This eliminates the need for complex control circuitry, simplifying the overall circuit structure and reducing power consumption. Simultaneously, the N-type MOSFET acts as a clamping mechanism, limiting the lowest potential of intermediate nodes from approaching ground. This prevents negative overvoltage caused by abnormal voltage fluctuations in the negative voltage domain from being transmitted to subsequent circuits in the positive voltage domain, protecting other devices and improving the circuit's reliability and stability.

[0042] In this embodiment, the isolation unit includes at least one isolation capacitor. One end of the isolation capacitor is connected to the input signal of the first voltage domain, and the other end is connected to the intermediate node. Utilizing the DC-blocking and AC-passing characteristics of a capacitor, the isolation unit can couple and transmit dynamic signal changes from the first voltage domain to the second voltage domain without transmitting the static voltage of the first voltage domain, thereby achieving safe isolation and signal transmission between voltage domains.

[0043] The choice of isolation capacitor value directly affects the signal transmission effect and speed; its value can be flexibly adjusted according to the signal conversion speed. The isolation capacitor value needs to be large enough to effectively transmit the dynamic changes of the input signal in the first voltage domain to the intermediate node; at the same time, the isolation capacitor value cannot be too large, otherwise it will increase the circuit area and cost.

[0044] Furthermore, isolation capacitors do not rely on complex amplification and shaping circuits, have a simple structure, and can be directly integrated onto the chip. This not only significantly reduces hardware costs and circuit complexity but also avoids the high power consumption problem caused by additional components in traditional off-chip solutions. Combined with auxiliary circuits, it further achieves the design goal of zero static power consumption, making the overall circuit more applicable and competitive in fields such as high-precision sensors and multi-voltage detection.

[0045] Furthermore, the load capacitance of the intermediate node includes the auxiliary capacitor, the input capacitor of the latch unit, and the parasitic capacitance of the intermediate node. The ratio of the capacitance value of the isolation capacitor to the capacitance value of the load capacitor is greater than or equal to 10.

[0046] From the perspective of signal transmission efficiency, this ratio ensures that the isolation capacitor has sufficient charge driving capability, effectively overcoming the charge shunting effect of the load capacitor. This allows the intermediate node to obtain a sufficiently large signal swing when the signal in the negative voltage domain is coupled through the capacitor, preventing signal attenuation due to excessive load. This lays the foundation for accurate signal identification and amplification by the subsequent latching unit. Regarding conversion speed, the ample charge of the isolation capacitor accelerates the charging and discharging process of the intermediate node, preventing the load capacitor from slowing down the signal response and enabling high-speed real-time conversion. Simultaneously, this ratio design reduces the interference of the load capacitor on signal stability, minimizes signal distortion caused by parasitic capacitance and other uncertainties, and improves the circuit's anti-interference capability.

[0047] In this embodiment, the latching unit is connected between the power supply terminal and ground in the second voltage domain. The latching unit precisely amplifies, latches, and holds the signal coupled to the intermediate node via the isolation capacitor, converting the coupled signal from the negative voltage domain into a stable digital signal in the positive voltage domain that meets the circuit processing requirements, thus completing the final adaptation of the cross-voltage domain signal. Relying on the stable power supply and ground potential references in the positive voltage domain, the latching unit can effectively suppress signal noise and improve the stability and accuracy of the output signal.

[0048] In this embodiment, the latching unit adopts a latching structure. The latching structure exhibits bistable characteristics, enabling it to quickly transition to a new state upon receiving a trigger signal and maintain that state until the next trigger signal arrives. The latching structure also responds quickly to voltage changes at intermediate nodes and maintains its output state after the signal stabilizes. The latching structure eliminates the need for additional complex driver or control modules, significantly improving the circuit's practicality and competitiveness without increasing hardware costs. This allows it to be stably applied in scenarios requiring high signal stability and conversion efficiency, such as high-precision sensors and multi-voltage detection.

[0049] In one specific embodiment, a signal conversion unit is also included. This signal conversion unit operates in the first voltage domain and is connected between the power supply terminal and ground in the first voltage domain. It is used to convert a single-ended input signal into a differential input signal in the first voltage domain. The signal conversion unit enables the circuit to process single-ended input signals, convert them into differential signals, and then perform level conversion. Differential signals have stronger common-mode noise immunity and better signal integrity compared to single-ended signals. The signal conversion unit can be implemented using a conventional single-ended to differential circuit, converting the input signal Sin in the first voltage domain into two differential signals Sp and Sn with opposite phases. These two differential signals are then input to subsequent isolation units.

[0050] Furthermore, the isolation unit includes two isolation capacitors, which respectively receive the input signal of the differential first voltage domain; the auxiliary circuit unit includes a first auxiliary circuit and a second auxiliary circuit respectively; the latch unit is a differential latch, which receives the voltage of the two intermediate nodes and outputs the differential signal of the second voltage domain.

[0051] Two isolation capacitors carry the two branches of the differential signal respectively, which can accurately preserve the differential voltage characteristics of the differential signal and avoid signal crosstalk or distortion. At the same time, through cooperation with the corresponding auxiliary circuit, the charge coupling efficiency and the stability of the intermediate node potential are further enhanced, providing a clear and symmetrical differential input signal for subsequent processing.

[0052] In this embodiment, the voltage range of the first voltage domain includes a negative voltage domain, and the voltage range of the second voltage domain includes a positive voltage domain. Specifically, the voltage range of the first voltage domain can be from the negative voltage source VNEG to the ground power supply GND (0V), and the voltage range of the second voltage domain can be from the ground power supply GND (0V) to the positive voltage source VDD, thus expanding the overall signal swing range of the circuit. The circuit of the present invention can establish a reliable signal transmission channel between these two voltage domains, realizing safe and efficient signal transmission between different voltage domains.

[0053] Example 2

[0054] like Figure 1 As shown, this embodiment is a specific embodiment of Embodiment 1. In this embodiment, the circuit includes an isolation unit, an auxiliary circuit unit, and a latching unit.

[0055] Specifically, the isolation unit includes a first isolation capacitor C1. One end of the first isolation capacitor C1 is connected to the input signal Sin of the first voltage domain, and the other end is connected to the intermediate node.

[0056] The auxiliary circuit unit includes a first auxiliary capacitor C2 and a first N-type MOSFET M1. One end of the first auxiliary capacitor C2 is connected to the voltage source of the first voltage domain, and the other end is connected to the intermediate node. The drain of the first N-type MOSFET M1 is connected to the intermediate node, and the source and gate are connected to ground (GND).

[0057] The latching unit adopts a single-ended latching type holder, which is connected between the positive voltage source VDD and the ground power supply GND in the second voltage domain. The input terminal is connected to the intermediate node, and the output terminal outputs the output signal Sop of the second voltage domain.

[0058] The conversion circuit described in this embodiment adopts a single-ended level conversion method, which has a simple structure, requires fewer components, occupies a small area, and has relatively low power consumption. It is more suitable for application scenarios with constraints on cost, area, and power consumption. In these scenarios, the single-ended structure can minimize circuit complexity and implementation cost while meeting basic performance requirements.

[0059] Example 3

[0060] like Figure 2 As shown, this embodiment is another specific embodiment of Embodiment 1. In this embodiment, the circuit includes a signal conversion unit, an isolation unit, an auxiliary circuit unit, and a latch unit.

[0061] Specifically, the signal conversion unit employs a single-ended to differential circuit, operates in the first voltage domain, and is connected between the negative voltage source VNEG and the ground power supply GND in the first voltage domain. The signal conversion unit converts the input signal Sin in the first voltage domain into two differential signals Sp and Sn with opposite phases, and outputs them through the first differential branch and the second differential branch.

[0062] The isolation unit includes a second isolation capacitor C3 and a third isolation capacitor C4. One end of the second isolation capacitor C3 is connected to the first differential branch circuit, receiving the first differential signal Sp, and the other end is connected to the intermediate node of the first differential branch circuit. One end of the third isolation capacitor C4 is connected to the second differential branch circuit, receiving the second differential signal Sn, and the other end is connected to the intermediate node of the second differential branch circuit.

[0063] The auxiliary circuit unit includes a first auxiliary circuit and a second auxiliary circuit. The first auxiliary circuit includes a second auxiliary capacitor C5 and a second N-type MOSFET M2; the second auxiliary circuit includes a third auxiliary capacitor C6 and a third N-type MOSFET M3. One end of both the second auxiliary capacitor C5 and the third auxiliary capacitor C6 is connected to the voltage source of the first voltage domain. The other end of the second auxiliary capacitor C5 is connected to the intermediate node of the first differential branch, and the other end of the third auxiliary capacitor C6 is connected to the intermediate node of the second differential branch. The drain of the second N-type MOSFET M2 is connected to the intermediate node of the first differential branch, the gate is connected to the intermediate node of the second differential branch, and the source is connected to ground (GND). The drain of the third N-type MOSFET M3 is connected to the intermediate node of the second differential branch, the gate is connected to the intermediate node of the first differential branch, and the source is connected to ground (GND).

[0064] The latching unit employs a differential latch comparator, connected between the positive voltage source VDD in the second voltage domain and the ground power supply GND. The two inputs of the differential latch comparator are respectively connected to the intermediate nodes of the first differential branch and the second differential branch, and the output terminal outputs the output signal Sop of the second voltage domain.

[0065] The conversion circuit described in this embodiment employs a differential level conversion method, which offers strong common-mode noise immunity and high reliability, making it more suitable for applications with high requirements for signal integrity and reliability. In these applications, although the differential structure increases circuit complexity and cost, it provides higher noise margin and signal integrity, enabling stable and reliable operation even in harsh electromagnetic environments.

[0066] Example 4

[0067] like Figure 3 As shown, an on-chip signal level conversion method converts an input signal in a first voltage domain into an output signal in a second voltage domain, comprising the following steps:

[0068] The processed input signal of the first voltage domain is input to the isolation unit. The processed input signal of the first voltage domain can be a single-ended signal or a differential signal converted by the signal conversion unit.

[0069] The isolation unit couples the input signal of the first voltage domain to the intermediate node. Utilizing the DC-blocking and AC-passing characteristics of a capacitor, the isolation unit transmits the dynamic changes of the input signal in the first voltage domain to the intermediate node. When the input signal in the first voltage domain changes abruptly, the voltage difference across the isolation capacitor changes. This change is transmitted to the intermediate node through capacitive coupling, causing a corresponding change in the voltage at the intermediate node.

[0070] The auxiliary circuit unit amplifies the coupled signal of the intermediate node. The auxiliary capacitor and isolation capacitor in the auxiliary circuit unit work together to enhance the voltage change amplitude of the intermediate node. The auxiliary capacitor and isolation capacitor receive the same input signal from the same first voltage domain. When this signal changes, both capacitors simultaneously couple to the intermediate node, resulting in superimposed voltage changes that make the voltage change of the intermediate node more significant. During signal stabilization, the N-type MOSFET in the auxiliary circuit unit provides a discharge path to ground for the intermediate node, stabilizing the potential of the intermediate node and preventing voltage drift.

[0071] The latch unit flips and maintains its output state based on the signal coupling of the intermediate node, outputting an output signal in the second voltage domain. When the voltage change of the intermediate node reaches the flipping threshold of the latch unit, the latch unit quickly flips to a new state and maintains that state after the flip. The signal in the second voltage domain is then output through the latch unit, thus completing the signal conversion from the first voltage domain to the second voltage domain.

[0072] In summary, the on-chip signal level conversion circuit provided by this invention achieves electrical isolation between different voltage domains through an isolation unit, transmits signals using capacitive coupling, and avoids the high power consumption problem of traditional solutions. By enhancing the coupling signal of intermediate nodes and stabilizing their potential through auxiliary circuit units, it solves the problem of false triggering caused by voltage drift at intermediate nodes in capacitive coupling schemes. High-speed signal conversion is achieved through rapid switching and maintaining the output state by a latch unit. The overall circuit structure is simple, the signal conversion speed is fast, and it is easy to integrate onto a chip.

[0073] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An on-chip signal level conversion circuit for converting an input signal in a first voltage domain into an output signal in a second voltage domain, characterized in that, include: An isolation unit is connected to the input signal of the first voltage domain to achieve electrical isolation between the first voltage domain and the second voltage domain, and to couple the input signal of the first voltage domain to the intermediate node; An auxiliary circuit unit, connected to the intermediate node, is used to enhance the coupling signal of the intermediate node and stabilize the potential of the intermediate node during signal stabilization. The latch unit operates in the second voltage domain, with its input terminal connected to the intermediate node. It is used to flip and maintain the output state according to the coupling signal of the intermediate node, and output the output signal of the second voltage domain. The auxiliary circuit unit includes: At least one auxiliary capacitor, one end of which is connected to the voltage source of the first voltage domain and the other end of which is connected to the intermediate node; At least one N-type MOS transistor is connected between the intermediate node and ground to provide a discharge path to ground for the intermediate node during signal stabilization.

2. The on-chip signal level conversion circuit as described in claim 1, characterized in that, The isolation unit includes at least one isolation capacitor; One end of the isolation capacitor is connected to the input signal of the first voltage domain, and the other end is connected to the intermediate node.

3. The on-chip signal level conversion circuit as described in claim 2, characterized in that, The load capacitance of the intermediate node includes the auxiliary capacitor, the input capacitor of the latch unit, and the parasitic capacitance of the intermediate node. The ratio of the capacitance value of the isolation capacitor to the capacitance value of the load capacitor is greater than or equal to 10.

4. The on-chip signal level conversion circuit as described in claim 3, characterized in that, The latch unit is connected between the power supply terminal and ground in the second voltage domain.

5. The on-chip signal level conversion circuit as described in claim 4, characterized in that, The latch unit adopts a latch-type structure.

6. The on-chip signal level conversion circuit as described in claim 1, characterized in that, It also includes a signal conversion unit; The signal conversion unit operates in the first voltage domain and is connected between the power supply terminal and ground in the first voltage domain. It is used to convert a single-ended input signal into a differential input signal in the first voltage domain.

7. The on-chip signal level conversion circuit as described in claim 6, characterized in that, The isolation unit includes two isolation capacitors, which respectively receive the input signal of the differential first voltage domain; the auxiliary circuit unit includes a first auxiliary circuit and a second auxiliary circuit respectively; the latch unit is a differential latch, which receives the voltage of the two intermediate nodes and outputs the differential signal of the second voltage domain.

8. The on-chip signal level conversion circuit as described in claim 1, characterized in that, The voltage range of the first voltage domain includes the negative voltage domain, and the voltage range of the second voltage domain includes the positive voltage domain.

9. An on-chip signal level conversion method, applied to the on-chip signal level conversion circuit as described in any one of claims 1-8, characterized in that, Includes the following steps: The processed input signal of the first voltage domain is input to the isolation unit; The input signal of the first voltage domain is coupled and output to the intermediate node through the isolation unit; The auxiliary circuit unit superimposes and enhances the coupling signal of the intermediate node; The latching unit flips and maintains the output state according to the signal coupling of the intermediate node, and outputs the output signal of the second voltage domain.

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