High-voltage MOS device and integrated circuit

Abstract

According to the high-voltage MOS device and the integrated circuit provided by the invention, the structure of the high-voltage MOS device is optimized, and the field plate structure is added in the epitaxial layer, so that the breakdown voltage of the device can be improved, the possibility that the surface of the device is broken down in advance is reduced, and the area of a chip or the integrated circuit cannot be increased; even the area of a chip or an integrated circuit is reduced, other performance of the device is not affected, and in addition, the field plate located on the surface of the semiconductor substrate is combined, the electric field lines can be further dispersed from different directions, so that the purposes of optimizing electric field distribution, ensuring the distribution uniformity of the electric field lines and further improving the breakdown voltage of the device are achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor microelectronics technology, specifically to the field of high-voltage device technology, and in particular to a high-voltage MOS device and integrated circuit. Background Technology

[0002] Field plate structures are a key design element in semiconductor devices, primarily used to optimize electric field distribution, improve device breakdown voltage, and alleviate the trade-off between breakdown voltage and on-resistance. The core principle of traditional field plate structures is to place a metal layer as a field plate on the surface of a shallow trench isolation (STI) structure or a field oxide structure such as local oxidation of silicon (LOCOS) to guide the electric field lines, making the electric field distribution more uniform throughout the channel region. This widens the depletion region size, reduces the surface electric field peak, and improves the breakdown voltage. To address the problems of poor morphology and easy breakdown at the edges of early metal field plates, resistive field plate technology using semi-insulating polycrystalline silicon was later used. This resulted in a flatter electric field intensity distribution along the drift region surface, significantly improving the device's breakdown voltage.

[0003] High-voltage MOS devices are core semiconductor devices for achieving high-voltage, high-power control. They typically employ field plate structures to improve breakdown voltage, enabling their application in integrated circuits such as BCD (Bipolar-CMOS-DMOS) and HV-CMOS (High-Voltage CMOS). However, adding field plate structures to existing field oxides in high-voltage MOS devices does not adequately improve breakdown voltage. It can only disperse electric field lines in a one-dimensional direction (from the drift region to the field plate), easily leading to field line concentration and premature breakdown, thus failing to achieve the desired effect. Furthermore, to improve breakdown resistance, the field plate area is usually increased, resulting in the field plate structure occupying a large chip area, which is detrimental to improving integrated circuit integration density and increasing chip manufacturing costs. Summary of the Invention

[0004] The purpose of this application is to provide a high-voltage MOS device and integrated circuit to solve the above-mentioned technical problems.

[0005] On one hand, this application provides a high-voltage MOS device, including a substrate, a first epitaxial layer and a second epitaxial layer stacked sequentially, and a gate dielectric layer and a gate stacked on the second epitaxial layer; the second epitaxial layer has a well region, and the well region has a source region and a drain region; wherein, the second epitaxial layer also has a first field plate, and each first epitaxial layer also has a second field plate.

[0006] In this embodiment, by optimizing the structure of the high-voltage MOS device and setting a field plate structure in the epitaxial layer, a portion of the electric field lines can be transferred from the device surface to the vicinity of the field plate in the epitaxial layer. This achieves the purpose of dispersing the electric field lines downward from the device drift region, thereby improving the device breakdown voltage and reducing the possibility of premature breakdown at the device surface. Moreover, adding a field plate in the epitaxial layer does not require additional area of ​​the device, and therefore does not occupy the chip area. This ensures that the chip area will not increase, and may even help to reduce the chip area, without affecting the original performance of the device.

[0007] Furthermore, by combining the second field plate in the epitaxial layer with the first field plate located on the surface of the second epitaxial layer, i.e., the field plate structure located on the upper surface of the semiconductor substrate, electric field lines can be dispersed from two directions (downward from the device drift region and upward from the device drift region), thereby achieving the purpose of optimizing the electric field distribution. Moreover, the distances of both from the drift region are as equal as possible, which can ensure the uniformity of the electric field line distribution and further improve the breakdown voltage of the device.

[0008] In one optional embodiment, the orthographic projection of the well region onto the substrate surface is located within the orthographic projection range of at least one second field plate onto the substrate surface; further, the second field plate includes multiple floating field plates, which are arranged in an array or in multiple concentric rings spaced apart.

[0009] In this embodiment, the second field plate is set as a multi-segment floating field plate, which can further optimize the distribution of electric field lines, improve the uniformity of electric field lines, greatly reduce the concentration of electric field lines, and reduce the possibility of premature breakdown at the end of the field plate (i.e., the edge of the field plate).

[0010] In one optional embodiment, when multiple floating field plates are arranged in an array, in the length direction of the array arrangement, the length of the first orthographic projection of the second field plate on the substrate is 1 to 1.5 times the length of the second orthographic projection of the well region in the second epitaxial layer on the substrate, and in the width direction of the array arrangement, the width of the first orthographic projection is 1 to 1.5 times the width of the second orthographic projection; the aforementioned length direction can also be referred to as the first direction, which refers to the direction parallel to the source region to the drain region; the aforementioned width direction can also be referred to as the second direction, which is parallel to the surface of the first substrate and perpendicular to the first direction.

[0011] In one optional implementation, when multiple floating field plates are arranged in an array, the first spacing between two adjacent floating field plates in the length direction of the array is equal to the second spacing between two adjacent floating field plates in the width direction of the array.

[0012] In one optional embodiment, the second field plate has at least two layers, and multiple floating field plates in two adjacent layers of the second field plate are spaced apart in the length direction and in the width direction, respectively.

[0013] In one optional embodiment, the second field plate is multilayered, and the orthographic projections of the floating field plates in the two odd-numbered second field plates on the substrate coincide, while the orthographic projections of the floating field plates in the two even-numbered second field plates on the substrate coincide.

[0014] In one optional embodiment, when multiple floating field plates are arranged in multiple concentric rings, the diameter of the outermost ring in the multiple concentric rings projected onto the substrate is 1 to 1.5 times the diagonal length of the second projection of the well region onto the substrate.

[0015] In one optional implementation, when multiple floating field plates are arranged in multiple concentric rings, each floating field plate is fan-shaped.

[0016] In one alternative implementation, each floating field plate has the same radial dimension in the radial direction of the annulus.

[0017] In one optional embodiment, at least a portion of the outer surface of the floating field plate is covered with an insulating dielectric layer; more preferably, the outer surface of the floating field plate, except for the outer surface facing the second epitaxial layer, is covered with an insulating dielectric layer.

[0018] In this embodiment, an insulating dielectric layer is used to at least partially cover the floating field plate, which can effectively prevent impurities in the floating field plate from diffusing into the epitaxial layer and affecting the field plate profile and the performance of the high-voltage MOS device.

[0019] In one optional embodiment, a drift region is provided in the trap region, the aforementioned source region is located outside the drift region, and the aforementioned drain region is located inside the drift region; the difference between the first distance of the first field plate from the bottom of the drift region and the minimum second distance of the second field plate from the bottom of the drift region is within 10%.

[0020] In one alternative implementation, the first field plate is a polycrystalline silicon field plate, and / or the second field plate is a polycrystalline silicon field plate.

[0021] On the other hand, this application provides an integrated circuit that includes the high-voltage MOS device mentioned in the preceding aspect. This integrated circuit may be, for example, a BCD, HV-CMOS, or other integrated circuit.

[0022] The high-voltage MOS device and integrated circuit provided in this disclosure optimize the structure of the high-voltage MOS device by setting a field plate in its epitaxial layer, which can improve the breakdown voltage of the device, reduce the possibility of premature breakdown on the device surface, disperse the electric field lines, improve the uniformity of the electric field line distribution, and further improve the device performance. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 A longitudinal cross-sectional view of a high-voltage MOS device provided in an embodiment of this application; Figure 2 for Figure 1 A schematic cross-sectional view of the high-voltage MOS device shown in the figure; Figure 3 A longitudinal cross-sectional schematic diagram of another high-voltage MOS device provided in an embodiment of this application; Figure 4 A cross-sectional schematic diagram of another high-voltage MOS device provided in an embodiment of this application; Figures 5 to 10 This is a cross-sectional schematic diagram of each manufacturing step in the manufacturing method provided in the embodiments of this application. Detailed Implementation

[0025] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same structures or parts are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known structural components may not be shown. For simplicity, a semiconductor structure obtained after several steps may be depicted in a single figure. Additionally, features of the examples described below may be combined with each other unless otherwise specified.

[0026] In the description of this application, terms such as "first" and "second" are used only for distinction and do not represent priority or quantity. For ease of description, this application uses spatial relationship terms such as "above," "upper," "below," and "lower" to describe the relationship between one structure and another structure as shown in the figures. However, if the device in the figures is flipped, it is described that the structure located "above" or "upper" relative to another structure will subsequently be located "below" or "lower" relative to another structure.

[0027] Figure 1 This is a longitudinal cross-sectional schematic diagram of a high-voltage MOS device provided in an embodiment of this application. Figure 1As shown in the illustration, the high-voltage MOS device 100 of this application embodiment includes a semiconductor substrate, a source region 160 and a drain region 170 located in the semiconductor substrate, and a gate structure disposed on the semiconductor substrate. The semiconductor substrate includes a substrate 110, at least one first epitaxial layer 120, and a second epitaxial layer 130 sequentially stacked. The gate structure is located on the second epitaxial layer 130 and includes a gate dielectric layer 140 and a gate 150 stacked together. Furthermore, both the source region 160 and the drain region 170 are located within the second epitaxial layer 130.

[0028] Furthermore, the high-voltage MOS device 100 also includes a first field plate 180 and at least one second field plate 190. The first field plate 180 is disposed on the second epitaxial layer 130 and located between the gate 150 and the drain region 170. In this embodiment, the first field plate 180 and the gate 150 are disposed adjacent to each other. An isolation dielectric layer is provided between the first field plate 180 and the second epitaxial layer 130. In this embodiment, a portion of the gate dielectric layer 140 is located between the first field plate 180 and the second epitaxial layer 130, meaning the gate dielectric layer 140 also serves as an isolation dielectric layer between the first field plate 180 and the semiconductor substrate. In other embodiments, field oxides such as LOCOS are used as the isolation dielectric layer between the first field plate 180 and the semiconductor substrate.

[0029] The second field plate 190 is disposed in the first epitaxial layer 120, and at least one second field plate 190 corresponds one-to-one with at least one first epitaxial layer 120, that is, each first epitaxial layer 120 contains one second field plate 190. Figure 1 For ease of description, only one first epitaxial layer 120 and its second field plate 190 are shown. It can be understood that when there are two or more first epitaxial layers, the number of second field plates will also increase accordingly, for example... Figure 3 As shown, there are four first epitaxial layers and four second field plates, which will not be described in detail here.

[0030] Understandably, for high-voltage MOS devices, a well region 101 and a drift region 102 located in the well region 101 are also provided in the second epitaxial layer 130. A shallow channel isolation region 103 may also be provided in the drift region 102. The aforementioned source region 160 is located in the well region 101 and outside the drift region 102, while the drain region 170 is located in the drift region 102.

[0031] In addition, the high-voltage MOS device 100 may also be provided with an insulating protective layer and a lead-out structure. The insulating protective layer covers and protects the gate 150, source region 160, drain region 170, first field plate 180 and exposed portion of the second epitaxial layer 130, etc. The lead-out structure includes a metal wiring layer covering the insulating protective layer and a conductive plug penetrating the insulating protective layer to lead out the gate 150, source region 160 and drain region 170, etc., respectively.

[0032] The high-voltage MOS device provided in this application, in addition to having a first field plate between the semiconductor substrate and the insulating protective layer, also has a second field plate in the epitaxial layer. This allows the surface electric field to be modulated by the MOS capacitor, transferring a portion of the electric field lines from the device surface to the device interior, and more specifically, to the vicinity of the second field plate. The electric field lines are dispersed downwards from the device drift region. Thus, through the cooperation between the first and second field plates, the electric field lines can be dispersed in two directions (downwards from the device drift region and upwards from the device drift region), further preventing the electric field lines from concentrating, ensuring the uniformity of the electric field line distribution, and ultimately achieving the goal of optimizing the electric field distribution.

[0033] In one possible implementation, the first field plate and the second field plate can be made of the same material or different materials, wherein the first field plate and the second field plate can be independently selected from metal field plates, resistive field plates, etc.

[0034] Preferably, in the embodiments of this application, considering the processing difficulty, the second field plate can be made of polycrystalline silicon material, that is, the second field plate is a polycrystalline silicon field plate. Compared with the prior art of setting a RESURF layer in the device, the embodiments of this application set a suspended polycrystalline silicon field plate in the epitaxial layer, which does not require precise matching between the doping concentration of the second field plate itself and the doping concentration of the drift region. The process window is wider and less sensitive to process fluctuations, which can reduce the process difficulty and improve the device manufacturing yield.

[0035] Preferably, in this embodiment of the application, the first field plate can also be made of polycrystalline silicon, that is, the first field plate is a polycrystalline silicon field plate. Additionally... Figure 1 The structure shown is for illustrative purposes only. In practice, the first field plate can be either an offset field plate or a floating field plate.

[0036] Furthermore, in order to achieve a uniform distribution of electric field lines and prevent excessive concentration of electric field lines in one direction, which could lead to premature device breakdown, the first distance A1 between the first field plate 180 on the second epitaxial layer 130 and the bottom of the drift region 102 disposed in the second epitaxial layer 130, and the second distance A2 between the second field plate 190 disposed in the first epitaxial layer 120 closest to the second epitaxial layer 130 and the bottom of the drift region 102, can be approximately equal. The difference between the first distance A1 and the second distance A2 is within 10%, i.e., A1*90%≤A2≤A1*110%. Preferably, in this embodiment, the first distance A1 and the second distance A2 are equal.

[0037] Preferably, in this embodiment, the distance between the field plate and the bottom of the drift zone refers to the distance between the center of the field plate and the bottom of the drift zone. In other embodiments, this distance can also be measured from the surface of the field plate, such as the distance between the surface of the field plate facing the bottom of the drift zone and the bottom of the drift zone.

[0038] In this embodiment, the orthographic projection of the second field plate 190 onto the substrate 110 covers the orthographic projection of the well region 101 onto the substrate 110, thus achieving effective alignment and avoiding electric field deviation. It is understood that this embodiment uses a single second field plate 190 as an example for illustration; therefore, the orthographic projection of this field plate onto the substrate 110 needs to cover the orthographic projection of the well region 101 onto the substrate 110. In other embodiments, when two or more layers of second field plates are provided, the overall orthographic projection of the two or more second field plates onto the substrate needs to cover the orthographic projection of the well region onto the substrate.

[0039] The range of the orthographic projection of the second field plate 190 onto the substrate 110, and the range of the overall orthographic projection of two or more second field plates 190 onto the substrate, can refer to the projection area enclosed by the outermost boundary when at least one field plate is orthographically projected onto the substrate.

[0040] Furthermore, in order to avoid electric field line concentration, the second field plate 190 in this embodiment can be configured as a segmented field plate, which can improve the uniformity of electric field lines, optimize the distribution of electric field lines, and reduce the possibility of premature breakdown at the end of the field plate.

[0041] Similarly, when the second field plate 190 is a segmented field plate, the range of the orthographic projection of the second field plate 190 onto the substrate 110, and the range of the overall orthographic projection of two or more second field plates 190 onto the substrate 110, can refer to the projection area enclosed by the outermost boundary of the segmented field plates when all segmented field plates (i.e., the subsequent floating field plates 191) are orthographically projected onto the substrate. If there are gaps or gaps between the projections of all segmented field plates onto the substrate, as long as they are within the area enclosed by the outermost boundary of the segmented field plates, they can be considered as part of the projection area.

[0042] Please also refer to Figure 2 , Figure 2 for Figure 1 The diagram shows a cross-sectional view of a high-voltage MOS device. In the high-voltage MOS device 100 provided in this embodiment, the second field plate 190 includes multiple floating field plates 191 arranged in segments and an insulating dielectric layer 192 corresponding to each floating field plate 191. The multiple floating field plates 191 are arranged in an array. The insulating dielectric layer 192 can completely cover the floating field plates 191, or it can partially cover them.

[0043] Preferably, in this embodiment, the insulating dielectric layer 192 covers a portion of the surface of the floating field plate 191. Specifically, the insulating dielectric layer 192 covers all outer surfaces of the floating field plate 191 except for the outer surface facing the second epitaxial layer 130, thus protecting the floating field plate 191. Furthermore, in the preferred embodiment of this application, when the second field plate is made of polycrystalline silicon, i.e., the floating field plate is made of polycrystalline silicon, it can effectively prevent impurities in the floating field plate 191 from diffusing into the epitaxial layer, affecting the field plate profile and the performance of the high-voltage MOS device.

[0044] In this embodiment, the insulating dielectric layer is used as an example to describe the floating field plate covered on all outer surfaces except the outer surface facing the second epitaxial layer, i.e., the side surface and the bottom surface facing the substrate 110. However, it is not limited to this. In other embodiments, the insulating dielectric layer may be covered on all outer surfaces of the floating field plate, or only the side surface may be covered, or only the bottom surface may be covered, or even no insulating dielectric layer may be covered on the floating field plate. The specific situation can be set according to the device or production requirements.

[0045] In the first direction, i.e., the length direction of the array arrangement, the first spacing S1 between two adjacent floating field plates 191 is preferably the same as the second spacing S2 between two adjacent floating field plates 191 in the second direction, i.e., the width direction of the array arrangement. That is, in any direction of arrangement, the spacing S (first spacing S1 or second spacing S2) between two adjacent floating field plates 191 is fixed. The aforementioned first spacing S1 and second spacing S2 both refer to the dimensions of the epitaxial layer between adjacent floating field plates 191.

[0046] As can be understood from the diagram, the length direction of the array arrangement mentioned above can refer to the direction from the source region to the drain region, or the direction from the drain region to the source region, or the channel length direction. Correspondingly, the width direction of the array arrangement can refer to the channel width direction, or the direction perpendicular to the direction from the source region to the drain region (or from the drain region to the source region) on the deposition plane of the epitaxial layer.

[0047] Preferably, in one possible implementation, in order to ensure that the number of floating field plates is sufficient and to improve the feasibility of process implementation (e.g., if the spacing S is too small, the process will not be easy to implement), the spacing S between two adjacent floating field plates 191 should not be too large or too small. It can usually be set to 0.1μm to 0.5μm according to the process node and the size of the high-voltage MOS device, that is, the values ​​of S1 and S2 are both in the range of 0.1μm to 0.5μm; the length L1 and width W1 of each floating field plate should also not be too large or too small. They can usually be set to 0.5μm to 1μm according to the process node and the size of the high-voltage MOS device. Of course, L1 and W1 can be the same or different.

[0048] In one possible implementation, when the floating field plates 191 in both the first field plate 180 and the second field plate 190 are made of polycrystalline silicon, the doping type of the floating field plates 191 in the first field plate 180 and the second field plate 190 can be the same, and the doping concentration can be similar or the same. However, this is not a limitation, and the doping types of the two can also be opposite.

[0049] In one specific embodiment, the array of multiple floating field plates 191 can be a matrix with a total length of L and a total width of W. The total length L can be regarded as the length of the second field plate 190, and the total width W can be regarded as the width of the second field plate 190. Correspondingly, in the length direction of the array arrangement, the length of the first orthographic projection of the second field plate 190 on the substrate 110 (i.e., the total length L) is 1 to 1.5 times the length of the second orthographic projection of the well region 101 in the second epitaxial layer 130 on the substrate 110. Similarly, in the width direction of the array arrangement, the width of the first orthographic projection (i.e., the total width W) is 1 to 1.5 times the width of the second orthographic projection. Correspondingly, at least one layer of the second field plate 190 on the substrate 110 covers the orthographic projection of the well region 101 in the second epitaxial layer 130 on the substrate 110, thereby ensuring maximum dispersion of electric field lines and improving the device breakdown voltage.

[0050] Correspondingly, the number of multiple floating field plates 191 in the matrix array can be derived from the relationship between the length, width and field plate spacing mentioned above. Specifically, after determining the size of the floating field plate 191 according to the design requirements of the device, such as when the length of a floating field plate is L1 and the width is W1, the number of multiple floating field plates 191 can be [W / (W1+S2)]*[L / (L1+S1)], and the result can be rounded down.

[0051] Correspondingly, in the case of multiple layers of second field plates, the number of floating field plates and the total length in each layer of second field plates can remain unchanged.

[0052] In another embodiment, the second field plate 190 has at least two layers, that is, the high-voltage MOS device 100 includes at least two first epitaxial layers 120. Correspondingly, each second field plate 190 is disposed in one first epitaxial layer 120. The plurality of floating field plates 191 in two adjacent second field plates 190 are spaced apart in the length direction and in the width direction, and the third spacing S3 between two adjacent second field plates 190 is (e.g., ...). Figure 3 As shown in the diagram, the third spacing S3 is the same as the first spacing S1. Similarly, the third spacing S3 is also the same as the second spacing S2 mentioned above, that is, the spacing between every two layers of the second field plate 190 is equal.

[0053] Furthermore, regarding the case of multilayer second field plates 190, the orthographic projections of the floating field plates 191 in the two odd-numbered second field plates 190 on the substrate 110 coincide. Similarly, the orthographic projections of the floating field plates 191 in the two even-numbered second field plates 190 on the substrate 110 coincide. It is understandable that, in a special case where there are only three second field plates, the orthographic projections of the floating field plates in the first and third odd-numbered field plates on the substrate coincide. Since there is no fourth field plate, there is no situation where the projections of the even-numbered field plates coincide. Otherwise, the above scheme applies.

[0054] Figure 3 This is a longitudinal cross-sectional schematic diagram of another high-voltage MOS device provided in an embodiment of this application. Figure 3 The high-voltage MOS device 300 provided in the illustrated embodiment, and Figure 1 The difference between the high-voltage MOS device 100 provided in the embodiment shown is that the high-voltage MOS device 300 has multiple first epitaxial layers on the substrate 310, more specifically four first epitaxial layers, and four second field plates corresponding to the four first epitaxial layers.

[0055] For ease of expression, such as Figure 3 In the illustrated embodiment, the four first epitaxial layers from bottom to top are defined as first layer 321, second layer 322, third layer 323, and fourth layer 324, respectively. Correspondingly, the second field plates located in the first layer 321, second layer 322, third layer 323, and fourth layer 324 are defined as first field plate 391, second field plate 392, third field plate 393, and fourth field plate 394, respectively. In this embodiment, the multiple floating field plates in the first field plate 391 and the multiple floating field plates in the second field plate 392 are spaced apart along the length and width directions of the array arrangement.

[0056] Understandably, the spacing here can be such that the orthographic projection of the floating field plate in the first-layer field plate 391 onto the substrate 310 falls between the orthographic projections of the corresponding two floating field plates in the second-layer field plate 392 onto the substrate 310. However, there are no restrictions on whether the orthographic projections of the floating field plates in the first-layer field plate 391 and the corresponding two floating field plates in the second-layer field plate 392 touch or partially overlap. This depends on factors such as the size and spacing of the floating field plates. Figure 3 In the illustrated embodiment, the orthographic projections of the floating field plates in different layers can partially overlap.

[0057] Furthermore, for the first layer field plate 391 and the third layer field plate 393, which are spaced apart, the multiple floating field plates in the first layer field plate 391 and the multiple floating field plates in the third layer field plate 393 are one-to-one corresponding in the stacking direction, and the orthographic projections of the corresponding two floating field plates on the substrate 310 coincide. Similarly, the multiple floating field plates in the second layer field plate 392 and the multiple floating field plates in the fourth layer field plate 394 are one-to-one corresponding in the stacking direction, and the orthographic projections of the corresponding two floating field plates on the substrate 310 also coincide.

[0058] Figure 4 This is a cross-sectional schematic diagram of another high-voltage MOS device provided in the embodiments of this application. Figure 4 The high-voltage MOS device 400 provided in the illustrated embodiment, and Figure 1 and Figure 2 The difference between the high-voltage MOS device 100 provided in the illustrated embodiment is that... Figure 4 In the high-voltage MOS device 400 shown, the floating field plate 491 has a fan-shaped structure, and multiple floating field plates 491 are arranged in multiple concentric rings with a certain interval between adjacent rings. Preferably, the interval between each ring can be the same. In this way, the fan-shaped structure with the above-mentioned interval setting can more evenly disperse the electric field lines and reduce the peak value of the local electric field intensity. In this embodiment, the floating field plate is described using a fan-shaped structure as an example, but it is not limited to this. In other embodiments, the floating field plate can also be elliptical, trapezoidal, triangular, hexagonal, etc.

[0059] Preferably, taking the example where the orthographic projection of the well region of the high-voltage MOS device onto the substrate surface is roughly rectangular, the maximum diameter Φ of the multiple concentric rings can be 1 to 1.5 times the diagonal length of the orthographic projection of the well region of the high-voltage MOS device 400 onto the substrate. This arrangement ensures that the orthographic projection of the device body (gate, source region, drain region, gate dielectric layer, first field plate, etc.) in the high-voltage MOS device 400 is located within the circumference defined by the orthographic projection of the ring with the largest outer diameter among the multiple concentric rings.

[0060] The aforementioned maximum diameter Φ refers to the diameter of the outermost ring projected onto the substrate. In practical applications, the value of the maximum diameter Φ of the multiple concentric rings depends on the dimensions of the high-voltage MOS device 400.

[0061] Furthermore, for each floating field plate 491 in each ring, its radial dimension in the radial direction of the ring is the same, such as... Figure 4 As shown, each sector has the same radial length L3, which further ensures the uniformity of the electric field line distribution.

[0062] In the case of multiple layers of second field plates, the number of floating field plates and their maximum diameter in each layer of second field plates should preferably remain unchanged.

[0063] In this embodiment, a fan-shaped field plate structure is adopted, which has a smoother structural outline and a larger radius of curvature. By increasing the radius of curvature, the electric field distribution can be smoothed, significantly reducing the peak electric field intensity at that point. The electric field is more uniformly distributed over a larger arc, which can effectively avoid points with excessively high local field strength, making it less likely to generate electric field spikes and further reducing the possibility of breakdown at the end of the field plate.

[0064] Accordingly, this disclosure also provides a method for fabricating a high-voltage MOS device, used to fabricate the aforementioned high-voltage MOS device. Please also refer to... Figures 5 to 10 , Figures 5 to 10 This is a cross-sectional schematic diagram of each manufacturing step in the manufacturing method provided in the embodiments of this application. For example... Figures 5 to 10 As shown, the method for fabricating a high-voltage MOS device provided in this application includes: S1. At least one first epitaxial layer is sequentially formed on the substrate, and a second field plate is formed in the current first epitaxial layer after each first epitaxial layer is formed and before the next first epitaxial layer is formed.

[0065] In one possible implementation, depositing a second field plate on the first epitaxial layer includes: growing an oxide layer on the surface of the first epitaxial layer; patterning the oxide layer to form a hard mask, and then etching the first epitaxial layer under the action of the mask to form a plurality of grooves in the first epitaxial layer; depositing doped polysilicon in the grooves, and then removing excess doped polysilicon from the surface of the oxide layer to obtain a floating field plate located in the grooves, forming the second field plate; and removing the oxide layer on the surface of the first epitaxial layer.

[0066] For details, please refer to Figure 5 and Figure 6 This example illustrates the formation of two first epitaxial layers. In this step, a first epitaxial layer 520 is first formed on a substrate 510. Then, an oxide layer is grown on the surface of the first epitaxial layer 520 by means of thermal oxidation or deposition, and the oxide layer is patterned. Then, the patterned oxide layer is used as a hard mask to etch the first epitaxial layer 520 to form a groove of a certain depth. Then, doped polysilicon is deposited, and then the excess doped polysilicon on the surface of the oxide layer is removed by means of CMP process and / or etch-back, leaving only the doped polysilicon located in the groove, thereby forming multiple floating field plates 591. Then, the remaining oxide layer on the surface of the first epitaxial layer 520 is removed, thereby forming the first epitaxial layer 520 with the second field plate 590.

[0067] The methods for forming the epitaxial layer, oxide layer, and depositing doped polysilicon described above are merely illustrative examples and are not limited thereto. Appropriate processes can be selected as needed, such as chemical vapor deposition, molecular beam epitaxy, selective epitaxy, etc.

[0068] Understandably, when it is necessary to fabricate multiple first epitaxial layers 520, a second first epitaxial layer 520 can be formed on the first first epitaxial layer 520 through wafer bonding or epitaxial processes. Then, the above-mentioned processes of growing oxide layers, patterning oxide layers, depositing doped polysilicon, and etching doped polysilicon are repeated to form multiple floating field plates 592 located in the second first epitaxial layer 520.

[0069] In one possible implementation, prior to depositing doped polysilicon within the groove, the method further includes forming an insulating dielectric layer on the inner wall of the groove.

[0070] Understandable, such as Figure 6 and 7 As shown, in order to prevent impurities in doped polysilicon from diffusing into the epitaxial layer and affecting the field plate profile and the performance of high-voltage MOS devices, an insulating dielectric layer, such as a silicon dioxide layer, can be formed on the inner wall of the groove before depositing doped polysilicon to provide insulation and protection, and then the doped polysilicon can be deposited.

[0071] S2. After forming at least one first epitaxial layer and the corresponding second field plate, a second epitaxial layer is formed on the at least one first epitaxial layer.

[0072] Understandably, after forming at least one first epitaxial layer, a second epitaxial layer 530 can be formed using other processes such as wafer bonding or epitaxial growth, for example... Figure 8 As shown in the image.

[0073] S3. A gate and a first polysilicon field plate are formed on the second epitaxial layer, and a source region and a drain region are formed in the second epitaxial layer.

[0074] In this step, after forming the second epitaxial layer 530, the fabrication of structures such as the gate, source / drain regions, and the first polysilicon field plate continues, thereby completing the fabrication of the high-voltage MOS device.

[0075] In one specific embodiment, a gate dielectric material layer can be formed first by thermal oxidation, followed by the deposition of polysilicon. Then, photolithography and etching are used to form the polysilicon gate, the first polysilicon field plate, and the gate dielectric layer. Next, source and drain regions are implanted. After implantation, annealing is performed, ultimately forming the desired structure. Figure 10 The device structure shown.

[0076] In one possible implementation, before forming the gate, source region, drain region, and first polysilicon field plate, the aforementioned method further includes: Isolation trenches, drift regions, and trap regions are formed on the second epitaxial layer.

[0077] Understandably, a hard mask material layer can be formed by depositing a pad oxide layer, SiN, or other hard mask material on the second epitaxial layer. This hard mask material layer is then patterned to form a hard mask layer. Next, the second epitaxial layer is etched to form a spacer trench (STI), followed by silicon dioxide filling. Then, well regions and drift regions are sequentially formed through ion implantation or other methods, ultimately forming a structure like... Figure 9 The structure shown.

[0078] The well region can be a P-type well region (taking a high-voltage NMOS device as an example, or an N-type well region if the doping concentration is low), and the doping concentration of the well region is 10 to 100 times that of the substrate concentration. An N-type drift region is formed in the well region (or a P-type drift region if the doping concentration is low), and the concentration of the drift region is 10 to 100 times that of the well region concentration.

[0079] Understandably, the above steps are only the core steps. In practice, there may also be steps such as forming an insulating protective layer, contact holes, and metal wiring layers, as well as thinning the back side of the substrate. These are conventional processes and will not be elaborated further. Furthermore, the above process steps only cover the formation of… Figure 10 The structure shown is used as an example for illustration. For other high-voltage MOS devices, the process can be adjusted according to the actual structure.

[0080] This application also provides an integrated circuit comprising the aforementioned high-voltage MOS device. This integrated circuit may be, for example, a BCD product, HV-CMOS, etc.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A high-voltage MOS device, characterized in that, It includes a substrate, a first epitaxial layer and a second epitaxial layer stacked sequentially, and a gate dielectric layer and a gate stacked on the second epitaxial layer; the second epitaxial layer has a well region, and the well region has a source region and a drain region; The second epitaxial layer is further provided with a first field plate, and the first epitaxial layer is further provided with at least one second field plate.

2. The high-voltage MOS device according to claim 1, characterized in that, The second field plate includes multiple floating field plates, which are arranged in an array or in multiple concentric rings spaced apart; the orthographic projection of the well region on the substrate surface is located within the orthographic projection range of the at least one second field plate on the substrate surface.

3. The high-voltage MOS device according to claim 2, characterized in that, When the plurality of floating field plates are arranged in an array, along the first direction, the size of the first orthographic projection of the second field plate on the substrate is 1 to 1.5 times the size of the second orthographic projection of the well region on the substrate; Along the second direction, the size of the first orthographic projection is 1 to 1.5 times the size of the second orthographic projection; Wherein, the first direction is parallel to the direction from the source region to the drain region, and the second direction is parallel to the surface of the first substrate and perpendicular to the first direction.

4. The high-voltage MOS device according to claim 2, characterized in that, When the plurality of floating field plates are arranged in an array, the first spacing between two adjacent floating field plates along the first direction is equal to the second spacing between two adjacent floating field plates along the second direction; Wherein, the first direction is parallel to the direction from the source region to the drain region, and the second direction is parallel to the surface of the first substrate and perpendicular to the first direction.

5. The high-voltage MOS device according to claim 3 or 4, characterized in that, The second field plate has at least two layers, and multiple floating field plates in two adjacent layers of the second field plate are respectively spaced apart in the first direction and in the second direction.

6. The high-voltage MOS device according to claim 2 or 5, characterized in that, The second field plate is multilayered, and the orthographic projections of the floating field plates in the two odd-numbered layers of the second field plate on the substrate coincide, while the orthographic projections of the floating field plates in the two even-numbered layers of the second field plate on the substrate coincide.

7. The high-voltage MOS device according to claim 2, characterized in that, When the multiple floating field plates are arranged in multiple concentric rings, the diameter of the outermost ring in the multiple concentric rings projected onto the substrate is 1 to 1.5 times the diagonal length of the well region projected onto the substrate.

8. The high-voltage MOS device according to claim 7, characterized in that, The floating field plate is fan-shaped; and / or, each of the floating field plates has the same radial dimension in the radial direction of the annulus.

9. The high-voltage MOS device according to any one of claims 2 to 8, characterized in that, At least a portion of the outer surface of the floating field plate is covered with an insulating dielectric layer.

10. The high-voltage MOS device according to any one of claims 2 to 8, characterized in that, The trap region is provided with a drift region, the source region is located outside the drift region, and the drain region is located inside the drift region; The difference between the first distance between the first field plate and the bottom of the drift region and the minimum second distance between the second field plate in the first epitaxial layer and the bottom of the drift region is within 10%.

11. The high-voltage MOS device according to any one of claims 1 to 10, characterized in that, The second field plate is a polycrystalline silicon field plate.

12. An integrated circuit, characterized in that, The high-voltage MOS device comprising any one of claims 1-11.

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