Display panel including silicon semiconductor layer having extended portion and electronic device including same

Abstract

The present application relates to a display panel and an electronic device including the same, the display panel including: a plurality of first transistors arranged adjacent to each other in a first direction; and a silicon semiconductor layer including a main portion extending in a first direction and an extending portion extending in a second direction crossing the first direction. In plan view, the extension portion is disposed between the first transistors.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0103444, filed on August 2, 2024, and Korean Patent Application No. 10-2025-0026023, filed on February 27, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display panel, and more specifically, to a display panel including a silicon semiconductor layer having an extended portion and an electronic device including the display panel. Background Technology

[0004] Display panels are already used in a variety of electronic devices. Advances in display panels have enabled them to achieve higher resolutions while also improving overall display quality. To display higher quality images at higher resolutions, the physical size of each pixel has been reduced, and therefore, a higher density of electronic components is required. Summary of the Invention

[0005] A display panel includes: a plurality of first transistors arranged adjacent to each other in a first direction; and a silicon semiconductor layer including a main portion extending in the first direction and an extension portion extending in a second direction intersecting the first direction. In a plan view, the extension portions are disposed between adjacent first transistors of the plurality of first transistors.

[0006] Each of the plurality of first transistors may include a first semiconductor layer and a first gate electrode, the first gate electrode being disposed on and overlapping the first semiconductor layer.

[0007] The first semiconductor layer may include an oxide semiconductor.

[0008] The display panel may also include a gate insulating layer covering a silicon semiconductor layer. A first semiconductor layer may be disposed on top of the gate insulating layer.

[0009] The display panel may also include multiple capacitor electrodes disposed between the gate insulating layer and the first semiconductor layer. The capacitor electrodes among the multiple capacitor electrodes may be spaced apart from each other and may correspond to the first transistors among the multiple first transistors.

[0010] In a plan view, the extension can be positioned between adjacent capacitor electrodes among multiple capacitor electrodes.

[0011] One end of the extension in the second direction may coincide with one end of the portion of each of the plurality of capacitor electrodes adjacent to the extension in the second direction.

[0012] The display panel may also include multiple shielding layers disposed between the capacitor electrodes and the first transistor.

[0013] Each of the multiple shielding layers can be electrically connected to a corresponding capacitor electrode among the multiple capacitor electrodes.

[0014] The display panel may further include a plurality of second transistors corresponding to a plurality of first transistors and a plurality of data lines corresponding to the plurality of second transistors. Each of the plurality of second transistors may have a first end electrically connected to a corresponding data line among the plurality of data lines and a second end electrically connected to a first gate electrode of a corresponding first transistor among the plurality of first transistors. The second semiconductor layer of each of the plurality of second transistors may be disposed on the same layer as the first semiconductor layer of each of the plurality of first transistors.

[0015] The display panel may also include drive voltage lines electrically connected to the silicon semiconductor layer.

[0016] The driving voltage line can be placed on the silicon semiconductor layer.

[0017] The display panel may also include an emission control transistor, comprising a first portion of the main portion disposed on a first side of the extension and a second portion of the main portion disposed on a second side of the extension. Each of the emission control transistors may be electrically connected to a corresponding first transistor among a plurality of first transistors.

[0018] The display panel may also include multiple connection electrodes that electrically connect each of the first and second portions of the main portion to a corresponding first transistor among a plurality of first transistors.

[0019] An electronic device includes a display panel and a lower cover forming the exterior of the electronic device. The lower cover includes an opening exposing a portion of the display panel. The display panel includes a plurality of first transistors arranged adjacent to each other in a first direction; and a silicon semiconductor layer including a main portion extending in the first direction and an extension portion extending in a second direction intersecting the first direction. In a plan view, the extension portions are disposed between adjacent first transistors of the plurality of first transistors.

[0020] Each of the plurality of first transistors may include a first semiconductor layer and a first gate electrode, the first gate electrode being disposed on and overlapping the first semiconductor layer.

[0021] The first semiconductor layer may include an oxide semiconductor.

[0022] The display panel may further include a gate insulating layer covering a silicon semiconductor layer. A first semiconductor layer may be disposed on top of the gate insulating layer. A plurality of capacitor electrodes may be disposed between the gate insulating layer and the first semiconductor layer, spaced apart from each other, and corresponding to a plurality of first transistors.

[0023] In a plan view, the extension can be positioned between adjacent capacitor electrodes among multiple capacitor electrodes.

[0024] The display panel may also include drive voltage lines electrically connected to the silicon semiconductor layer. Attached Figure Description

[0025] A more complete understanding of this disclosure and its many accompanying aspects will be readily obtained when considered in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram of an electronic device according to an embodiment of the present invention; Figure 2 This is a perspective view of an electronic device according to an embodiment of the present invention; Figure 3 This is a perspective view illustrating a case where the electronic device according to an embodiment of the present invention is a wearable electronic device; Figure 4 This is a perspective view showing the case where the electronic device according to an embodiment of the present invention is a vehicle electronic device; Figure 5 This is a plan view of a display module according to an embodiment of the present invention; Figure 6 yes Figure 5 A side view of the display module; Figure 7 yes Figure 5 A floor plan of the display module; Figure 8 yes Figure 7 A magnified plan view of area A of the display module; Figure 9 This is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; Figure 10 It is set in Figure 7 The equivalent circuit diagram of the pixels in the display area of ​​the display module; Figure 11 It shows the setting Figure 7 A plan view showing the positions of transistors, capacitors, etc., in the pixels of the display area of ​​the display module; Figures 12 to 20 It is used for Figure 11 A plan view of components such as transistors and capacitors in each layer of the display panel shown; Figure 21 yes Figure 11 A plan view of the pixel electrodes of the display panel; and Figure 22 It is along Figure 11 The sectional view taken by line B-B'. Detailed Implementation

[0026] Because this invention allows for various modifications and numerous embodiments, certain embodiments will be shown in the accompanying drawings and described in the detailed description. The effects and features of the invention, as well as the methods for implementing them, will be elucidated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the invention is not necessarily limited to the embodiments described below and can be implemented in various forms.

[0027] In the following description, embodiments of the invention will be described with reference to the accompanying drawings, wherein similar or corresponding elements may be given similar reference numerals when described with reference to the drawings, and where an element is not described in detail with respect to the drawings, it will be understood that the element is at least similar to a corresponding element that has been described elsewhere in this disclosure.

[0028] In the embodiments described below, when various elements such as layers, regions, plates, etc., are disposed "on" another element, these elements can not only be disposed "directly" on the other element, but the other element can also be interposed between them. Furthermore, while each figure may represent one or more specific embodiments of this disclosure and is drawn to scale so that relative lengths, thicknesses, and angles can be inferred from them, it should be understood that the invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​can be modified within the spirit and scope of this disclosure, for example, to allow for manufacturing limitations, etc.

[0029] In the following implementation, the x-axis, y-axis, and z-axis are not necessarily limited to the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not necessarily perpendicular to each other.

[0030] In the following embodiments, such terms as the first and second are not necessarily used in a limiting sense, and may be used for the purpose of distinguishing one element from another.

[0031] In the following implementation, the terms “comprising” or “including” as used herein specify the presence of the stated features or elements, but do not exclude the addition of one or more other features or elements.

[0032] In this specification, "A and / or B" means A or B or A and B. Furthermore, "at least one of A and B" means A or B or A and B.

[0033] In the following embodiments, when a layer, region, or element is referred to as being connected, it includes not only cases where the layer, region, or element is directly connected, but also cases where the layer, region, or element is indirectly connected and another layer, region, or element is inserted between them. For example, in this specification, when a layer, region, or element is referred to as being electrically connected, it indicates cases where the layer, region, or element is directly electrically connected and / or cases where the layer, region, or element is indirectly electrically connected and another layer, region, or element is inserted between them.

[0034] Embodiments of this disclosure relate to high-performance display panels and their integration into electronic devices. According to these methods, arrangements of semiconductor layers and transistor configurations can optimize space within pixel circuitry, reduce interference, and enhance image quality. For example, the display panel may include first transistors and a silicon semiconductor layer arranged side-by-side along a first direction, the silicon semiconductor layer including a main portion extending in that same direction and an extension portion extending perpendicularly thereto. In a plan view, the extension portion is disposed between the first transistors. This design allows for better use of available space in compact areas such as high-resolution displays and helps manage manufacturing challenges associated with patterning and defects.

[0035] Silicon semiconductor layers can overlap with a bottom metal layer used as a shield, protecting the circuitry from electrostatic discharge (ESD) and minimizing optical interference. Additionally, oxide semiconductor layers can be used for other transistors in pixel circuits, leveraging their high carrier mobility and low leakage properties. Display panels can also be equipped with various shielding and capacitor layers strategically positioned to enhance performance and stability. For example, shielding layers are electrically connected to capacitor electrodes to further minimize electrical noise and improve display clarity.

[0036] In terms of integration into devices, this advanced display panel is designed to be flexible and suitable for a range of electronic devices, including smartphones, tablets, televisions, smartwatches, and even automotive systems. Various structural areas of the panel can be used, such as display areas, peripheral areas, and sub-areas, and folded or curved areas can exist, allowing for innovative form factors. The multilayered circuitry and display structure, with transistors and capacitors organized across multiple conductive and insulating layers, allows devices to maintain high resolution and reliable operation in demanding physical configurations. This design not only improves image quality but also supports new applications in both consumer electronics and specialized devices such as transparent displays and wearable devices.

[0037] Figure 1This is a schematic block diagram of an electronic device 1 according to an embodiment of the present invention. The electronic device 1 according to the embodiment may be a display device, or may further include modules with additional functions in addition to the display module 11.

[0038] like Figure 1 As shown, the electronic device 1 according to the embodiment may include a display module 11, a processor 51, a memory 52, a power module 54, an input module 55, an output module 56, and a communication module 57.

[0039] The display module 11 may include the display panel 10 as described below (see below) Figure 5 As an example, display module 11 may include display panel 10 and data driver 20 mounted thereon (see [link to relevant documentation]). Figure 5 Display panel 10 is described below.

[0040] Processor 51 can control most of the components of electronic device 1. As an example, processor 51 can output digital video data to display module 11, causing display module 11 to display an image, and can receive input data from input module 55 to allow electronic device 1 to perform functions corresponding to the associated data. Processor 51 may include at least one of a central processing unit (CPU), application processor (AP), graphics processing unit (GPU), communication processor (CP), image signal processor (ISP), and controller.

[0041] When needed, processor 51 can be divided into two or more parts from a functional or structural perspective. Therefore, processor 51 can consist of multiple processing devices operating in concert. As an example, processor 51 may include a main processor in the form of a first driver chip and an auxiliary processor in the form of a second driver chip, the main processor including a central processing unit, and the auxiliary processor being part of display module 11. The auxiliary processor in the form of the second driver chip may include a controller that receives image signals from the main processor and processes the image signals to match the interface specifications of the display panel 10 included in display module 11.

[0042] The memory 52 may include at least one of non-volatile memory (such as flash memory) and volatile memory (such as random access memory (RAM)). The memory 52 may store data information required for the operation of the processor 51 or the display module 11. When the processor 51 executes an application stored in the memory 52, data signals for images and / or input control signals may be transmitted to the display module 11, and the display module 11 may process the provided signals and output image information.

[0043] The power module 54 may include a power module such as a power adapter or battery cell, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 1. Power conversion via the power conversion module may include DC-DC conversion, AC-DC conversion, and DC-AC conversion. However, the invention is not necessarily limited thereto.

[0044] Input module 55 can provide input information to processor 51 and / or display module 11. Input module 55 may include not only physical buttons, keyboards, and microphones, but also various types of sensor modules. Examples of sensor modules may include touch sensors, pressure sensors, proximity sensors, position sensors, digitizers, motion recognition sensors, camera sensors, light receiving sensors, photoelectric conversion sensors, and / or temperature sensors. Furthermore, sensor modules may include biosensors such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, and / or heart rate sensors.

[0045] Output module 56 can receive information other than the image received from processor 51 and can provide that information to the user. Output module 56 may include, for example, a sound module such as a speaker, a haptic module such as a vibration motor, and / or a light-emitting module such as a light-emitting diode (LED). In addition, output module 56 may include unique functional modules of electronic device 1, such as a cooling module of a refrigerator.

[0046] For example, display module 11 can also be responsible for output functions. As an example, display panel 10 included in display module 11 can display (e.g., output) information processed by electronic device 1. As an example, display panel 10 can display execution screen information of an application driven by electronic device 1, user interface (UI), or graphical user interface (GUI) information corresponding to the execution screen information. Display panel 10 may include a display layer and a touchscreen layer, wherein the display layer displays images and the touchscreen layer senses user touch input, such as touch from a finger or stylus / pen. Therefore, display panel 10 can be used as part of input module 55, which provides an input interface between electronic device 1 and the user, and simultaneously as part of output module 56, which provides an output interface between electronic device 1 and the user.

[0047] The communication module 57 is responsible for transmitting / receiving information between the electronic device 1 and external devices, and may include a receiver and a transmitter. The communication module 57 may include various types of wireless communication modules or various types of wired communication modules, such as mobile communication modules, broadcast receiving modules, wireless Internet modules, short-range communication modules, Wi-Fi modules and / or Bluetooth modules.

[0048] Figure 1The electronic device 1 shown is merely an example. As an example, a display device without communication functionality may not include the communication module 57. Furthermore, in cases where electronic device 1 includes a display device, at least one component of electronic device 1 may be included in the display device. Additionally, some of the individual modules functionally included in a single module may be included in the display device, and some other individual modules may be included separately from the display device in electronic device 1. As an example, the display device may include a display module 11, and the processor 51, memory 52, and power module 54 may be components of electronic device 1, rather than the display device itself. Optionally, the display device may include a display module 11 and a power module 54, and the power module 54 may provide power to components such as the processor 51 and memory 52 of electronic device 1. However, various modifications are possible.

[0049] Figure 2 This is a schematic diagram of an electronic device 1 according to an embodiment of the present invention. Figure 2 Examples of electronic devices 1 include a smartphone 1_1a, a tablet computer 1_1b, a laptop / notebook computer 1_1c, a television (TV) 1_1d, and a computer monitor 1_1e. Electronic device 1 may include a display panel and a lower cover forming the exterior of said electronic device 1, the lower cover including an opening that exposes a portion of the display panel.

[0050] The smartphone 1_1a may include not only a processor 51, a memory 52, a power module 54, and a display module 11, but may also include an input module 55 such as a touch sensor and a communication module 57. The smartphone 1_1a can process information received through the communication module 57 or other input modules and display that information through the display module 11.

[0051] Similar to the smartphone 1_1a, the tablet computer 1_1b, laptop / notebook computer 1_1c, television (TV) 1_1d and / or computer monitor 1_1e may include a display module 11 and an input module 55, and may include a communication module 57 depending on the circumstances.

[0052] Figure 3 This is a schematic diagram illustrating the case where the electronic device 1 according to an embodiment of the present invention is a wearable electronic device. Figure 3 The following are examples of electronic devices 1: smart glasses 1_2a, head-mounted display 1_2b, and smartwatch 1_2c.

[0053] The smart glasses 1_2a and head-mounted display 1_2b may include a display module 11 for displaying images and a reflector that reflects the images and provides them to the user's eyes. The user can use the electronic device 1 to experience virtual reality or augmented reality.

[0054] The smartwatch 1_2c may include a biosensor as an input module 55 and provide the user with biological information identified by the biosensor through a display module 11.

[0055] Figure 4 This is a schematic diagram illustrating the case where the electronic device 1 according to an embodiment of the present invention is a vehicle electronic device 1-3. For example... Figure 4 As shown, the vehicle electronic equipment 1_3 may be included in the vehicle's dashboard, center instrument panel, etc., or may be a central information display (CID) set on the vehicle's control panel or an interior mirror display that replaces the side mirrors.

[0056] However, the electronic device 1 according to the present invention is not necessarily limited thereto. As an example, the electronic device 1 according to embodiments of the present invention may include not only devices centered on displays such as digital billboards, electronic billboards, and / or portable game consoles, but also various household appliances that display information via the display module 11, such as refrigerators, washing machines, dryers, air conditioners, and / or robotic vacuum cleaners. Furthermore, where the display module 11 has the function of transmitting light, the electronic device 1 may be a smart window or transparent display device that shares a background and an image. However, the electronic device 1 according to the present invention is not necessarily limited thereto. Any electronic device can fall within the scope of the present invention as long as the electronic device 1 includes the display panel 10 described below.

[0057] Figure 5 This is a schematic plan view of a display module 11 including a display panel 10 according to an embodiment of the present invention, and Figure 6 yes Figure 5 A schematic side view of the display module 11. The electronic device 1 may include... Figure 5 and Figure 6 The display module 11 shown is shown.

[0058] Display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the area in which an image is displayed and can be set with multiple pixels. The display area DA can have various shapes, such as circular, elliptical, polygonal, or the shape of a specific graphic. Figure 5 The image shows that the display area DA has a roughly rectangular shape with rounded corners.

[0059] The peripheral region PA can be located outside the display area DA. The peripheral region PA can include a first peripheral region PA1 and a second peripheral region PA2, wherein the first peripheral region PA1 surrounds at least a portion of the display area DA, and the second peripheral region PA2 is located at the lower end of the display area DA and extends in a first direction (e.g., the x-axis direction). The width of the second peripheral region PA2 in the first direction (e.g., the x-axis direction) can be smaller than the width of the display area DA. At least a portion of the second peripheral region PA2 can be easily bent to a significant degree without breaking or otherwise suffering damage.

[0060] Figure 5 The planar shape of the display panel 10 shown may be substantially equal to that of the substrate 100 included in the display panel 10 (see...). Figure 7 The shape of the substrate 100 is described below. When the display panel 10 includes a display area DA and a peripheral area PA outside the display area DA, it can mean that the substrate 100 includes a display area DA and a peripheral area PA outside the display area DA. In the following description, for convenience, it is assumed that the substrate 100 includes a display area DA and a peripheral area PA.

[0061] Display panel 10 may include a main region MR, a curved region BR outside the main region MR, and a sub-region SR spaced apart from the main region MR and interposed between them. The main region MR may be located on one side of the curved region BR, and the sub-region SR may be located on the other (e.g., opposite) side of the curved region BR. Figure 6 As shown, the display panel 10 can be bent in the curved region BR, and when viewed from a third direction (e.g., the z-axis direction), at least a portion of the sub-region SR can overlap with the main region MR.

[0062] Despite Figure 6 The illustration shows that the display panel 10 is curved, but the invention is not necessarily limited thereto. As an example, the display panel 10 may be a foldable display panel, in which case the display panel 10 may be bent within the display area DA about a bending axis spanning the display area DA. The display panel 10 may not be bent when needed. The sub-region SR may be a non-display area.

[0063] The data driver 20 may be disposed in a sub-region SR of the display panel 10 included in the display module 11. The data driver 20 may be disposed on the display panel 10 in the form of an integrated circuit (IC). As an example, the data driver 20 may be a data driver integrated circuit that generates data signals.

[0064] The display circuit board 30 can be attached to the end of a sub-region SR of the display panel 10. For example, the display module 11 may include the display circuit board 30 when needed. The display circuit board 30 can be electrically connected to the data driver 20, etc., via pads in the sub-region SR of the display panel 10.

[0065] Figure 7 yes Figure 5 A schematic plan view of the display module 11. (See attached diagram.) Figure 7 As shown, the display panel 10 included in the display module 11 may include a substrate 100. Various elements forming the display panel 10 may be disposed on the substrate 100.

[0066] Substrate 100 may comprise glass, ceramic, metal, or polymer resin. Substrate 100 may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Substrate 100 may have a multilayer structure comprising two layers containing the aforementioned polymer resin and an inorganic material layer interposed therebetween. Optionally, substrate 100 may have a structure in which layers comprising polymer resin and inorganic material layers are alternately stacked. The inorganic material layer may comprise, for example, silicon oxide, silicon nitride, or silicon nitride.

[0067] Pixels can be located in a display area DA, and the display area DA can display images using light emitted from the pixels. Each pixel may include a light-emitting diode (LED), and the LED may be electrically connected to a pixel circuitry PC. The pixel circuitry PC and the LED may be disposed within the display area DA. For convenience, although... Figure 7 The diagram shows a pixel circuit PC and a light-emitting diode (LED) arranged side by side, but the pixel circuit PC may at least partially overlap with the LED. As an example, the LED may be positioned on the pixel circuit PC.

[0068] The gate drive circuit, pad 14, first power line 15, and second power line 16 can be disposed in the peripheral region PA. The gate drive circuit may include, for example, a first scan drive circuit 12a, a second scan drive circuit 12b, and / or an emitt control drive circuit 13.

[0069] The first scan drive circuit 12a can be configured to provide a scan signal to the pixel circuit PC via the gate line SL. The second scan drive circuit 12b can be arranged opposite the first scan drive circuit 12a, with the display area DA interposed between them. Some of the pixel circuits PC located in the display area DA can be electrically connected to the first scan drive circuit 12a, and others can be connected to the second scan drive circuit 12b. Depending on the situation, the second scan drive circuit 12b can be omitted.

[0070] Similar to the first scan drive circuit 12a, the emission control drive circuit 13 can be located on one side of the display area DA. The emission control drive circuit 13 can provide emission control signals to the pixels via the emission control line EL. Although in Figure 7 The diagram shows that the emission control drive circuit 13 is located only on one side of the display area DA, but the present invention is not necessarily limited thereto. For example, the display panel 10 may include the emission control drive circuit 13 located on both one and the other side of the display area DA. Optionally, the display panel 10 may include a first scan drive circuit 12a located on one side of the display area DA and an emission control drive circuit 13 located on the other side of the display area DA.

[0071] Pad 14 may be disposed in the second peripheral region PA2 of substrate 100. Pad 14 may be exposed due to not being covered by an insulating layer and may be electrically connected to display circuit board 30. Pad 34 of display circuit board 30 may be electrically connected to pad 14 of display panel 10.

[0072] The display circuit board 30 is configured to transmit signals or power from the controller to the display panel 10. Control signals generated by the controller can be transmitted to the gate drive circuit via the display circuit board 30. Furthermore, the controller can provide a first power voltage ELVDD (see [link to relevant documentation]) to the first power line 15 and the second power line 16. Figure 10 ) and the second power voltage ELVSS (see Figure 10 A first power voltage ELVDD (hereinafter referred to as the driving voltage) can be provided to each pixel circuit PC via the driving voltage line PL connected to the first power line 15, and a second power voltage ELVSS (hereinafter referred to as the common voltage) can be provided to the common electrode of the light-emitting diodes (LEDs) connected to the second power line 16. The first power line 15 may extend in a first direction (e.g., the x-axis direction). The second power line 16 may have a ring shape having an open side and partially surrounding the display area DA.

[0073] The data signal of the data driver 20 can be transmitted to the pixel circuit PC via the data line DL electrically connected to the input line IL.

[0074] Figure 8 yes Figure 7 A schematic enlarged concept diagram of area A of display module 11. (See attached diagram.) Figure 8 As shown, the data line DL, extending in the second direction (y-axis direction), is located in the display area DA, and the input line IL is located in the peripheral area PA. The input line IL can transmit the data signal from the data driver 20 to the data line DL. For ease of explanation, although... Figure 8 The diagram shows that the data lines DL include a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, a fifth data line DL5, and a sixth data line DL6, and the input lines IL include a first input line IL1, a second input line IL2, a third input line IL3, a fourth input line IL4, a fifth input line IL5, and a sixth input line IL6. However, the number of data lines DL and the number of input lines IL can be varied.

[0075] Some data lines DL can be directly connected to the corresponding input lines IL, but some other data lines DL can be electrically connected to the corresponding input lines IL via data transfer lines DTL.

[0076] The first data line DL1, the third data line DL3, and the fifth data line DL5 can receive data signals from the first input line IL1, the third input line IL3, and the fifth input line IL5. The first data line DL1, the third data line DL3, and the fifth data line DL5 can be electrically connected to the first input line IL1, the third input line IL3, and the fifth input line IL5. Each of the first data line DL1, the third data line DL3, and the fifth data line DL5 can be integrally formed with a corresponding one of the first input line IL1, the third input line IL3, and the fifth input line IL5. Optionally, as... Figure 8 As shown, each of the first data line DL1, the third data line DL3, and the fifth data line DL5 can be electrically connected to a corresponding one of the first input lines IL1, IL3, and IL5 through the first contact hole CNT1.

[0077] The second data line DL2, the fourth data line DL4, and the sixth data line DL6 can be electrically connected to the second input line IL2, the fourth input line IL4, and the sixth input line IL6 via the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3. For example, the second input line IL2 can be electrically connected to the second data line DL2 via the first data transmission line DTL1, the fourth input line IL4 can be electrically connected to the fourth data line DL4 via the second data transmission line DTL2, and the sixth input line IL6 can be electrically connected to the sixth data line DL6 via the third data transmission line DTL3.

[0078] A significant portion of each of the first data transmission lines DTL1, DTL2, and DTL3 can be located within the display area DA. One end of each of the first data transmission lines DTL1, DTL2, and DTL3 can be electrically connected via the second contact hole CNT2 to a corresponding one of the second input lines IL2, IL4, and IL6. The other end of each of the first data transmission lines DTL1, DTL2, and DTL3 can be electrically connected via the third contact hole CNT3 to a corresponding one of the second data lines DL2, DL4, and DL6. For example, although in Figure 8 The diagram shows the second contact hole CNT2 and the third contact hole CNT3 located in the peripheral region PA, but the invention is not necessarily limited thereto. As an example, the second contact hole CNT2 and / or the third contact hole CNT3 may be located in the display region DA.

[0079] The first data transmission line DTL1 may include a first horizontal connector DHL1, a first vertical connector DVL1, and a first additional vertical connector DVL1'; the second data transmission line DTL2 may include a second horizontal connector DHL2, a second vertical connector DVL2, and a second additional vertical connector DVL2'; and the third data transmission line DTL3 may include a third horizontal connector DHL3, a third vertical connector DVL3, and a third additional vertical connector DVL3'. The first horizontal connector DHL1, the second horizontal connector DHL2, and the third horizontal connector DHL3 may extend generally in a first direction (e.g., the x-axis direction). The first vertical connector DVL1, the second vertical connector DVL2, the third vertical connector DVL3, the first additional vertical connector DVL1', the second additional vertical connector DVL2', and the third additional vertical connector DVL3' may extend generally in a second direction (e.g., the y-axis direction) and may be substantially parallel to the data line DL.

[0080] Each of the second input line IL2, the fourth input line IL4, and the sixth input line IL6 can be electrically connected through the second contact hole CNT2 to a corresponding one of the first vertical connection line DVL1, the second vertical connection line DVL2, and the third vertical connection line DVL3, and each of the second data line DL2, the fourth data line DL4, and the sixth data line DL6 can be electrically connected through the third contact hole CNT3 to a corresponding one of the first additional vertical connection line DVL1', the second additional vertical connection line DVL2', and the third additional vertical connection line DVL3'. Each of the first horizontal connecting line DHL1, the second horizontal connecting line DHL2, and the third horizontal connecting line DHL3 can be electrically connected to a corresponding one of the first vertical connecting line DVL1, the second vertical connecting line DVL2, and the third vertical connecting line DVL3 through the first connecting contact hole DHL-CNT1, and can be electrically connected to a corresponding one of the first additional vertical connecting line DVL1', the second additional vertical connecting line DVL2', and the third additional vertical connecting line DVL3' through the second connecting contact hole DHL-CNT2.

[0081] The first vertical connecting line DVL1, the second vertical connecting line DVL2, the third vertical connecting line DVL3, the first additional vertical connecting line DVL1', the second additional vertical connecting line DVL2', and the third additional vertical connecting line DVL3' can be disposed on the same first layer, and the first horizontal connecting line DHL1, the second horizontal connecting line DHL2, and the third horizontal connecting line DHL3 can be disposed on a second layer different from the first layer. For example, when certain components are disposed on the same layer, these components can be formed simultaneously using the same material through the same masking process.

[0082] As mentioned above, Figure 8 The diagram shows a first data transmission line DTL1 comprising a first horizontal connecting line DHL1, a first vertical connecting line DVL1, and a first additional vertical connecting line DVL1'; a second data transmission line DTL2 comprising a second horizontal connecting line DHL2, a second vertical connecting line DVL2, and a second additional vertical connecting line DVL2'; and a third data transmission line DTL3 comprising a third horizontal connecting line DHL3, a third vertical connecting line DVL3, and a third additional vertical connecting line DVL3'. However, the invention is not necessarily limited thereto.

[0083] As an example, such as Figure 9 As shown ( Figure 9(This is a schematic enlarged concept diagram of a portion of a display panel 10 according to an embodiment of the present invention). The first data transmission line DTL1 may include a first horizontal connection line DHL1 and a first vertical connection line DVL1, the second data transmission line DTL2 may include a second horizontal connection line DHL2 and a second vertical connection line DVL2, and the third data transmission line DTL3 may include a third horizontal connection line DHL3 and a third vertical connection line DVL3. In this case, each of the first horizontal connection line DHL1, the second horizontal connection line DHL2, and the third horizontal connection line DHL3 can be electrically connected to a corresponding one of the first vertical connection lines DVL1, the second vertical connection line DVL2, and the third vertical connection line DVL3 through the first connection contact hole DHL-CNT1, and can be electrically connected to a corresponding one of the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the second connection contact hole DHL-CNT2.

[0084] Figure 10 It is located in the area included Figure 7 The equivalent circuit diagram of the pixels in the display area DA of the display panel 10 in the display module 11. (See diagram below.) Figure 10 As shown, the pixel circuit PC connected to the light-emitting diode (LED) may include multiple transistors and multiple capacitors. As an example, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a holding capacitor Chd.

[0085] The first transistor T1 can be a drive transistor that outputs a drive current corresponding to the data signal, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be switching transistors that transmit signals through on / off operations. The first terminal (first electrode) of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be one of the source region and the drain region, and the second terminal (second electrode) can be the other.

[0086] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a p-channel metal-oxide-semiconductor field-effect transistor (PMOS), and the remaining transistors can be n-channel metal-oxide-semiconductor field-effect transistors (NMOS). As an example, the fifth transistor T5 can be a PMOS, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 can be NMOS. Optionally, the fifth transistor T5 and the sixth transistor T6 can be PMOS, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be NMOS. Optionally, all transistors can be NMOS, or all transistors can be PMOS.

[0087] At least one of the transistors can be a transistor with a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and the remaining transistors can be transistors with an oxide semiconductor layer. As used herein, the LTPS semiconductor layer can be a specialized form of silicon used to produce thin-film transistors for high-performance display panels. Unlike amorphous silicon, which lacks a crystalline structure, LTPS consists of many small silicon crystals that allow for significantly better conductivity. LTPS can be fabricated using processes such as laser annealing to crystallize silicon at relatively low temperatures. The resulting LTPS semiconductor layer can exhibit high electron mobility, meaning that charge moves through it quickly and efficiently. This property enables the production of transistors that can switch pixels on and off more quickly, making LTPS ideal for high-resolution, high-refresh-rate displays provided in modern smartphones, tablets, and advanced monitors. Because transistors can be made smaller and more efficient, LTPS technology also helps reduce power consumption and allows complex circuitry to be integrated directly onto the display itself.

[0088] As an example, the fifth transistor T5 may include a semiconductor layer comprising polycrystalline silicon with high reliability, and each of the remaining transistors may include an oxide semiconductor layer with characteristics of high carrier mobility and low leakage current. Below, the case is described where the fifth transistor T5 is a PMOS comprising a silicon semiconductor layer and the remaining transistors are NMOS comprising oxide semiconductor layers.

[0089] The pixel circuit PC can be electrically connected to the gate line that transmits signals to the gate electrode of each of the transistors. As an example, the pixel circuit PC can be connected to the scan line GWL that transmits the scan signal GW, the first reference gate line GRL that transmits the first reference signal GR, the second reference gate line GCL that transmits the second reference signal GC, the first transmit control line EML that transmits the first transmit control signal EM, the second transmit control line EMBL that transmits the second transmit control signal EMB, and the data line DL that transmits the data signal DATA. Furthermore, the pixel circuit PC can be connected to the drive voltage line PL that transmits the drive voltage ELVDD, the reference voltage line VRL that transmits the reference voltage VREF, and the initialization voltage line VL that transmits the initialization voltage VINT.

[0090] A first transistor T1, acting as a driving transistor, can be electrically connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a first gate electrode G1 connected to the first node N1, a first terminal electrically connected to the driving voltage line PL, and a second terminal connected to the second node N2. The first terminal may be a drain region D, and the second terminal may be a source region S. The first terminal of the first transistor T1 can be electrically connected to the driving voltage line PL via a fifth transistor T5, and the second terminal of the first transistor T1 can be electrically connected to the pixel electrode of the light-emitting diode (LED) via a sixth transistor T6. The first transistor T1 can receive a data signal DATA according to the switching operation of the second transistor T2 and is configured to control the amount of the driving current Id flowing through the LED.

[0091] A second transistor T2, acting as a data write transistor, can be electrically connected between the data line DL and the first node N1. The second transistor T2 may include a gate electrode, a first terminal, and a second terminal, wherein the gate electrode is connected to the scan line GWL, the first terminal is connected to the data line DL, and the second terminal is connected to the first node N1. The second transistor T2 can be turned on according to the scan signal GW transmitted to the scan line GWL to electrically connect the data line DL to the first node N1 and transmit the data signal DATA to the first node N1, which is transmitted from the data line DL.

[0092] A third transistor T3, serving as the first initialization transistor, can be electrically connected between the first node N1 and the reference voltage line VRL. The third transistor T3 may include a gate electrode, a first terminal, and a second terminal, wherein the gate electrode is connected to the first reference gate line GRL, the first terminal is connected to the first node N1, and the second terminal is connected to the reference voltage line VRL. The third transistor T3 can be turned on according to a first reference signal GR transmitted to the first reference gate line GRL, and can transmit a reference voltage VREF to the first node N1, which originates from the reference voltage line VRL.

[0093] The fourth transistor T4, serving as the second initialization transistor, can be electrically connected between the first transistor T1 and the initialization voltage line VL. For example, the fourth transistor T4 can be electrically connected between the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 may include a gate electrode, a first terminal, and a second terminal, wherein the gate electrode is connected to the first emitter control line EML, the first terminal is connected to the second terminal of the sixth transistor T6 and the light-emitting diode (LED), and the second terminal is connected to the initialization voltage line VL. The fourth transistor T4 can be turned on according to a first emitter control signal EM transmitted to the first emitter control line EML, and can transmit an initialization voltage VINT to the pixel electrode of the LED, which originates from the initialization voltage line VL. For example, the fourth transistor T4 can initialize the potential of the pixel electrode of the LED to the initialization voltage VINT.

[0094] A fifth transistor T5, serving as the emitter control transistor, can be electrically connected between the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate electrode, a first terminal, and a second terminal, wherein the gate electrode is connected to the first emitter control line EML, the first terminal is connected to the drive voltage line PL, and the second terminal is connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to a first emitter control signal EM from the first emitter control line EML.

[0095] A sixth transistor T6, serving as the operation control transistor, can be connected between the first transistor T1 and the light-emitting diode (LED). The sixth transistor T6 may include a gate electrode, a first terminal, and a second terminal, wherein the gate electrode is connected to a second emission control line EMBL, the first terminal is connected to a second node N2, and the second terminal is connected to the LED. The sixth transistor T6 can be turned on according to a second emission control signal EMB from the second emission control line EMBL, and the second node N2 can be electrically connected to the pixel electrode of the LED.

[0096] For example, although in Figure 10 The diagram shows a fifth transistor T5 operating in response to a first transmit control signal EM, and a sixth transistor T6 operating in response to a second transmit control signal EMB; however, the invention is not necessarily limited to this. As an example, the fifth transistor T5 and the sixth transistor T6 may operate in response to the same transmit control signal.

[0097] For example, the first reference signal GR can be substantially synchronized with the scan signal GW of the pixel circuit PC in the previous row. The second reference signal GC, described below, can also be substantially synchronized with the scan signal GW of the pixel circuit PC in the previous row, or substantially synchronized with the scan signal GW or the first reference signal GR of the pixel circuit PC in the next row.

[0098] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2. For example, the pixel circuit PC included in the display panel according to this embodiment can be a source follower type circuit, wherein the storage capacitor Cst is connected between the first node N1 and the second node N2. The first storage electrode CEs1 of the storage capacitor Cst can be connected to the first node N1, and the second storage electrode CEs2 can be connected to the second node N2. The electrodes constituting the capacitor can be referred to as capacitor electrodes. The storage capacitor Cst can store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal DATA. As used herein, the source follower type circuit can be a configuration in which an input signal is applied to the gate and an output is obtained from the source terminal. In this setting, the voltage at the source closely follows the voltage at the gate, typically reduced slightly due to the threshold voltage of the transistor. Although it does not amplify the voltage, the circuit acts as a buffer, maintaining signal strength while allowing it to drive low-impedance components. This makes it particularly useful in display technology, where it helps stabilize the voltage delivered to the pixel elements, ensuring consistent image quality.

[0099] A holding capacitor Chd can be connected between the seventh transistor T7 and the second node N2. The first holding electrode CEh1 of the holding capacitor Chd can be electrically connected to the second node N2, and the second holding electrode CEh2 can be electrically connected to the reference voltage line VRL through the seventh transistor T7. The holding capacitor Chd ensures that the voltage at the second node N2 of the first transistor T1 does not fluctuate and remains constant when the surrounding signal fluctuates.

[0100] A seventh transistor T7, serving as the third initialization transistor, can be connected between the second holding electrode CEh2 of the holding capacitor Chd and the reference voltage line VRL. The seventh transistor T7 may include a gate electrode, a first terminal, and a second terminal, wherein the gate electrode is connected to the second reference gate line GCL, the first terminal is connected to the second holding electrode CEh2 of the holding capacitor Chd, and the second terminal is connected to the reference voltage line VRL. The seventh transistor T7 can be turned on according to a second reference signal GC transmitted to the second reference gate line GCL, and can transmit a reference voltage VREF to the second holding electrode CEh2 of the holding capacitor Chd, which originates from the reference voltage line VRL.

[0101] A light-emitting diode (LED) may include pixel electrodes and a common electrode above the pixel electrodes, wherein the pixel electrodes are electrically connected to a second node N2 via a sixth transistor T6, and the common electrode may receive a common voltage ELVSS. The common electrode may be a single, integral body above multiple LEDs. As used herein, the term "integral body" may be intended to refer to a single, uninterrupted structure excluding individual portions.

[0102] Despite Figure 10 The diagram shows a pixel circuit PC comprising seven transistors and two capacitors, but the invention is not necessarily limited thereto. As an example, the pixel circuit PC may include five transistors and two capacitors. The pixel circuit PC may also include six transistors and one or two capacitors.

[0103] Figure 11 This is a schematic arrangement diagram showing the positions of transistors, capacitors, etc., in the pixels located in the display area of ​​the display panel 10 included in the display module 11. For ease of description, Figure 11 Two pixel circuits are shown, for example, a first pixel circuit PC1 and a second pixel circuit PC2 located in the same row in a first direction (e.g., the x-axis direction). However, the invention is not necessarily limited to this. Furthermore, although in Figure 11 The diagram shows a first pixel circuit PC1 and a second pixel circuit PC2 that are approximately mirror-symmetrical about each other with respect to a dashed line IML extending in a second direction (e.g., the y-axis direction), but the invention is not necessarily limited thereto. The display panel 10 may include a plurality of pixel circuits arranged to form rows in a first direction (e.g., the x-axis direction) and columns in a second direction (e.g., the y-axis direction).

[0104] like Figure 11 As shown, each of the first pixel circuit PC1 and the second pixel circuit PC2 may include a transistor and a capacitor. As an example, each of the first pixel circuit PC1 and the second pixel circuit PC2 may include the components described above. Figure 10 The first transistor T1 to the seventh transistor T7, the storage capacitor Cst, and the holding capacitor Chd are described. For example, when considering the first pixel circuit PC1 and the second pixel circuit PC2, the two first transistors T1 can be arranged adjacent to each other in a first direction (e.g., the x-axis direction).

[0105] Gate lines electrically connected to the first pixel circuit PC1 and the second pixel circuit PC2 (e.g., scan line GWL, first reference gate line GRL, second reference gate line GCL, first emission control line EML, and second emission control line EMBL) may extend substantially in a first direction (e.g., the x-axis direction). Furthermore, the horizontal connection line DHL (see...) Figure 19It can also extend generally in the first direction (e.g., the x-axis direction).

[0106] The first pixel circuit PC1 can be electrically connected to the data line DL passing through the first pixel circuit PC1, and the second pixel circuit PC2 can be electrically connected to the data line DL passing through the second pixel circuit PC2. The data line DL can extend substantially in a second direction (e.g., the y-direction). The data line DL electrically connected to the first pixel circuit PC1 and the data line DL electrically connected to the second pixel circuit PC2 can be symmetrical to each other with respect to the aforementioned dashed line IML.

[0107] The first pixel circuit PC1 can be electrically connected to voltage lines, such as the reference voltage line VRL and the initialization voltage line VL passing through the first pixel circuit PC1. The second pixel circuit PC2 can be electrically connected to voltage lines, such as the reference voltage line VRL and the initialization voltage line VL passing through the second pixel circuit PC2. The reference voltage line VRL and the initialization voltage line VL electrically connected to the first pixel circuit PC1 and the reference voltage line VRL and the initialization voltage line VL electrically connected to the second pixel circuit PC2 can be symmetrical to each other with respect to the aforementioned dashed line IML. Each of the reference voltage line VRL and the initialization voltage line VL can extend substantially in a second direction (e.g., the y-axis direction). For convenience, the initialization voltage line VL passing through the first pixel circuit PC1 can be referred to as the first initialization voltage line, and the initialization voltage line VL passing through the second pixel circuit PC2 can be referred to as the second initialization voltage line. For example, the first initialization voltage line and the second initialization voltage line extending in the second direction (e.g., the y-axis direction) can be arranged alternately in a first direction (e.g., the x-axis direction).

[0108] The vertical connector line (DVL) can also extend in a second direction (e.g., the y-axis direction). The vertical connector line (DVL) can correspond to a reference. Figure 8 or Figure 9 The described data transmission line DTL includes, for example, one of the first vertical connection line DVL1, the second vertical connection line DVL2, the third vertical connection line DVL3, the first additional vertical connection line DVL1', the second additional vertical connection line DVL2', and the third additional vertical connection line DVL3'. In this case, the vertical connection line DVL can be electrically connected to... Figure 11 The first pixel circuit PC1 and the second pixel circuit PC2 shown are located in different columns of pixel circuits via data lines DL to transmit data signals to the pixel circuits in different columns. Optionally, the first pixel circuit PC1 or the second pixel circuit PC2 is not located in... Figure 8 or Figure 9In the case where the vertical connecting line DVL is located in the center of the display area DA instead of near the corner of the display area DA, it can be a dummy line to which no electrical signal is applied or a dummy line to which a preset electrical signal is applied when needed.

[0109] For example, the horizontal connector line DHL described below can correspond to the reference. Figure 8 or Figure 9 The described data transmission line DTL is a portion of, for example, one of the first horizontal connection line DHL1, the second horizontal connection line DHL2, and the third horizontal connection line DHL3. In this case, the horizontal connection line DHL, together with the vertical connection line DVL, can be electrically connected to... Figure 11 The first pixel circuit PC1 and the second pixel circuit PC2 shown are located in different columns of pixel circuits via data lines DL to transmit data signals to the pixel circuits in different columns. Optionally, the first pixel circuit PC1 or the second pixel circuit PC2 is not located in... Figure 8 or Figure 9 In the case where the horizontal connecting line DHL is located in the center of the display area DA rather than near the corner of the display area DA, it can be a dummy line that does not apply an electrical signal to it or a dummy line that applies a preset electrical signal to it when needed.

[0110] Figures 12 to 20 It is used for Figure 11 A schematic arrangement of elements such as transistors and capacitors in each layer of the display panel 10 shown. Figure 21 yes Figure 11 A schematic diagram of the pixel electrodes of the display panel 10. Furthermore, Figure 22 It is along Figures 11 to 21 A schematic cross-sectional view taken by line B-B'.

[0111] For ease of description, the case in which the first pixel circuit PC1 is located in the i-th row and j-th column and the second pixel circuit PC2 is located in the i-th row and j+1-th column is described.

[0112] The display panel 10 may include a circuit layer and a display element layer. The circuit layer includes transistors and capacitors disposed on the substrate 100, and the display element layer is disposed on the circuit layer and includes light-emitting diodes (LEDs). The circuit layer may include reference... Figure 10 and Figure 11 Described transistors and capacitors.

[0113] like Figure 12As shown, a bottom metal layer 1010 may be disposed on a substrate 100. The bottom metal layer 1010 may include a first portion 1011, a second portion 1012 and a third portion 1013, wherein the first portion 1011 extends in a second direction (e.g., the y-axis direction), and the second portion 1012 and the third portion 1013 extend in a first direction (e.g., the x-axis direction).

[0114] The first portion 1011 may be located on the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2. The second portion 1012 and the third portion 1013 of the bottom metal layer 1010 may be located on opposite sides, with the first portion 1011 interposed between them. The second portion 1012 and the third portion 1013 may extend integrally in a first direction (e.g., the x-direction) and may be partially curved. The bottom metal layer 1010 may include a metallic material. For example, the bottom metal layer 1010 may include at least one material selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As an example, the bottom metal layer 1010 may have a single-layer structure including molybdenum, a double-layer structure in which molybdenum and titanium layers are stacked, or a triple-layer structure in which titanium, aluminum, and titanium layers are stacked.

[0115] The bottom metal layer 1010 can have a constant voltage level. As an example, the bottom metal layer 1010 can be related to the above reference. Figure 10 The described drive voltage line PL has the same voltage. For example, the drive voltage ELVDD can be applied to the bottom metal layer 1010. For this purpose, the bottom metal layer 1010 can be electrically connected, for example, in the peripheral region PA to a portion of the drive voltage line PL or the first power line 15. The bottom metal layer 1010 can shield at least a portion of the light traveling to the fifth semiconductor layer A5 of the fifth transistor T5 and protect the fifth transistor T5 from electrostatic discharge (ESD).

[0116] A buffer layer 101 may be disposed on the bottom metal layer 1010 to cover the bottom metal layer 1010. The buffer layer 101 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The buffer layer 101 may have a single-layer structure or a multi-layer structure.

[0117] Figure 13 The silicon semiconductor layer 1110 shown can be disposed on the buffer layer 101. The silicon semiconductor layer 1110 may include silicon, for example, polycrystalline silicon.

[0118] like Figure 13As shown, the silicon semiconductor layer 1110 may have an isolated shape. As used herein, the phrase "isolated shape" may mean that the structure is physically separate and not connected to similar structures that may be nearby or on the same layer. Furthermore, the silicon semiconductor layer 1110 may include a main portion MP having a shape extending generally in a first direction (e.g., the x-axis direction) and an extension portion ETP having a shape extending in a second direction (e.g., the y-axis direction) intersecting the first direction. The main portion MP and the extension portion ETP may be a single, integral body. The main portion MP of the silicon semiconductor layer 1110 may intersect the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2. Furthermore, the extension portion ETP of the silicon semiconductor layer 1110 may overlap with the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2 in a plan view. In a plan view, the extension portion ETP may be located between the first transistor T1 of the first pixel circuit PC1 and the second transistor T2 of the second pixel circuit PC2. The silicon semiconductor layer 1110 may include a fifth semiconductor layer A5 for each of the first pixel circuit PC1 and the second pixel circuit PC2. In other words, the fifth semiconductor layer A5 of the first pixel circuit PC1 and the fifth semiconductor layer A5 of the second pixel circuit PC2 can be an integral part of the same body.

[0119] When the silicon semiconductor layer 1110 has only the main portion MP and no extension portion ETP, the area occupied by the silicon semiconductor layer 1110 in the area of ​​the first pixel circuit PC1 and the area of ​​the second pixel circuit PC2 becomes very small. In this case, during the process of forming a layer comprising silicon semiconductor material on approximately the entire surface of the substrate 100 and patterning the layer with a photoresist or the like to form the main portion MP, a large amount of photoresist is removed, and therefore, a large amount of time is consumed, and furthermore, defects may occur where the main portion MP is not formed in the expected shape. Conversely, in the display panel 10 according to this embodiment and the electronic device 1 including the display panel 10, because the silicon semiconductor layer 1110 includes both the extension portion ETP and the main portion MP, the area occupied by the silicon semiconductor layer 1110 in the area of ​​the first pixel circuit PC1 and the area of ​​the second pixel circuit PC2 can be increased. In addition, the occurrence of defects during the manufacturing process can be effectively prevented or minimized.

[0120] The silicon semiconductor layer 1110 may overlap with the bottom metal layer 1010. As an example, the main portion MP of the silicon semiconductor layer 1110 may substantially overlap with the third portion 1013 of the bottom metal layer 1010, and the extended portion ETP of the silicon semiconductor layer 1110 may overlap with the first portion 1011 of the bottom metal layer 1010. Therefore, the fifth semiconductor layer A5 of each of the first pixel circuit PC1 and the second pixel circuit PC2 may overlap with the third portion 1013 of the bottom metal layer 1010.

[0121] A first gate insulating layer 103 may be disposed on the silicon semiconductor layer 1110 to cover the silicon semiconductor layer 1110. The first gate insulating layer 103 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The first gate insulating layer 103 may have a single-layer structure or a multi-layer structure.

[0122] Figure 14 The first gate layer 1200 shown can be disposed on the first gate insulating layer 103. For example, for convenience, Figure 14 The first gate layer 1200 and the silicon semiconductor layer 1110 beneath it are shown in an overlapping manner. Figure 14 The diagram shows a first gate layer 1200 including a first emission control line EML, a first conductive layer 1210, a second conductive layer 1220, a third conductive layer 1230, and a fourth conductive layer 1240. The first emission control line EML, first conductive layer 1210, second conductive layer 1220, third conductive layer 1230, and fourth conductive layer 1240 of the first pixel circuit PC1 and the first emission control line EML, first conductive layer 1210, second conductive layer 1220, third conductive layer 1230, and fourth conductive layer 1240 of the second pixel circuit PC2 are generally symmetrical to each other with respect to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2.

[0123] like Figure 14 As shown, the first conductive layer 1210, the second conductive layer 1220, the third conductive layer 1230, and the fourth conductive layer 1240 may be spaced apart from each other. The first conductive layer 1210, the second conductive layer 1220, the third conductive layer 1230, and the fourth conductive layer 1240 may comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure comprising these materials. Elements included in the first gate layer 1200 may be formed simultaneously using the same material, and therefore may have the same layer structure.

[0124] The first emission control line EML may extend generally in a first direction (e.g., the x-axis direction) to traverse the first pixel circuit PC1 and the second pixel circuit PC2. The first emission control line EML may traverse pixel circuits arranged in the same row as the first pixel circuit PC1 and the second pixel circuit PC2.

[0125] The first emission control line EML may include the fifth gate electrode G5 of the fifth transistor T5 in each of the first pixel circuit PC1 and the second pixel circuit PC2. A portion of the first emission control line EML may protrude to overlap with the fifth semiconductor layer A5 of the fifth transistor T5, and the protruding portion of the first emission control line EML may correspond to the fifth gate electrode G5 of the fifth transistor T5. The fifth semiconductor layer A5 of the fifth transistor T5 may include a channel region C5 overlapping with the fifth gate electrode G5 and conductive regions S5 and D5 located on two opposite sides of the channel region C5, wherein the conductive regions S5 and D5 are made conductive by doping with impurities or by plasma treatment. One of the conductive regions S5 and D5 may be a source region, and the other may be a drain region. The source region and the drain region may correspond to the source electrode and the drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the nature of the transistor.

[0126] The first conductive layer 1210 can have an isolated shape, and the first conductive layer 1210 can be a single unit in two adjacent pixel circuits. As an example, such as... Figure 14 As shown, the first conductive layer 1210 belonging to the first pixel circuit PC1 can be integrally formed with the first conductive layer 1210 of the pixel circuit located in the -x direction (e.g., the pixel circuit located in the (j-1)th column), and the first conductive layer 1210 belonging to the second pixel circuit PC2 can be integrally formed with the first conductive layer 1210 of the pixel circuit located in the +x direction (e.g., the pixel circuit located in the (j+2)th column). Each of the second conductive layer 1220 and the third conductive layer 1230 can have an isolated shape. The fourth conductive layer 1240 can also have an isolated shape and is integrally formed with the first pixel circuit PC1 and the pixel circuit in the (j-1)th column, and furthermore, with the second pixel circuit PC2 and the pixel circuit in the (j+2)th column. In the first pixel circuit PC1 and the second pixel circuit PC2, the first conductive layer 1210, the second conductive layer 1220, the third conductive layer 1230, and the fourth conductive layer 1240 can be symmetrical to each other with respect to the aforementioned dashed line IML.

[0127] The first conductive layer 1210 may be connected to the third semiconductor layer A3 described below (see below) Figure 17The first conductive layer 1210 can shield at least a portion of the light traveling toward the third semiconductor layer A3 of the third transistor T3 and protect the third transistor T3 from electrostatic discharge (ESD).

[0128] The second conductive layer 1220 located in each of the first pixel circuit PC1 and the second pixel circuit PC2 may have an isolated shape and be positioned adjacent to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2. The second conductive layer 1220 may be the second holding electrode CEh2 of the holding capacitor Chd.

[0129] The third conductive layer 1230 located in each of the first pixel circuit PC1 and the second pixel circuit PC2 can be the first storage electrode CEs1 of the storage capacitor Cst.

[0130] The second gate insulating layer 105 may cover the first gate layer 1200. The second gate insulating layer 105 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The second gate insulating layer 105 may have a single-layer structure or a multi-layer structure. When necessary, the second gate insulating layer 105 may comprise a material different from that of the first gate insulating layer 103. As an example, the first gate insulating layer 103 may comprise silicon oxide, and the second gate insulating layer 105 may comprise silicon nitride.

[0131] Figure 15 The second gate layer 1300 shown can be disposed on the second gate insulating layer 105. Figure 15 The diagram shows that the second gate layer 1300 includes a fifth conductive layer 1310 and a sixth conductive layer 1320. The fifth conductive layer 1310 and the sixth conductive layer 1320 of the first pixel circuit PC1 and the fifth conductive layer 1310 and the sixth conductive layer 1320 of the second pixel circuit PC2 are approximately symmetrical to each other with respect to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2.

[0132] like Figure 15 As shown, the fifth conductive layer 1310 and the sixth conductive layer 1320 may be spaced apart from each other. The fifth conductive layer 1310 and the sixth conductive layer 1320 may comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may comprise a single-layer structure or a multi-layer structure containing the above materials. Elements included in the second gate layer 1300 may be formed simultaneously using the same material, and therefore may have the same layer structure.

[0133] The fifth conductive layer 1310 located in each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape. The fifth conductive layer 1310 in the first pixel circuit PC1 and the fifth conductive layer 1310 in the second pixel circuit PC2 can be spaced apart from each other and substantially symmetrical to each other with respect to the aforementioned dashed line IML. In the plan view, the extension portion ETP of the silicon semiconductor layer 1110 can be positioned between the fifth conductive layer 1310 in the first pixel circuit PC1 and the fifth conductive layer 1310 in the second pixel circuit PC2. The fifth conductive layer 1310 of the first pixel circuit PC1 can overlap with the second conductive layer 1220 and the third conductive layer 1230 located below it in the first pixel circuit PC1. The fifth conductive layer 1310 can be the first holding electrode CEh1 of the holding capacitor Chd and the second storage electrode CEs2 of the storage capacitor Cst. For example, the first holding electrode CEh1 of the holding capacitor Chd and the second storage electrode CEs2 of the storage capacitor Cst can be an integral body. Therefore, the second conductive layer 1220 and the fifth conductive layer 1310 can form a holding capacitor Chd, and the third conductive layer 1230 and the fifth conductive layer 1310 can form a storage capacitor Cst.

[0134] The sixth conductive layer 1320 located in each of the first pixel circuit PC1 and the second pixel circuit PC2 can also have an isolated shape. The sixth conductive layer 1320 can be connected to the second semiconductor layer A2 described below (see...). Figure 17 The sixth conductive layer 1320 can shield at least a portion of the light traveling toward the second semiconductor layer A2 of the second transistor T2 and protect the second transistor T2 from electrostatic discharge (ESD).

[0135] The first interlayer insulating layer 107 may cover the second gate layer 1300. The first interlayer insulating layer 107 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The first interlayer insulating layer 107 may have a single-layer structure or a multi-layer structure. As an example, the first interlayer insulating layer 107 may have a stacked structure comprising layers comprising silicon oxide and layers comprising silicon nitride.

[0136] Figure 16 The intermediate conductive layer 1400 shown can be disposed on the first interlayer insulating layer 107. Figure 16 The diagram shows an intermediate conductive layer 1400 including a shielding layer 1410. The shielding layers 1410 of the first pixel circuit PC1 and the second pixel circuit PC2 are approximately symmetrical to each other with respect to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2.

[0137] The shielding layer 1410 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single-layer structure or a multi-layer structure comprising the above materials. As an example, the shielding layer 1410 may have a single-layer structure comprising molybdenum or titanium.

[0138] The shielding layer 1410 located in each of the first pixel circuit PC1 and the second pixel circuit PC2 may have an isolated shape. The shielding layer 1410 may be connected to the first semiconductor layer A1 described below (see [link to description]). Figure 17 The shielding layer 1410 can shield at least a portion of the light traveling toward the first semiconductor layer A1 of the first transistor T1 and protect the first transistor T1 from electrostatic discharge (ESD). The shielding layer 1410 can be connected to the fifth conductive layer 1310 beneath it via contact holes 1410CT formed in the first interlayer insulating layer 107. Therefore, the shielding layer 1410 can have the same potential as the first holding electrode CEh1 of the holding capacitor Chd and the fifth conductive layer 1310, which is the second storage electrode CEs2 of the storage capacitor Cst.

[0139] The second interlayer insulating layer 108 may be disposed above the intermediate conductive layer 1400. The second interlayer insulating layer 108 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The second interlayer insulating layer 108 may have a single-layer structure or a multi-layer structure. As an example, the second interlayer insulating layer 108 may have a stacked structure comprising layers comprising silicon oxide and layers comprising silicon nitride.

[0140] Figure 17 The semiconductor layer 1500 shown may be disposed on the second interlayer insulating layer 108. The semiconductor layer 1500 may include an oxide semiconductor. The oxide semiconductor may include at least one selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, the oxide semiconductor may include ITZO (InSnZnO) or IGZO (InGaZnO). Figure 17 The diagram shows a semiconductor layer 1500 comprising a first oxide semiconductor pattern 1510, a second oxide semiconductor pattern 1520, a third oxide semiconductor pattern 1530, and a fourth oxide semiconductor pattern 1540. For example... Figure 17As shown, the first oxide semiconductor pattern 1510, the second oxide semiconductor pattern 1520, the third oxide semiconductor pattern 1530 and the fourth oxide semiconductor pattern 1540 may be spaced apart from each other.

[0141] The first oxide semiconductor pattern 1510 located in each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape. The first oxide semiconductor pattern 1510 may include a first semiconductor layer A1, a fourth semiconductor layer A4, and a sixth semiconductor layer A6. For example, the first semiconductor layer A1, the fourth semiconductor layer A4, and the sixth semiconductor layer A6 of the first pixel circuit PC1 can be a single, integral body, and the first semiconductor layer A1, the fourth semiconductor layer A4, and the sixth semiconductor layer A6 of the second pixel circuit PC2 can also be a single, integral body. The first oxide semiconductor pattern 1510 can have a shape that is bent several times.

[0142] The first semiconductor layer A1, the fourth semiconductor layer A4, and the sixth semiconductor layer A6 included in the first oxide semiconductor pattern 1510 can be respectively referenced below. Figure 18 The first gate electrode 1610, the seventh conductive layer 1620, and the second emission control line EMBL are described as overlapping. For example, the portion of the first oxide semiconductor pattern 1510 that overlaps with the first gate electrode 1610 may be the first semiconductor layer A1, the portion of the first oxide semiconductor pattern 1510 that overlaps with the seventh conductive layer 1620 may be the fourth semiconductor layer A4, and the portion of the first oxide semiconductor pattern 1510 that overlaps with the second emission control line EMBL may be the sixth semiconductor layer A6.

[0143] For example, in a planar view, the shapes of the first oxide semiconductor pattern 1510 of the first pixel circuit PC1 and the first oxide semiconductor pattern 1510 of the second pixel circuit PC2 can be different from each other. The first oxide semiconductor pattern 1510 of the first pixel circuit PC1 can be an integral part of the first oxide semiconductor pattern of a pixel circuit located in the same row as the first pixel circuit PC1 and in an adjacent column (e.g., a pixel circuit extending in the direction of a pixel circuit located in the i-th row and j-1-th column), which is located in the j-1-th column. In contrast, the first oxide semiconductor pattern 1510 of the second pixel circuit PC2 can have an isolated shape. The first oxide semiconductor pattern 1510 of the first pixel circuit PC1 can also have an isolated shape when needed. In this case, the first oxide semiconductor pattern 1510 of the first pixel circuit PC1 and the first oxide semiconductor pattern 1510 of the second pixel circuit PC2 can be approximately symmetrical to each other with respect to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2.

[0144] The second oxide semiconductor pattern 1520 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape and be a single unit in the two adjacent pixel circuits. As an example, such as Figure 17 As shown, the second oxide semiconductor pattern 1520 belonging to the first pixel circuit PC1 can be integrally formed with the second oxide semiconductor pattern 1520 of the pixel circuit located in the -x direction (e.g., the pixel circuit located in column j-1), and the second oxide semiconductor pattern 1520 belonging to the second pixel circuit PC2 can be integrally formed with the second oxide semiconductor pattern 1520 of the pixel circuit located in the +x direction (e.g., the pixel circuit located in column j+2). The second oxide semiconductor patterns 1520 of the first pixel circuit PC1 and the second oxide semiconductor pattern 1520 of the second pixel circuit PC2 can be approximately symmetrical to each other with respect to the aforementioned dashed line IML.

[0145] The second oxide semiconductor pattern 1520 may include a second semiconductor layer A2 of the second transistor T2 and a third semiconductor layer A3 of the third transistor T3. For example, the second semiconductor layer A2 of the second transistor T2 and the third semiconductor layer A3 of the third transistor T3 may be integrally connected to each other. The second semiconductor layer A2 and the third semiconductor layer A3 of the second oxide semiconductor pattern 1520 may be related to the following reference. Figure 18 The scan line GWL and the first reference gate line GRL are described as overlapping. For example, the portion of the second oxide semiconductor pattern 1520 that overlaps with the scan line GWL may be the second semiconductor layer A2, and the portion of the second oxide semiconductor pattern 1520 that overlaps with the first reference gate line GRL may be the third semiconductor layer A3.

[0146] The third oxide semiconductor pattern 1530 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape and be a single unit in the two adjacent pixel circuits. As an example, such as Figure 17 As shown, the third oxide semiconductor pattern 1530 belonging to the first pixel circuit PC1 can be integrally formed with the third oxide semiconductor pattern 1530 of the pixel circuit disposed in the -x direction (e.g., the pixel circuit disposed in the j-1 column), and the third oxide semiconductor pattern 1530 belonging to the second pixel circuit PC2 can be integrally formed with the third oxide semiconductor pattern 1530 of the pixel circuit disposed in the +x direction (e.g., the pixel circuit disposed in the j+2 column). The third oxide semiconductor pattern 1530 of the first pixel circuit PC1 and the third oxide semiconductor pattern 1530 of the second pixel circuit PC2 can be approximately symmetrical to each other with respect to the aforementioned dashed line IML.

[0147] The third oxide semiconductor pattern 1530 may include a seventh semiconductor layer A7 of the seventh transistor T7. The seventh semiconductor layer A7 of the third oxide semiconductor pattern 1530 may be related to the following reference... Figure 18 The second reference gate line GCL is described as overlapping. For example, the portion of the third oxide semiconductor pattern 1530 that overlaps with the second reference gate line GCL may be the seventh semiconductor layer A7.

[0148] The fourth oxide semiconductor pattern 1540 can be disposed in the first pixel circuit PC1. The fourth oxide semiconductor pattern 1540 can be disposed at a position corresponding to one end of the first oxide semiconductor pattern 1510 in the second pixel circuit PC2, and can correspond to the type of dummy electrode.

[0149] Each of the first oxide semiconductor pattern 1510, the second oxide semiconductor pattern 1520, the third oxide semiconductor pattern 1530, and the fourth oxide semiconductor pattern 1540 may include at least a partially conductive region. As an example, at least a portion of each of the first oxide semiconductor pattern 1510, the second oxide semiconductor pattern 1520, the third oxide semiconductor pattern 1530, and the fourth oxide semiconductor pattern 1540 may be doped or plasma-treated, and thus the treated portion may become conductive.

[0150] The third gate insulating layer 109 may cover the semiconductor layer 1500. The third gate insulating layer 109 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The third gate insulating layer 109 may have a single-layer structure or a multi-layer structure.

[0151] Figure 18 The third gate layer 1600 shown can be disposed on the third gate insulating layer 109. For convenience, Figure 18 The third gate layer 1600 and the semiconductor layer 1500 beneath it are shown in an overlapping manner. Figure 18 The diagram shows a third gate layer 1600 comprising a first gate electrode 1610, a seventh conductive layer 1620, an eighth conductive layer 1630, a first reference gate line GRL, a scan line GWL, a second reference gate line GCL, a second emission control line EMBL, and an auxiliary power line 1640. The components in the first pixel circuit PC1 and the second pixel circuit PC2 are approximately symmetrical to each other with respect to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2.

[0152] The first gate electrode 1610, the seventh conductive layer 1620, the eighth conductive layer 1630, the first reference gate line GRL, the scan line GWL, the second reference gate line GCL, the second emitter control line EMBL, and the auxiliary power line 1640 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including these materials. Elements included in the third gate layer 1600 may be formed simultaneously using the same materials, and therefore may have the same layer structure.

[0153] The first gate electrode 1610 of each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape and is the gate electrode of the first transistor T1. The portion of the first oxide semiconductor pattern 1510 that overlaps with the first gate electrode 1610 can be a channel region C1, and the two opposite sides of the channel region C1 can be conductive regions S1 and D1, which are made conductive by doping with impurities or by plasma treatment. One of the conductive regions S1 and D1 can be a source region, and the other can be a drain region. The source region and the drain region can correspond to the source electrode and the drain electrode. The positions of the source region and the drain region can be interchanged according to the nature of the transistor.

[0154] The seventh conductive layer 1620 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape and be a single unit in the two adjacent pixel circuits. As an example, such as Figure 18 As shown, the seventh conductive layer 1620 belonging to the first pixel circuit PC1 can be an integral body with the seventh conductive layer 1620 of the pixel circuit disposed in the -x direction (e.g., the pixel circuit disposed in the j-1 column), and the seventh conductive layer 1620 belonging to the second pixel circuit PC2 can be an integral body with the seventh conductive layer 1620 of the pixel circuit disposed in the +x direction (e.g., the pixel circuit disposed in the j+2 column).

[0155] The seventh conductive layer 1620 can be the gate electrode of the fourth transistor T4. A portion of the seventh conductive layer 1620 can correspond to the fourth gate electrode G4. The portion of the first oxide semiconductor pattern 1510 that overlaps with the seventh conductive layer 1620 can be the channel region C4, and the two opposite sides of the channel region C4 can be conductive regions S4 and D4. The conductive regions S4 and D4 are made conductive by doping with impurities or by plasma treatment. One of the conductive regions S4 and D4 can be the source region, and the other can be the drain region. The source region and the drain region can correspond to the source electrode and the drain electrode. The positions of the source region and the drain region can be interchanged according to the nature of the transistor. The seventh conductive layer 1620 can be connected to the first emitter control line EML through contact holes 1620CT formed in the second gate insulating layer 105, the first interlayer insulating layer 107, the second interlayer insulating layer 108, and the third gate insulating layer 109.

[0156] The eighth conductive layer 1630 can be disposed above the first pixel circuit PC1 and the second pixel circuit PC2 and has an isolated shape. The eighth conductive layer 1630 can be connected to the horizontal connection line DHL described below, and can electrically connect the broken portions of the horizontal connection line DHL. This is described below.

[0157] The first reference gate line GRL can extend generally in a first direction (e.g., the x-axis direction) to traverse the first pixel circuit PC1 and the second pixel circuit PC2. The first reference gate line GRL can traverse pixel circuits arranged in the same row as the first pixel circuit PC1 and the second pixel circuit PC2. The first reference gate line GRL can be connected to the first conductive layer 1210 through contact holes GRLCT formed in the second gate insulating layer 105, the first interlayer insulating layer 107, the second interlayer insulating layer 108, and the third gate insulating layer 109. A portion of the first reference gate line GRL can correspond to the third gate electrode G3. The portion of the second oxide semiconductor pattern 1520 corresponding to the first reference gate line GRL can be a channel region C3, and the two opposite sides of the channel region C3 can be conductive regions S3 and D3, which are made conductive by doping with impurities or plasma treatment. One of the conductive regions S3 and D3 can be a source region, and the other can be a drain region. The source region and drain region can correspond to the source electrode and the drain electrode. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0158] The scan line GWL can extend generally in a first direction (e.g., the x-axis direction) to traverse the first pixel circuit PC1 and the second pixel circuit PC2. The scan line GWL can traverse pixel circuits arranged in the same row as the first pixel circuit PC1 and the second pixel circuit PC2. A portion of the scan line GWL can correspond to the second gate electrode G2. The portion of the second oxide semiconductor pattern 1520 corresponding to the scan line GWL can be a channel region C2, and the two opposite sides of the channel region C2 can be conductive regions S2 and D2, which are made conductive by doping with impurities or plasma treatment. One of the conductive regions S2 and D2 can be a source region, and the other can be a drain region. The source and drain regions can correspond to the source electrode and the drain electrode. The positions of the source and drain regions can be interchanged depending on the nature of the transistor.

[0159] The second reference gate line GCL can extend substantially in a first direction (e.g., the x-axis direction) to traverse the first pixel circuit PC1 and the second pixel circuit PC2. The second reference gate line GCL can traverse pixel circuits arranged in the same row as the first pixel circuit PC1 and the second pixel circuit PC2. A portion of the second reference gate line GCL can correspond to the seventh gate electrode G7. The portion of the third oxide semiconductor pattern 1530 corresponding to the second reference gate line GCL can be a channel region C7, and the two opposite sides of the channel region C7 can be conductive regions S7 and D7, which are made conductive by doping with impurities or plasma treatment. One of the conductive regions S7 and D7 can be a source region, and the other can be a drain region. The source and drain regions can correspond to the source electrode and the drain electrode. The positions of the source and drain regions can be interchanged depending on the nature of the transistor.

[0160] The second emission control line EMBL can extend substantially in a first direction (e.g., the x-axis direction) to traverse the first pixel circuit PC1 and the second pixel circuit PC2. The second emission control line EMBL can traverse pixel circuits arranged in the same row as the first pixel circuit PC1 and the second pixel circuit PC2. The second emission control line EMBL can be connected to the fourth conductive layer 1240 via contact holes EMBLCT formed in the second gate insulating layer 105, the first interlayer insulating layer 107, the second interlayer insulating layer 108, and the third gate insulating layer 109. A portion of the second emission control line EMBL can correspond to the sixth gate electrode G6. The portion of the first oxide semiconductor pattern 1510 corresponding to the second emission control line EMBL can be a channel region C6, and the two opposite sides of the channel region C6 can be conductive regions S6 and D6, which are made conductive by doping with impurities or plasma treatment. One of the conductive regions S6 and D6 can be a source region, and the other can be a drain region. The source region and drain region can correspond to the source electrode and the drain electrode. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0161] The auxiliary power line 1640 may extend generally in a first direction (e.g., the x-axis direction) to traverse the first pixel circuit PC1 and the second pixel circuit PC2. The auxiliary power line 1640 may traverse pixel circuits arranged in the same row as the first pixel circuit PC1 and the second pixel circuit PC2. The auxiliary power line 1640 is connected to the driving voltage line PL described below, and thus, the set of auxiliary power lines 1640 and driving voltage lines PL can have a grid structure in the display area DA.

[0162] The third interlayer insulating layer 111 may cover the third gate layer 1600. The third interlayer insulating layer 111 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The third interlayer insulating layer 111 may have a single-layer structure or a multi-layer structure. As an example, the third interlayer insulating layer 111 may have a stacked structure comprising layers comprising silicon oxide and layers comprising silicon nitride. The third interlayer insulating layer 111 may be an organic insulating layer comprising an organic insulating material such as acryloyl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0163] Figure 19 The first source / drain layer 1700 shown can be disposed on the third interlayer insulating layer 111. Figure 19The diagram shows a first source / drain layer 1700 including a drive voltage line PL, a first connecting electrode 1720, a second connecting electrode 1730, a third connecting electrode 1740, a fourth connecting electrode 1750, a fifth connecting electrode 1760, a sixth connecting electrode 1772, a seventh connecting electrode 1774, an eighth connecting electrode 1776, a dummy connecting electrode 1776', and a horizontal connecting line DHL. The components in the first pixel circuit PC1 and the second pixel circuit PC2 are approximately symmetrical to each other with respect to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2.

[0164] The driving voltage line PL, the first connecting electrode 1720, the second connecting electrode 1730, the third connecting electrode 1740, the fourth connecting electrode 1750, the fifth connecting electrode 1760, the sixth connecting electrode 1772, the seventh connecting electrode 1774, the eighth connecting electrode 1776, and the horizontal connecting line DHL may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including these materials. The elements included in the first source and drain layer 1700 may be formed simultaneously using the same materials and therefore may have the same layer structure.

[0165] The driving voltage line PL can have a shape extending along the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2 in a second direction (e.g., the y-axis direction). The driving voltage line PL can be connected to the auxiliary power line 1640 below it via a contact hole PLCT1 formed in the third interlayer insulating layer 111. Through this connection structure, multiple driving voltage lines PL and multiple auxiliary power lines 1640 can form a grid structure in the display area DA, and through this structure, the voltage drop (IR drop) of the driving voltage ELVDD can be minimized. Furthermore, the driving voltage line PL can be connected to the silicon semiconductor layer 1110 via contact holes PLCT2 formed in the first gate insulating layer 103, the second gate insulating layer 105, the first interlayer insulating layer 107, the second interlayer insulating layer 108, the third gate insulating layer 109, and the third interlayer insulating layer 111. In this way, the silicon semiconductor layer 1110 can have a potential equal to or similar to the driving voltage ELVDD.

[0166] The first connection electrode 1720 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape. The first connection electrode 1720 can be electrically connected to the first semiconductor layer A1 of the first transistor T1 through contact holes 1720CT1 formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. Furthermore, the first connection electrode 1720 can be connected to the fifth semiconductor layer A5 of the fifth transistor T5 through contact holes 1720CT2 formed in the first gate insulating layer 103, the second gate insulating layer 105, the first interlayer insulating layer 107, the second interlayer insulating layer 108, the third gate insulating layer 109, and the third interlayer insulating layer 111. Therefore, the first connection electrode 1720 can electrically connect the first transistor T1 and the fifth transistor T5 to each other.

[0167] The second connection electrode 1730 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 may have an isolated shape. The second connection electrode 1730 may correspond to Figure 10 The first node N1 in the pixel circuit PC. The second connection electrode 1730 can be electrically connected to the first gate electrode 1610 of the first transistor T1 through a contact hole 1730CT3 formed in the third interlayer insulating layer 111. In addition, the second connection electrode 1730 can be electrically connected to the third semiconductor layer A3 through a contact hole 1730CT1 formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. Furthermore, the second connection electrode 1730 passes through an opening formed in the fifth conductive layer 1310 through a contact hole 1730CT2 formed in the second gate insulating layer 105, the first interlayer insulating layer 107, the second interlayer insulating layer 108, the third gate insulating layer 109, and the third interlayer insulating layer 111, and is electrically connected to the third conductive layer 1230. Therefore, the second connection electrode 1730 can electrically connect the first gate electrode G1 of the first transistor T1, the third transistor T3, and the first storage electrode CEs1 to each other.

[0168] The third connection electrode 1740 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 may have an isolated shape. The third connection electrode 1740 may correspond to Figure 10The second node N2 in the pixel circuit PC. The third connection electrode 1740 can be electrically connected to the fifth conductive layer 1310, which includes the second storage electrode CEs2 and the second holding electrode CEh2, through contact holes 1740CT1 formed in the first interlayer insulating layer 107, the second interlayer insulating layer 108, the third gate insulating layer 109 and the third interlayer insulating layer 111. In addition, the third connection electrode 1740 can be electrically connected to the first oxide semiconductor pattern 1510 through contact holes 1740CT2 formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. The connection point between the third connection electrode 1740 and the first oxide semiconductor pattern 1510 can be disposed between the region of the first oxide semiconductor pattern 1510 corresponding to the first semiconductor layer A1 and the region of the first oxide semiconductor pattern 1510 corresponding to the sixth semiconductor layer A6 (see See). Figure 17 In this way, the third connection electrode 1740 can electrically connect the second storage electrode CEs2, the second holding electrode CEh2, the first transistor T1, and the sixth transistor T6 to each other.

[0169] The fourth connection electrode 1750, disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2, has an isolated shape and can be an integral body in the first pixel circuit PC1 and the pixel circuit disposed in the (j-1)th column, and can also be an integral body in the second pixel circuit PC2 and the pixel circuit disposed in the (j+2)th column. The fourth connection electrode 1750 can be electrically connected to the third semiconductor layer A3 through contact holes 1750CT1 formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. Furthermore, the fourth connection electrode 1750 can be electrically connected to the seventh semiconductor layer A7 through contact holes 1750CT2 formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. The fourth connection electrode 1750 can be electrically connected to the reference voltage line VRL described below (see...). Figure 20 ), and can transmit the reference voltage VREF to the third transistor T3 and the seventh transistor T7.

[0170] The fifth connection electrode 1760 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 can have an isolated shape. Furthermore, the fifth connection electrode 1760 can be electrically connected to the second conductive layer 1220, which serves as the first holding electrode CEh1 and acts as the holding capacitor Chd, via contact holes 1760CT1 formed in the second gate insulating layer 105, the first interlayer insulating layer 107, the second interlayer insulating layer 108, the third gate insulating layer 109, and the third interlayer insulating layer 111. Additionally, the fifth connection electrode 1760 can be electrically connected to the seventh semiconductor layer A7 via contact holes 1760CT2 formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. In this way, the fifth connection electrode 1760 can electrically connect the first holding electrode CEh1 and the seventh transistor T7 to each other.

[0171] The sixth connection electrode 1772, disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2, may have an isolated shape. The sixth connection electrode 1772 can be electrically connected to the second semiconductor layer A2 through contact holes 1772CT formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. The sixth connection electrode 1772 can be electrically connected to the data line DL (see...). Figure 20 ), to transmit the data signal DATA to the second transistor T2.

[0172] The seventh connection electrode 1774 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 may have an isolated shape. The seventh connection electrode 1774 may be electrically connected to the fourth semiconductor layer A4 of the fourth transistor T4 through contact holes 1774CT formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. The seventh connection electrode 1774 may be electrically connected to the pixel electrode 210 of the light-emitting diode (LED) as described below.

[0173] The eighth connection electrode 1776 disposed in the second pixel circuit PC2 can have an isolated shape. In the second pixel circuit PC2, the eighth connection electrode 1776 can be electrically connected to the fourth semiconductor layer A4 of the fourth transistor T4 through contact holes 1776CT formed in the third gate insulating layer 109 and the third interlayer insulating layer 111. As described below, the eighth connection electrode 1776 can be electrically connected to the initialization voltage line VL traversing the second pixel circuit PC2 (see...). Figure 20 This is to transfer the initialization voltage VINT to the fourth transistor T4. For example, as... Figure 17As shown, the fourth transistor T4 disposed in the first pixel circuit PC1 located in the j-th column is electrically connected to the fourth transistor disposed in the pixel circuit (adjacent in the -x direction) in the (j-1)-th column. Therefore, the fourth transistor T4 disposed in the first pixel circuit PC1 can be electrically connected to the initialization voltage line traversing the pixel circuit (adjacent in the -x direction) in the (j-1)-th column, instead of the initialization voltage line VL traversing the first pixel circuit PC1 (see [reference]). Figure 20 ).

[0174] The dummy connection electrode 1776' disposed in the first pixel circuit PC1 can have an isolated shape. The dummy connection electrode 1776' can be electrically connected to the fourth oxide semiconductor pattern 1540, which is also a dummy pattern, through the contact hole 1776CT'. For example, the dummy connection electrode 1776' and the eighth connection electrode 1776 can be symmetrical to each other with respect to the dashed line IML.

[0175] A horizontal connecting line DHL, which generally extends in a first direction (e.g., the x-axis direction) but is disconnected by the driving voltage line PL, can be electrically connected to the eighth conductive layer 1630 through a contact hole DHLCT formed in the third interlayer insulating layer 111. Therefore, the combination of the eighth conductive layer 1630 and the horizontal connecting line DHL described below can correspond to the reference... Figure 8 or Figure 9 This describes a portion of the data transfer line DTL, such as one of the first horizontal connector DHL1, the second horizontal connector DHL2, and the third horizontal connector DHL3. The horizontal connector DHL needs to be electrically connected to the vertical connector DVL described below (see [link to documentation]). Figure 20 In the case of a horizontal connector DHL, the horizontal connector DHL can be electrically connected to the vertical connector DVL at the part where the contact hole DHLCT is set.

[0176] The fourth interlayer insulation layer 113 can be set in the reference. Figure 19 The first source / drain layer 1700 is described. The fourth interlayer insulating layer 113 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon nitride. The fourth interlayer insulating layer 113 may have a single-layer structure or a multilayer structure. As an example, the fourth interlayer insulating layer 113 may have a stacked structure comprising layers comprising silicon oxide and layers comprising silicon nitride. The fourth interlayer insulating layer 113 may be an organic insulating layer comprising an organic insulating material such as acryloyl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0177] Figure 20 The second source / drain layer 1800 shown can be disposed on the fourth interlayer insulating layer 113. For example... Figure 20As shown, the second source / drain layer 1800 includes a data line DL, a vertical connection line DVL, an initialization voltage line VL, a reference voltage line VRL, and a ninth connection electrode 1810. The components in the first pixel circuit PC1 and the second pixel circuit PC2 are approximately symmetrical to each other with respect to the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2.

[0178] Each of the data line DL, vertical connection line DVL, initialization voltage line VL, and reference voltage line VRL can extend in a second direction (e.g., the y-axis direction). The data line DL, vertical connection line DVL, initialization voltage line VL, and reference voltage line VRL traversing the first pixel circuit PC1 and the data line DL, vertical connection line DVL, initialization voltage line VL, and reference voltage line VRL traversing the second pixel circuit PC2 can be substantially symmetrical to each other with respect to the dashed line IML.

[0179] The data line DL traversing each of the first pixel circuit PC1 and the second pixel circuit PC2 can be electrically connected to the reference via the contact hole DLCT formed in the fourth interlayer insulating layer 113. Figure 19 The sixth connection electrode 1772 is described to provide a data signal to the second transistor T2.

[0180] The vertical connecting line DVL traversing each of the first pixel circuit PC1 and the second pixel circuit PC2 can correspond to a reference. Figure 8 or Figure 9 A portion of the described data transmission line DTL, for example, one of the first vertical connecting line DVL1, the second vertical connecting line DVL2, the third vertical connecting line DVL3, the first additional vertical connecting line DVL1', the second additional vertical connecting line DVL2', and the third additional vertical connecting line DVL3'. Because the vertical connecting line DVL includes a portion protruding in a first direction (e.g., the x-axis direction), in cases where the vertical connecting line DVL needs to be electrically connected to the horizontal connecting line DHL disposed below it, the vertical connecting line DVL can be electrically connected to the horizontal connecting line DHL in the protruding portion through a contact hole formed in the fourth interlayer insulation layer 113.

[0181] The initialization voltage line VL traversing the second pixel circuit PC2 can be electrically connected to the eighth connection electrode 1776 below it through the contact hole VLCT formed in the fourth interlayer insulating layer 113, and the eighth connection electrode 1776 can be electrically connected to the first oxide semiconductor pattern 1510 below it through the contact hole 1776CT to deliver the initialization voltage to the fourth transistor T4 of the second pixel circuit PC2.

[0182] The initialization voltage line VL traversing the first pixel circuit PC1 can be electrically connected to the dummy connection electrode 1776' through the contact hole VLCT formed in the fourth interlayer insulating layer 113. (See above reference.) Figure 19 As described, such as Figure 17 As shown, the fourth transistor T4 disposed in the first pixel circuit PC1 disposed in the j-th column is electrically connected to the fourth transistor disposed in the pixel circuit (adjacent in the -x direction) in the (j-1)-th column. Therefore, the fourth transistor T4 disposed in the first pixel circuit PC1 can be electrically connected to the initialization voltage line that crosses the pixel circuit (adjacent in the -x direction) in the (j-1)-th column, instead of the first initialization voltage line VL that crosses the first pixel circuit PC1.

[0183] The semiconductor layer 1500 can be symmetrical with respect to the dashed line IML in the first pixel circuit PC1 and the second pixel circuit PC2, and therefore, the fourth oxide semiconductor pattern 1540 of the first pixel circuit PC1 can be an integral part of the first oxide semiconductor pattern 1510. In this case, the initialization voltage line VL traversing the first pixel circuit PC1 can be electrically connected to the fourth transistor T4 of the first pixel circuit PC1.

[0184] The reference voltage line VRL traversing each of the first pixel circuit PC1 and the second pixel circuit PC2 can be electrically connected to the reference through the contact hole VRLCT formed in the fourth interlayer insulating layer 113. Figure 19 The fourth connection electrode 1750 is described. As described above, the fourth connection electrode 1750 can be electrically connected to the second oxide semiconductor pattern 1520 and the third oxide semiconductor pattern 1530 to provide a reference voltage to the third transistor T3 and the seventh transistor T7.

[0185] For example, the first pixel circuit PC1 located in the j-th column can share the reference voltage line VRL with the pixel circuit located in the (j-1)-th column adjacent in the -x direction, and the second pixel circuit PC2 located in the j+1-th column can share the reference voltage line VRL with the pixel circuit located in the j+2-th column adjacent in the +x direction.

[0186] Each ninth connection electrode 1810 may have an isolated shape. The ninth connection electrode 1810 disposed in each of the first pixel circuit PC1 and the second pixel circuit PC2 can be electrically connected to a reference via a contact hole 1810CT formed in the fourth interlayer insulating layer 113. Figure 19The seventh connection electrode 1774 is described. The ninth connection electrode 1810 can also be electrically connected to the pixel electrode 210 in the upper portion through the contact hole 210CT in the upper portion. As described above, the seventh connection electrode 1774 can be electrically connected to the fourth transistor T4 and the sixth transistor T6. Therefore, the seventh connection electrode 1774 and the ninth connection electrode 1810 can electrically connect the pixel electrode of the light-emitting diode (LED) to the fourth transistor T4 and the sixth transistor T6.

[0187] The planarization layer 115 may cover the second source / drain layer 1800. The planarization layer 115 may be an organic insulating layer comprising an organic insulating material such as acryloyl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0188] A light-emitting diode (LED) can be disposed on the planarization layer 115. The LED may include a pixel electrode 210, an intermediate layer 220, and a common electrode 230 disposed on the planarization layer 115. Figure 21 The use of pixel electrode 210 is shown. For example, since a light-emitting diode (LED) includes pixel electrode 210, the location of pixel electrode 210 can be referred to as the location of the light-emitting diode (LED). For convenience, Figure 21 The pixel electrode 210 and the second source / drain layer 1800 below it are shown in an overlapping manner.

[0189] like Figure 21 As shown, light-emitting diodes (LEDs) can be spaced apart from each other. Figure 21 The diagram shows a second light-emitting diode (LED2) overlapping with the first pixel circuit PC1 and the second pixel circuit PC2, electrically connected to the first pixel circuit PC1 located in the i-th row and j-th column. For example, although the second LED2 could be positioned on the dashed line IML between the first pixel circuit PC1 and the second pixel circuit PC2, as shown... Figure 21 As shown, however, the pixel electrode 210 of the second light-emitting diode LED2 may have a protrusion protruding in the -x direction and be electrically connected to the first pixel circuit PC1 through a contact hole 210CT formed in the planarization layer 115. Furthermore, in other light-emitting diodes, the pixel electrode 210 may have a protrusion, and within the protrusion, it may be electrically connected to the corresponding pixel circuit through a contact hole 210CT below it.

[0190] Four third light-emitting diodes (LED3) can be arranged around the second light-emitting diodes (LED2). Figure 21 The diagram shows a third light-emitting diode (LED3) positioned at the four vertices of a quadrilateral within the dashed lines representing the boundary of the set of first pixel circuits PC1 and second pixel circuits PC2. For example, in... Figure 21The diagram shows a third light-emitting diode (LED3) located at the lower right end, electrically connected to a second pixel circuit PC2 located in the i-th row and j+1-th column; a third light-emitting diode (LED3) located at the upper right end, electrically connected to a pixel circuit located in the i-1-th row and j+1-th column and adjacent to the second pixel circuit PC2 in the +y direction; a third light-emitting diode (LED3) located at the lower left end, electrically connected to a pixel circuit located in the i-th row and j-1-th column and adjacent to the first pixel circuit PC1 in the -x direction; and a third light-emitting diode (LED3) located at the upper left end, electrically connected to a pixel circuit located in the i-1-th row and j-1-th column.

[0191] For example, the first light-emitting diode (LED) can be electrically connected to a pixel circuit adjacent to the first pixel circuit PC1 in the +y direction and located in the (i-1)th row and jth column. Furthermore, the first LED can be electrically connected to a pixel circuit adjacent to the second pixel circuit PC2 in the +x direction and located in the i-th row and j+2th column, a pixel circuit located in the i-th row and j-2th column, and a pixel circuit adjacent to the first pixel circuit PC1 in the -y direction and located in the i+1th row and jth column. Similar to the second LED2, even in the case of the first LED, four third LEDs LED3 can be arranged around the first LED.

[0192] For example, the pixel circuits arranged in the +x direction in the i-th row can be a repeat of the set of pixel circuits for the first light-emitting diode, the third light-emitting diode LED3, the second light-emitting diode LED2, and the third light-emitting diode LED3. Furthermore, the pixel circuits arranged in the y-axis direction in the j-th column can be a repeat of the set of pixel circuits for the first light-emitting diode and the second light-emitting diode LED2, and the pixel circuits arranged in the second direction (e.g., the y-axis direction) in each of the (j-1)-th and (j+1)-th columns can be pixel circuits for the third light-emitting diode LED3.

[0193] As an example, the first light-emitting diode can be a diode that emits red light, the second light-emitting diode LED2 can be a diode that emits blue light, and the third light-emitting diode LED3 can be a diode that emits green light.

[0194] However, the arrangement of light-emitting diodes is not limited to the above arrangement and can be modified in various ways.

[0195] Pixel electrode 210 can be a transparent or semi-transparent electrode or a reflective electrode. As an example, pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer, wherein the reflective layer includes Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). X The pixel electrode 210 may contain at least one of the following: ZnO or ZnO2, indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). As an example, the pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0196] A pixel defining layer 119 can be disposed on the planarization layer 115. By covering the edge of the pixel electrode 210 and increasing the distance between the pixel electrode 210 and the common electrode 230 above the pixel electrode 210, the pixel defining layer 119 can prevent arcing or the like at the edge of the pixel electrode 210. For example, as... Figure 21 and Figure 22 As shown, the pixel defining layer 119 has an opening 119OP to expose the central portion of the pixel electrode 210. The exposed portion of the pixel electrode 210 can be defined as the emission region EA. The pixel defining layer 119 may include an organic insulating material such as polyimide, acrylic resin, benzocyclobutene, phenolic resin, etc., and is formed by spin coating or the like.

[0197] At least a portion of the intermediate layer 220, including the emitting layer of a light-emitting diode (LED), may be disposed in an opening formed in the pixel defining layer 119. The emitting region of the LED may be defined by the opening. The intermediate layer 220 may include the emitting layer. The emitting layer may include an organic material, including a fluorescent or phosphorus material that emits red, green, blue, or white light. The emitting layer may include a polymeric organic material or a low molecular weight organic material. Functional layers may optionally be further disposed below and above the emitting layer, and the functional layers may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0198] Optionally, the intermediate layer 220 may include a first stack comprising an emission layer and a functional layer, a second stack comprising an emission layer and a functional layer, and a charge generation layer between the first and second stacks. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The light emission efficiency of a series-connected light-emitting diode (LED) comprising multiple emission layers can be enhanced, or even further, through the negative and positive charge generation layers.

[0199] The negative charge generation layer can be an n-type charge generation layer. The negative charge generation layer can provide electrons. The negative charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material. The positive charge generation layer can be a p-type charge generation layer. The positive charge generation layer can provide holes. The positive charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material.

[0200] The emission layer can have a patterned shape corresponding to the pixel electrode 210. The intermediate layer 220, excluding the emission layer, can be a single, integral body above the multiple pixel electrodes 210. However, various modifications are possible.

[0201] The common electrode 230 can be a transparent electrode or a reflective electrode. As an example, the common electrode 230 can be a transparent or semi-transparent electrode and can include a thin metal film containing Li, Ca, Al, Ag, Mg, or compounds thereof (e.g., LiF) and have a small work function. Furthermore, the common electrode 230 can also include a transparent conductive oxide (TCO) layer disposed on the metal film, such as ITO, indium zinc oxide (IZO), ZnO, ZnO2, or In2O3.

[0202] The common electrode 230 can be integrally formed over the entire surface of the display area DA to cover the display area DA, and is disposed on the intermediate layer 220 and the pixel defining layer 119. For example, each of the pixel electrodes 210 can be arranged to correspond to each light-emitting diode (LED), and the common electrode 230 can be an integral body corresponding to multiple LEDs. Multiple LEDs can share the common electrode 230. The stacked structure of the pixel electrode 210, the intermediate layer 220, and the common electrode 230 can correspond to the LEDs.

[0203] When needed, an encapsulation layer can be provided on the light-emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer interposed therebetween.

[0204] As described above, the fifth conductive layer 1310 can be the second storage electrode CEs2 of the storage capacitor Cst, and simultaneously, it can also be the first holding electrode CEh1 of the holding capacitor Chd. When the potential of the second storage electrode CEs2 of the storage capacitor Cst becomes unstable in each pixel circuit, the first transistor T1, acting as the driving transistor, may not be able to accurately control the amount of current corresponding to the data signal DATA. This may cause the display device to fail to display a high-quality image.

[0205] Conversely, in the display panel 10 and the electronic device 1 including the display panel 10, according to an embodiment, the silicon semiconductor layer 1110 is electrically connected to the driving voltage line PL as described above. Furthermore, in a plan view, an extension portion ETP of the silicon semiconductor layer 1110 is disposed between the first transistor T1 of the first pixel circuit PC1 and the first transistor T1 of the second pixel circuit PC2. For example, in a plan view, the extension portion ETP of the silicon semiconductor layer 1110 is disposed between the fifth conductive layer 1310 corresponding to the second node N2 of the first transistor T1 of the first pixel circuit PC1 and the fifth conductive layer 1310 corresponding to the second node N2 of the first transistor T1 of the second pixel circuit PC2. Therefore, the extension portion ETP of the silicon semiconductor layer 1110, having a potential of a driving voltage ELVDD as a constant voltage or similar voltage, can effectively prevent or minimize the electrical influence between the second node N2 of the first pixel circuit PC1 and the second node N2 of the second pixel circuit PC2. In this way, a display panel 10 displaying high-quality images and an electronic device 1 including the display panel 10 can be realized.

[0206] In order to effectively prevent the second node N2 of the first pixel circuit PC1 and the second node N2 of the second pixel circuit PC2 from electrically influencing each other, one end of the extension portion ETP of the silicon semiconductor layer 1110 in the second direction (e.g., the y-axis direction) coincides with one end of the portion of the fifth conductive layer 1310 in the first pixel circuit PC1 adjacent to the extension portion ETP in the second direction (e.g., the y-axis direction) and one end of the portion of the fifth conductive layer 1310 in the second pixel circuit PC2 adjacent to the extension portion ETP in the second direction (e.g., the y-axis direction).

[0207] For example, as described above, the fifth transistor T5 in the first pixel circuit PC1 and the second pixel circuit PC2 includes the main portion MP of the silicon semiconductor layer 1110 as a component. Therefore, the fifth transistor T5 of the first pixel circuit PC1 may include a portion of the main portion MP disposed on one side of the extension portion ETP, for example, a portion of the main portion MP disposed in the -x direction relative to the extension portion ETP. Similarly, the fifth transistor T5 of the second pixel circuit PC2 may include a portion of the main portion MP disposed on the other side of the extension portion ETP, for example, a portion of the main portion MP disposed in the +x direction relative to the extension portion ETP. Furthermore, as described above, each of the two opposite ends of the main portion MP can be electrically connected to the corresponding first transistor T1 via the first connection electrode 1720.

[0208] Thus far, various electronic devices 1, display panels 10 and / or display modules 11 have been described, and each of the electronic devices 1, display panels 10 and / or display modules 11 falls within the scope of this disclosure.

[0209] Although the invention has been described with reference to various embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that these are examples and various changes and equivalent other embodiments may be made therefrom.

Claims

1. A display panel, comprising: The first transistors are arranged adjacent to each other in a first direction; as well as A silicon semiconductor layer includes a main portion extending in the first direction and an extension portion extending in a second direction intersecting the first direction. In the plan view, the extension portion is disposed between the first transistors.

2. The display panel according to claim 1, wherein, Each of the first transistors includes a first semiconductor layer and a first gate electrode, the first gate electrode being disposed on and overlapping the first semiconductor layer.

3. The display panel according to claim 2, wherein, The first semiconductor layer includes an oxide semiconductor.

4. The display panel according to claim 2, further comprising a gate insulating layer, the gate insulating layer covering the silicon semiconductor layer, wherein, The first semiconductor layer is disposed on the gate insulating layer.

5. The display panel according to claim 4, further comprising a capacitor electrode disposed between the gate insulating layer and the first semiconductor layer, wherein, The capacitor electrodes are spaced apart from each other and correspond to the first transistor.

6. The display panel according to claim 5, wherein, In the plan view, the extension portion is disposed between the capacitor electrodes.

7. The display panel according to claim 5, wherein, One end of the extension in the second direction coincides with one end of the portion of each of the capacitor electrodes adjacent to the extension in the second direction.

8. The display panel according to claim 5, further comprising a shielding layer disposed between the capacitor electrode and the first transistor.

9. The display panel according to claim 8, wherein, Each of the shielding layers is electrically connected to a corresponding capacitor electrode among the capacitor electrodes.

10. The display panel according to claim 1, further comprising: The second transistor corresponds to the first transistor; as well as The data line corresponds to the second transistor. Each of the second transistors has a first end electrically connected to a corresponding data line in the data line and a second end electrically connected to a first gate electrode of a corresponding first transistor in the first transistor, and In this embodiment, the second semiconductor layer of each of the second transistors is disposed on the same layer as the first semiconductor layer of each of the first transistors.

11. The display panel according to claim 1, further comprising a driving voltage line electrically connected to the silicon semiconductor layer.

12. The display panel according to claim 11, wherein, The driving voltage line is disposed on the silicon semiconductor layer.

13. The display panel of claim 1, further comprising an emission control transistor, the emission control transistor comprising a first portion of the main portion disposed on a first side of the extension portion and a second portion of the main portion disposed on a second side of the extension portion. in, Each of the emitter control transistors is electrically connected to a corresponding first transistor within the first transistor.

14. The display panel of claim 13, further comprising a connection electrode that electrically connects each of the first portion and the second portion of the main portion to a corresponding first transistor in the first transistor.

15. An electronic device comprising: Display panel; as well as A lower cover, forming the exterior of the electronic device, the lower cover including an opening that exposes a portion of the display panel. The display panel includes: The first transistors are arranged adjacent to each other in a first direction; and A silicon semiconductor layer includes a main portion extending in the first direction and an extension portion extending in a second direction intersecting the first direction. In the plan view, the extension portion is disposed between the first transistors.

16. The electronic device according to claim 15, wherein, Each of the first transistors includes a first semiconductor layer and a first gate electrode, the first gate electrode being disposed on and overlapping the first semiconductor layer.

17. The electronic device according to claim 16, wherein, The first semiconductor layer includes an oxide semiconductor.

18. The electronic device according to claim 16, wherein the display panel further comprises: A gate insulating layer covering the silicon semiconductor layer, wherein the first semiconductor layer is disposed on the gate insulating layer; and The capacitor electrode is disposed between the gate insulating layer and the first semiconductor layer, spaced apart from each other, and corresponds to the first transistor.

19. The electronic device according to claim 18, wherein, In the plan view, the extension portion is disposed between the capacitor electrodes.

20. The electronic device of claim 15, wherein the display panel further comprises a driving voltage line electrically connected to the silicon semiconductor layer.

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