Software and hardware collaborative optimization method and system of BMC chip based on RISC-V architecture

Abstract

The invention relates to a software and hardware collaborative optimization method and system of a BMC chip based on an RISC-V architecture, belongs to the technical field of chip design, designs a core processing unit of the BMC chip by utilizing an RISC-V instruction set architecture, and meets the performance and power consumption requirements of the BMC through a modularized and extensible instruction set. Hardware acceleration is provided for specific functions (such as secure startup and encryption) of the BMC through custom instruction extension, and performance, power consumption and reliability indexes of a BMC chip are improved by coordinating and optimizing an RISC-V processor core, a peripheral interface and a software system, so that management and monitoring requirements of a server system are met. The technology has a wide application prospect in the field of server system management.

Description

Technical Field

[0001] This invention relates to a hardware and software co-optimization method and system for a BMC chip based on the RISC-V architecture, belonging to the field of chip design technology. Background Technology

[0002] The Baseboard Management Controller (BMC) is a dedicated microcontroller integrated into server, storage, and network systems to provide out-of-band management and monitoring capabilities. The main functions of the BMC include: 1. Power Management: Controlling the power-on / off sequence of the system, monitoring power consumption, and managing the power status of the system.

[0003] 2. Temperature monitoring: Tracks temperature sensor data at various points within the system and triggers cooling measures when thresholds are exceeded.

[0004] 3. Remote access: Enables remote administrators to diagnose, configure, and restore the system in the event of a failure of the main operating system.

[0005] 4. Log recording and alarms: Collect hardware event logs and generate alarms for critical events such as fan failure and abnormal voltage.

[0006] The BMC chip is a critical component in server systems, responsible for monitoring and managing server hardware. With the rapid development of cloud computing and big data technologies, the demands for server system management and maintenance are increasing. Traditional BMC chips based on proprietary instruction set architectures have limitations in terms of flexibility, scalability, and cost-effectiveness. Traditionally, BMCs are designed based on proprietary microcontroller architectures and real-time operating systems, but this approach has several limitations: 1. Poor flexibility: Proprietary BMC designs are usually tied to specific hardware platforms and cannot be easily customized or have their functions expanded.

[0007] 2. High cost: The development and maintenance costs of customized BMC solutions are high, especially for small and medium-sized system vendors.

[0008] 3. Supplier lock-in: Proprietary BMC designs require tight integration with system vendors, making it difficult to adopt alternative solutions. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention proposes a hardware-software co-optimization method for BMC chips based on the RISC-V architecture, aiming to design more efficient, flexible, and economical BMC solutions for server, storage, and network systems. This method improves the performance, power consumption, and reliability of the BMC chip by coordinating and optimizing the RISC-V processor core, peripheral interfaces, and software system, thereby meeting the management and monitoring requirements of server systems. This technology has broad application prospects in the field of server system management.

[0010] The technical solution of the present invention is as follows: A hardware-software co-optimization method for BMC chips based on the RISC-V architecture is proposed. This method utilizes the RISC-V instruction set architecture to design the core processing unit of the BMC chip, meeting the performance and power consumption requirements of the BMC through a modular and scalable instruction set. Hardware acceleration is provided for specific BMC functions (such as secure boot and encryption) through custom instruction extensions.

[0011] The design includes the following: (1) Hardware design The RV32E or RV64I core is selected as the core processing unit of the BMC. A dedicated bus interface is designed between the processor core and peripheral circuits to achieve precise mapping and scheduling of processor resources, optimizing area and power consumption, suitable for the low-power requirements of the BMC. A memory subsystem is designed, specifically by directly deploying a low-power SRAM controller and a DDR memory controller on the processor bus, and configuring a dedicated memory management unit (MMU) to improve memory access efficiency. SPI Flash is used for firmware storage, supporting remote firmware updates; at least one peripheral interface is supported to ensure broad compatibility with system components.

[0012] Preferably, in step (1), the peripheral interface includes, but is not limited to, I2C / SMBus, UART, GPIO, PCIe, and Ethernet interface.

[0013] Preferably, in step (1), the firmware update of the firmware storage includes the following steps: implementing a firmware update mechanism, designing a firmware update mechanism that supports remote updates via network or other interfaces; the specific process includes downloading, verifying, storing, and applying the update, while providing a rollback mechanism to deal with update failures. The rollback mechanism includes: designing a dual-partition storage strategy, which can quickly switch to the backup partition and restore to the previous stable state when the firmware update fails, ensuring the continuous operation of the system. Specifically, the implementation can be to use a network interface to transmit encrypted firmware to Flash, use Flash to complete firmware storage, use the BMC operating system to identify the firmware name, and analyze whether it is BMC firmware or Host firmware; use a decryption module to accelerate decryption and verification, and finally complete the update of the corresponding firmware.

[0014] (2) Software optimization Based on the RISC-V architecture, a lightweight real-time operating system for BMC is built by customizing the kernel, customizing the scheduler, and configuring security isolation mechanisms, supporting real-time task scheduling and security.

[0015] Preferably, in step (2), the specific construction steps include: Step S1: Kernel trimming; Select an open-source real-time operating system that supports the RISC-V architecture as the base, and trim its kernel according to the functional requirements of the BMC chip, removing unnecessary components to reduce system size and memory usage; Specifically, trim the file system, graphical interface library, and unnecessary network protocol stacks (such as FTP, Telnet), retaining only core functions such as task scheduling, memory management, interrupt handling, and IPC (inter-process communication); Step S2: Scheduler customization; To meet the real-time requirements of BMC tasks, customize the operating system's task scheduler; Adopt a priority-based preemptive scheduling strategy to allocate the highest preemptive priority to high-priority critical tasks (such as temperature monitoring and power failure alarms) to ensure their response time is in the millisecond range; Assign lower priority to low-priority tasks (such as log recording and web interface data updates) to execute them when the system is idle; Step S3: Configure security isolation mechanism; Utilize the Physical Memory Protection (PMP) function of the RISC-V architecture to configure independent memory protection areas for critical tasks (including secure boot and firmware updates) and general management tasks; By configuring PMP registers, restrict different tasks to access only their authorized memory address space and peripherals, preventing the crash or attack of a single task from affecting the stability and security of the entire system.

[0016] Based on the RISC-V security extension instruction set, a multi-stage boot firmware bootloader is constructed, integrating a hardware encryption engine, an image signature verification module, and a trusted boot verification process to ensure the integrity and security of the firmware. The RISC-V security extension instruction set is a standardized instruction set defined by RISC-V for accelerating symmetric encryption, hash algorithms, and public-key cryptography.

[0017] Preferably, in step (2), the multi-stage boot firmware bootloader includes the following steps: Bootloader & Firmware: Optimized for booting and booting RISC-V architecture BMC chips. Initialization for RISC-V chips uses a step-by-step boot process, specifically including the following stages: ZSBL, SBI, U-Boot, and Linux. The specific implementation is not limited to these methods; it can be ZSBL + openSBI + U-Boot + OpenBMC (Linux). The specific process is as follows... Figure 3 As shown.

[0018] Hardware Abstraction Layer (HAL): Located between the operating system and the physical hardware, it shields the implementation differences of the underlying hardware. In a RISC-V environment, openSBI is preferred as the implementation of HAL. It encapsulates the core hardware operation details of the underlying CPU, such as privilege mode switching, interrupt management, and timer access, thereby providing a standardized hardware access interface for the upper-layer operating system. This allows different operating systems (such as Linux or RTOS) to run without modification for specific hardware. HAL is the key technology layer for decoupling all upper-layer software functions from the underlying hardware in this invention.

[0019] Operating System: Selected and optimized based on the specific architecture and application scenario of the BMC chip; 1. When the BMC chip adopts the resource-constrained RV32 architecture, or when there are strict real-time requirements for tasks such as precise fan speed control and emergency power failure handling (e.g., response time must be in the microsecond or millisecond range), a lightweight real-time operating system (RTOS) can be built using the method described above. 2. When the BMC chip adopts the relatively resource-rich RV64 architecture and needs to support complex management functions such as a complete network protocol stack and web server, the full-featured Linux operating system should be selected, and customized development can be carried out based on the open-source OpenBMC project.

[0020] Firmware and drivers are software modules written or ported based on each peripheral interface (such as I2C / SMBus, UART, GPIO, PCIe, etc.) integrated into the BMC chip by HAL. According to the hardware specifications of each interface, drivers are designed and implemented, including functions such as device initialization, data transmission, interrupt handling, and error handling. For example, for the I2C interface, the Linux kernel's I2C framework is used to implement read and write functions for the slave device; for the UART interface, its baud rate configuration and data transmission / reception functions are implemented. These drivers interact with the hardware through HAL to ensure its ability to work with the operating system and to optimize performance and power consumption.

[0021] Application Layer and BMC Management Software: This layer primarily develops or ports BMC-specific application software, specifically independent application modules for power management, temperature monitoring, and fan control. These modules ensure flexible configuration and invocation, exchange data with the hardware layer using standard APIs, handle system management tasks, and perform power management, temperature control, and fan control. The layer also ensures these software programs can interact with the underlying hardware through the operating system's APIs. A user-friendly interface, including a web interface or command-line interface (CLI), is provided, supporting configuration, monitoring, and log viewing functions. The web interface is provided via an HTTP / HTTPS server, while the CLI is implemented through specific command-line tools.

[0022] For the BMC management interface, the IPMI and Redfish protocol stack implementations were refactored to enable it to perform protocol communication functions on an operating system under the RISC-V architecture.

[0023] Preferably, in step (2), the reconstruction of the IPMI and Redfish protocol stack implementation specifically includes: completing the configuration of the BMC management software, specifically implementing a centralized management configuration tool that allows users to set various management parameters, such as device address, communication rate and monitoring threshold, through a graphical interface or CLI, so as to adjust the system's operating status in real time; implementing the IPMI and Redfish interface, specifically based on RISC-V security extension, reconstructing the IPMI and Redfish protocol stack, implementing an end-to-end encrypted communication channel, supporting multi-factor authentication and fine-grained access control policies, providing remote monitoring and management functions, and ensuring good integration with the operating system and hardware. This system enables status acquisition and analysis, recording system events, errors, alarms, and other information, providing real-time monitoring and logging. It supports KVM over LAN functionality, allowing remote management and control of the system, and provides a remote access interface supporting operations such as power on / off, restart, and configuration. It implements multiple authentication and authorization mechanisms, specifically: Role-Based Access Control (RBAC): defining different roles such as administrators, operators, and regular users, and precisely assigning different operation permissions (such as configuration modification, firmware updates, log viewing, etc.) to each role, thereby achieving minimal and fine-grained permission management; and Multi-Factor Authentication (MFA): adding a second authentication factor to traditional username and password authentication, such as requiring users to provide a one-time password (OTP) generated through an out-of-band channel (such as a mobile application), significantly enhancing login security. Mandatory Access Control (MAC): Utilizing operating system kernel-level security policies (such as SELinux), MAC sets fixed security labels and access rules for processes and files, forcibly restricting the permission scope of critical processes (such as the IPMI service process). Even if compromised, these processes cannot access other system resources without authorization, thus providing a deeper level of protection. It ensures that only authorized users can access the BMC, while also providing data encryption, secure transmission, and other functions to protect system and data security.

[0024] (3) Security function optimization An integrated hardware-accelerated encryption engine enhances the security of data transmission and storage.

[0025] Implement a secure boot mechanism to ensure the integrity and security of the firmware during the BMC boot process.

[0026] By leveraging the rich extension instructions of the RISC-V architecture, a secure boot process for the BMC chip is provided. Specifically, a dedicated secure boot hardware module is used, employing RISC-V Z extension instructions, which provide hardware cryptographic primitives, secure hash calculations, and signature verification functions.

[0027] Preferred options include: Design a RISC-V-based secure bootloader (such as the existing ZSBL program) that can directly interact with the hardware acceleration module. Within the bootloader, a hardware accelerator is used to perform integrity verification and authentication of the boot code, ensuring that only authenticated firmware can boot. The hardware accelerator is also used to accelerate encryption algorithms (such as RSA and SHA) to improve boot speed. The integrity and speed of the secure boot process are tested and verified to ensure both security and efficiency.

[0028] Encryption and decryption hardware acceleration: Hardware Accelerator Design: Design or integrate a hardware accelerator that supports common encryption algorithms (such as existing AES, RSA, SHA, etc.), ensuring its compatibility with the RISC-V core; integrate the hardware accelerator into the RISC-V BMC chip, ensuring it can be directly called by the operating system and application layer; develop drivers that allow the openBMC operating system to recognize and use this hardware accelerator for encryption and decryption operations; link the openBMC encryption library, prioritizing the use of the hardware accelerator for encryption and decryption operations to reduce CPU load; conduct performance testing, comparing the efficiency of hardware acceleration and software encryption to ensure the acceleration effect of the encryption process. Ensure the security of the hardware accelerator to prevent unauthorized access and use.

[0029] (4) Optimization of power management unit Design a dedicated power management unit (PMU) that supports multiple power states and enables low-power modes.

[0030] Leveraging the programmability of RISC-V, power management strategies can be dynamically adjusted to adapt to different workloads.

[0031] Preferably, multiple power state support is provided: A power management unit (PMU) supporting multiple power states is designed, based on existing IPMI power management specifications and the OpenPOWER standard, combined with a RISC-V architecture power management unit, to implement modes including active, sleep, and standby. Control of the PMU is implemented in openBMC, a DBus-based powered daemon is developed, a state transition event listening mechanism is constructed, and RESTful APIs and systemd service interfaces are provided to achieve fine-grained management and rapid switching of power states, supporting the switching of multiple power states. Specifically, a multi-dimensional intelligent automatic power state switching mechanism is constructed: It enters shallow sleep when CPU utilization is 0-30%, remains active at 30-60%, and maintains high-performance mode above 60%; combined with temperature management, it automatically reduces the power state when the chip temperature exceeds 75°C; it intelligently adjusts the depth of energy-saving mode based on system idle time; it performs dynamic energy consumption optimization while ensuring the real-time performance of critical services, automatically switching to the optimal power state based on the current system state (such as load and temperature); and it ensures the stability and security of the power state switching process, avoiding system crashes or data loss.

[0032] Preferably, the power management unit optimization also includes thermal management: monitoring the temperature of the BMC chip and adjusting the power state according to the temperature to prevent overheating. Integrating temperature monitoring functionality into openBMC involves integrating multiple temperature sensors (such as LM75 and DS18B20) via the I2C bus, configuring a temperature acquisition cycle of 1-2 seconds, developing a DBus-based temperature data communication daemon process called thermal-monitor, and building a monitoring system that includes temperature threshold configuration, real-time monitoring, and alarm notifications. A RESTful API interface is provided to enable remote querying of temperature data, ensuring the system can acquire temperature data in real time. A thermal management strategy is designed, specifically a four-level temperature response mechanism: full performance operation from 0-60°C, CPU frequency reduction of 15-25% from 60-75°C, active frequency reduction and shutdown of non-critical modules from 75-85°C, and emergency power-down protection above 85°C. Dynamic voltage and frequency adjustment is achieved through DVFS technology, intelligently controlling fan speed and precisely adjusting the power supply strategy based on the real-time temperature curve. A temperature-power-performance mapping model is established, specifically a 3D Look-up Table, whose three dimensions are real-time temperature (T), target power consumption (P), and performance requirement level (L). Each entry in the table (T, P, L) correspond to a preset CPU operating frequency and core voltage (F, V) combination. The thermal management strategy queries this table based on the current input parameters to determine the optimal power state and dynamically adjusts the power state based on temperature data to ensure the chip operates within a safe temperature range. It works in conjunction with system-level thermal management to ensure the thermal balance of the entire system. The effectiveness of the thermal management strategy is tested through simulated overheating scenarios to ensure timely response to temperature changes.

[0033] A computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the steps in the aforementioned hardware-software co-optimization method for a BMC chip based on a RISC-V architecture.

[0034] An electronic device includes a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the hardware-software co-optimization method for a BMC chip based on a RISC-V architecture as described above.

[0035] Through the above-mentioned hardware and software co-optimization, the advantages of the RISC-V architecture can be fully utilized. While ensuring the performance requirements of traditional BMC chips, the characteristics of the RISC-V architecture can be used for upgrades, thereby accelerating the use of the RISC-V architecture in the BMC chip field.

[0036] These technical solutions optimize the performance, security, and power consumption of the BMC chip, and leverage the openness and flexibility of the RISC-V architecture to design more efficient and economical server management solutions.

[0037] This invention primarily focuses on the design of a RISC-V architecture BMC control chip for servers. Through the cooperation of software and hardware, the BMC chip is transformed from the traditional ARM architecture to the open-source RISC-V architecture. This involves some specific advantages of the RISC-V architecture. With the cooperation of hardware design and software stack, a BMC system with practical application significance is completed.

[0038] The beneficial effects of this invention are as follows: BMC chips based on the open-source RISC-V instruction set architecture can better meet the needs of current server systems. The emergence of the open-source RISC-V instruction set architecture has brought new opportunities to BMC design. Compared with proprietary architectures, RISC-V has the following advantages: 1. High scalability: The RISC-V core can be easily expanded according to the needs of different BMC applications.

[0039] 2. High customizability: The RISC-V architecture allows for extensive customization of the instruction set, peripherals, and storage subsystems to optimize specific BMC use cases.

[0040] 3. Lower cost: The open-source nature of RISC-V eliminates licensing fees, enabling more cost-effective BMC solutions.

[0041] 4. Abundant Ecosystem Support: The rapidly developing RISC-V ecosystem provides a variety of tools, IP, and software support to accelerate BMC development. Attached Figure Description

[0042] Figure 1 The overall architecture of the BMC chip based on the RISC-V architecture; Figure 2 Software architecture of BMC chip based on RISC-V architecture; Figure 3 Startup flowchart of BMC chip based on RISC-V architecture. Detailed Implementation

[0043] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0044] Example 1

[0045] A hardware-software co-optimization method for a RISC-V-based BMC chip involves the chip design, primarily focusing on the application of the RISC-V architecture. The RISC-V-based BMC chip includes core processing unit design, memory design, storage design, and peripheral interface design. Targeted optimizations are also made to the security functions and power management unit of the RISC-V-based BMC chip. The core processing unit of the BMC chip is designed using the RISC-V instruction set architecture, meeting the BMC's performance and power consumption requirements through a modular and scalable instruction set. Hardware acceleration is provided for BMC-specific functions (such as secure boot and encryption) through custom instruction extensions.

[0046] The design includes the following: (1) Hardware design The core processing unit of the BMC chip is designed using the RISC-V instruction set architecture (ISA). Based on the BMC's performance and power consumption requirements, a suitable RISC-V core is selected, choosing either the RV32E or RV64I core as the core processing unit. Using the RV64I architecture provides the BMC chip with a more complex system, a larger address space, and higher performance. The specific implementation is not limited to using open-source or commercial RISC-V cores, providing the BMC chip with 64-bit processor core processing capabilities.

[0047] The RISC-V instruction set is modular. A basic instruction set (such as RV32I or RV64I) is selected based on the needs of the BMC chip, and standard extensions (such as the M extension for integer multiplication and division, and the F extension for single-precision floating-point operations) are added. This design allows the BMC chip to be precisely matched to the required functions, avoiding unnecessary waste of hardware resources.

[0048] RISC-V's openness allows for the addition of custom instruction extensions, enabling BMC chips to support specific functions through hardware acceleration. For example, dedicated instructions can be added to the BMC to accelerate the processing of the IPMI (Intelligent Platform Management Interface) protocol.

[0049] Provide hardware acceleration for BMC-specific functions through custom instruction extensions. Acceleration is achieved using RISC-V extended instruction sets, including implementations of both standard RISC-V extended instruction sets and custom extended instruction sets. For example, extended instruction sets can be used for encryption functions, ensuring data encryption effectiveness and providing faster encryption and decryption operations. Specifically, this can be achieved by using the RISC-V standard instruction set extension K instruction extension to accelerate various encryption algorithms. This implementation can be applied to, but is not limited to, secure boot or other scenarios suitable for encryption, such as firmware signature verification and key management, directly calling hardware accelerators to execute tasks, thus improving boot speed and security.

[0050] Complete the overall design of the RISC-V based BMC chip. like Figure 1 The diagram illustrates the overall architecture of a BMC chip based on the RISC-V architecture. It outlines the contents of each module of a RISC-V architecture BMC chip, and the specific implementation of each module is shown below.

[0051] 1. Core Processing Unit Based on the performance and power consumption requirements of the BMC, the RV32E (32-bit embedded) or RV64I (64-bit general-purpose) cores are selected. Furthermore, the RISC-V core functions are tailored and expanded according to specific power consumption requirements. For example, adding V instructions enhances matrix operations, accelerating matrix operations in the BMC, which can speed up the deployment of localized AI algorithms, increase computational efficiency, and thus reduce corresponding power consumption.

[0052] Implement clock gating technology to shut down unused parts of the circuitry when inactive to save power.

[0053] 2. Memory Design Integrating small-capacity SRAM enables fast access to frequently used data and instructions, reducing reliance on external memory. Designing a DDR memory controller supports memory versions such as DDR3, DDR4, or higher. Optimizing memory access efficiency involves implementing caching mechanisms, prefetching strategies, and memory scheduling algorithms to improve memory access speed. Designing a memory subsystem specifically improves memory access efficiency by directly deploying a low-power SRAM controller and a DDR memory controller on the processor bus and configuring a dedicated memory management unit (MMU).

[0054] 3. Storage Design The BMC firmware is stored using SPI Flash, which supports remote firmware updates and provides sufficient capacity to store boot code, management software, and configuration data.

[0055] 4. Peripheral Interface Design It supports at least one peripheral interface to ensure broad compatibility with system components. Peripheral interfaces include, but are not limited to, I2C / SMBus, UART, GPIO, PCIe, and Ethernet interfaces.

[0056] I2C / SMBus: Implements an I2C or SMBus controller for communication with other components within the system, such as sensors and power modules. Supports multi-master mode, allowing multiple devices to share the bus.

[0057] UART: Provides a UART interface for debugging, log output, and possible low-speed data transmission. High-speed mode is supported to improve transmission efficiency.

[0058] GPIO: Integrated programmable GPIO pins for various control and monitoring functions, such as switches and indicator lights. Supports interrupts and event triggering.

[0059] PCIe: Design a PCIe interface to allow the BMC to communicate with the host system via a high-speed interface, supporting high-bandwidth data transmission. Consider root port or endpoint design, depending on the BMC's role in the system.

[0060] Ethernet interface: Integrated Gigabit Ethernet controller, supporting remote management. Implements TCP / IP protocol stack and related management protocols (such as IPMI over LAN, Redfish, etc.).

[0061] By designing a dedicated bus interface between the processor core and peripheral circuits, precise mapping and scheduling of processor resources can be achieved, optimizing area and power consumption, and making it suitable for the low power requirements of BMC.

[0062] Firmware updates via firmware storage involve the following steps: implementing and designing a firmware update mechanism that supports remote updates via network or other interfaces; the specific process includes downloading, verifying, storing, and applying the update, while providing a rollback mechanism to handle update failures. The rollback mechanism includes designing a dual-partition storage strategy to quickly switch to the backup partition and restore to the previous stable state in case of firmware update failure, ensuring continuous system operation. Specifically, this can be achieved by using a network interface to transmit encrypted firmware to Flash memory, storing the firmware in Flash, identifying the firmware name through the BMC operating system to determine whether it is BMC firmware or Host firmware, accelerating decryption and verification through a decryption module, and finally completing the corresponding firmware update.

[0063] Software optimization of the BMC chip based on the RISC-V architecture was carried out in three aspects: optimization of the basic software functions (2), optimization of security functions (3), and optimization of the power management unit (4). The optimization strategy ensures that the chip retains the functions of a traditional BMC chip while highlighting the characteristics of the RISC-V architecture. For example, security strategies and power consumption management. Ultimately, through hardware and software co-optimization, efficient system management, monitoring, and control functions were achieved. The software architecture of the RISC-V-based BMC chip is as follows: Figure 2 As shown.

[0064] (2) Software optimization Based on the RISC-V architecture, a lightweight real-time operating system for BMC is built by customizing the kernel, customizing the scheduler, and configuring security isolation mechanisms, supporting real-time task scheduling and security.

[0065] Its specific construction steps include: Step S1: Kernel trimming; Select an open-source real-time operating system that supports the RISC-V architecture as the base, and trim its kernel according to the functional requirements of the BMC chip, removing unnecessary components to reduce system size and memory usage; Specifically, trim the file system, graphical interface library, and unnecessary network protocol stacks (such as FTP, Telnet), retaining only core functions such as task scheduling, memory management, interrupt handling, and IPC (inter-process communication); Step S2: Scheduler customization; To meet the real-time requirements of BMC tasks, customize the operating system's task scheduler; Adopt a priority-based preemptive scheduling strategy to allocate the highest preemptive priority to high-priority critical tasks (such as temperature monitoring and power failure alarms) to ensure their response time is in the millisecond range; Assign lower priority to low-priority tasks (such as log recording and web interface data updates) to execute them when the system is idle; Step S3: Configure security isolation mechanism; Utilize the Physical Memory Protection (PMP) function of the RISC-V architecture to configure independent memory protection areas for critical tasks (including secure boot and firmware updates) and general management tasks; By configuring PMP registers, restrict different tasks to access only their authorized memory address space and peripherals, preventing the crash or attack of a single task from affecting the stability and security of the entire system.

[0066] Based on the RISC-V security extension instruction set, a multi-stage boot firmware bootloader is constructed, integrating a hardware encryption engine, an image signature verification module, and a trusted boot verification process to ensure the integrity and security of the firmware. The RISC-V security extension instruction set is a standardized instruction set defined by RISC-V for accelerating symmetric encryption, hash algorithms, and public-key cryptography.

[0067] The multi-stage boot firmware bootloader includes the following steps: Bootloader & Firmware: Optimized for booting and booting RISC-V architecture BMC chips. Initialization for RISC-V chips uses a step-by-step boot process, specifically including the following stages: ZSBL, SBI, U-Boot, and Linux. The specific implementation is not limited to these methods; it can be ZSBL + openSBI + U-Boot + OpenBMC (Linux). The specific process is as follows... Figure 3 As shown.

[0068] Hardware Abstraction Layer (HAL): Located between the operating system and the physical hardware, it shields the implementation differences of the underlying hardware. In a RISC-V environment, openSBI is preferred as the implementation of HAL. It encapsulates the core hardware operation details of the underlying CPU, such as privilege mode switching, interrupt management, and timer access, thereby providing a standardized hardware access interface for the upper-layer operating system. This allows different operating systems (such as Linux or RTOS) to run without modification for specific hardware. HAL is the key technology layer for decoupling all upper-layer software functions from the underlying hardware in this invention.

[0069] Operating System: Selected and optimized based on the specific architecture and application scenario of the BMC chip; 1. When the BMC chip adopts the resource-constrained RV32 architecture, or when there are strict real-time requirements for tasks such as precise fan speed control and emergency power failure handling (e.g., response time must be in the microsecond or millisecond range), a lightweight real-time operating system (RTOS) can be built using the method described above. 2. When the BMC chip adopts the relatively resource-rich RV64 architecture and needs to support complex management functions such as a complete network protocol stack and web server, the full-featured Linux operating system should be selected, and customized development can be carried out based on the open-source OpenBMC project.

[0070] Firmware and drivers are software modules written or ported based on each peripheral interface (such as I2C / SMBus, UART, GPIO, PCIe, etc.) integrated into the BMC chip by HAL. According to the hardware specifications of each interface, drivers are designed and implemented, including functions such as device initialization, data transmission, interrupt handling, and error handling. For example, for the I2C interface, the Linux kernel's I2C framework is used to implement read and write functions for the slave device; for the UART interface, its baud rate configuration and data transmission / reception functions are implemented. These drivers interact with the hardware through HAL to ensure its ability to work with the operating system and to optimize performance and power consumption.

[0071] Application Layer and BMC Management Software: This layer primarily develops or ports BMC-specific application software, specifically independent application modules for power management, temperature monitoring, and fan control. These modules ensure flexible configuration and invocation, exchange data with the hardware layer using standard APIs, handle system management tasks, and perform power management, temperature control, and fan control. The layer also ensures these software programs can interact with the underlying hardware through the operating system's APIs. A user-friendly interface, including a web interface or command-line interface (CLI), is provided, supporting configuration, monitoring, and log viewing functions. The web interface is provided via an HTTP / HTTPS server, while the CLI is implemented through specific command-line tools.

[0072] For the BMC management interface, the IPMI and Redfish protocol stack implementations were refactored to enable it to perform protocol communication functions on an operating system under the RISC-V architecture.

[0073] The IPMI and Redfish protocol stack implementation was refactored, specifically including: configuring the BMC management software, which involves implementing a centralized configuration tool that allows users to set various management parameters, such as device address, communication rate, and monitoring thresholds, through a graphical interface or CLI, in order to adjust the system's operating status in real time; implementing the IPMI and Redfish interface, specifically based on RISC-V security extensions; refactoring the IPMI and Redfish protocol stack to implement an end-to-end encrypted communication channel, supporting multi-factor authentication and fine-grained access control policies, providing remote monitoring and management functions, and ensuring good integration with the operating system and hardware. This system enables status acquisition and analysis, recording system events, errors, alarms, and other information, providing real-time monitoring and logging. It supports KVM over LAN functionality, allowing remote management and control of the system, and provides a remote access interface supporting operations such as power on / off, restart, and configuration. It implements multiple authentication and authorization mechanisms, specifically: Role-Based Access Control (RBAC): defining different roles such as administrators, operators, and regular users, and precisely assigning different operation permissions (such as configuration modification, firmware updates, log viewing, etc.) to each role, thereby achieving minimal and fine-grained permission management; and Multi-Factor Authentication (MFA): adding a second authentication factor to traditional username and password authentication, such as requiring users to provide a one-time password (OTP) generated through an out-of-band channel (such as a mobile application), significantly enhancing login security. Mandatory Access Control (MAC): Utilizing operating system kernel-level security policies (such as SELinux), MAC sets fixed security labels and access rules for processes and files, forcibly restricting the permission scope of critical processes (such as the IPMI service process). Even if compromised, these processes cannot access other system resources without authorization, thus providing a deeper level of protection. It ensures that only authorized users can access the BMC, while also providing data encryption, secure transmission, and other functions to protect system and data security.

[0074] (3) Security function optimization An integrated hardware-accelerated encryption engine enhances the security of data transmission and storage.

[0075] Implement a secure boot mechanism to ensure the integrity and security of the firmware during the BMC boot process.

[0076] By leveraging the rich extension instructions of the RISC-V architecture, a secure boot process for the BMC chip is provided. Specifically, a dedicated secure boot hardware module is used, employing RISC-V Z extension instructions, which provide hardware cryptographic primitives, secure hash calculations, and signature verification functions.

[0077] Specifically, it includes: Design a RISC-V-based secure bootloader (such as the existing ZSBL program) that can directly interact with the hardware acceleration module. Within the bootloader, a hardware accelerator is used to perform integrity verification and authentication of the boot code, ensuring that only authenticated firmware can boot. The hardware accelerator is also used to accelerate encryption algorithms (such as RSA and SHA) to improve boot speed. The integrity and speed of the secure boot process are tested and verified to ensure both security and efficiency.

[0078] Encryption and decryption hardware acceleration: Hardware Accelerator Design: Design or integrate a hardware accelerator that supports common encryption algorithms (such as existing AES, RSA, SHA, etc.), ensuring its compatibility with the RISC-V core; integrate the hardware accelerator into the RISC-V BMC chip, ensuring it can be directly called by the operating system and application layer; develop drivers that allow the openBMC operating system to recognize and use this hardware accelerator for encryption and decryption operations; link the openBMC encryption library, prioritizing the use of the hardware accelerator for encryption and decryption operations to reduce CPU load; conduct performance testing, comparing the efficiency of hardware acceleration and software encryption to ensure the acceleration effect of the encryption process. Ensure the security of the hardware accelerator to prevent unauthorized access and use.

[0079] (4) Optimization of power management unit Design a dedicated power management unit (PMU) that supports multiple power states and enables low-power modes.

[0080] Leveraging the programmability of RISC-V, power management strategies can be dynamically adjusted to adapt to different workloads.

[0081] Multi-Power State Support: A power management unit (PMU) supporting multiple power states is designed. Based on existing IPMI power management specifications and the OpenPOWER standard, and combined with a RISC-V architecture power management unit, it implements modes including active, sleep, and standby. Control of the PMU is implemented in openBMC, a DBus-based powered daemon is developed, a state transition event listening mechanism is constructed, and RESTful APIs and systemd service interfaces are provided to achieve fine-grained management and rapid switching of power states, supporting the switching of multiple power states. Specifically, a multi-dimensional intelligent automatic power state switching mechanism is constructed: It enters shallow sleep when CPU utilization is 0-30%, remains active between 30-60%, and maintains high-performance mode above 60%; combined with temperature management, it automatically reduces the power state when the chip temperature exceeds 75°C; it intelligently adjusts the depth of energy-saving mode based on system idle time; it performs dynamic energy consumption optimization while ensuring the real-time performance of critical services, automatically switching to the optimal power state based on the current system state (such as load and temperature); and it ensures the stability and security of the power state switching process, avoiding system crashes or data loss.

[0082] Power management unit optimization also includes thermal management: monitoring the temperature of the BMC chip and adjusting the power state according to the temperature to prevent overheating. Integrating temperature monitoring functionality into openBMC involves integrating multiple temperature sensors (such as LM75 and DS18B20) via the I2C bus, configuring a temperature acquisition cycle of 1-2 seconds, developing a DBus-based temperature data communication daemon process called thermal-monitor, and building a monitoring system that includes temperature threshold configuration, real-time monitoring, and alarm notifications. A RESTful API interface is provided to enable remote querying of temperature data, ensuring the system can acquire temperature data in real time. A thermal management strategy is designed, specifically a four-level temperature response mechanism: full performance operation from 0-60°C, CPU frequency reduction of 15-25% from 60-75°C, active frequency reduction and shutdown of non-critical modules from 75-85°C, and emergency power-down protection above 85°C. Dynamic voltage and frequency adjustment is achieved through DVFS technology, intelligently controlling fan speed and precisely adjusting the power supply strategy based on the real-time temperature curve. A temperature-power-performance mapping model is established, specifically a 3D look-up table. The three dimensions are real-time temperature (T), target power consumption (P), and performance requirement level (L). Each entry in the table (T, P, ...) represents a specific value. L corresponds to a preset CPU operating frequency and core voltage (F, V) combination. The thermal management strategy queries this table based on the current input parameters to determine the optimal power state and dynamically adjusts the power state based on temperature data to ensure the chip operates within a safe temperature range. It works in conjunction with system-level thermal management to ensure the thermal balance of the entire system. The effectiveness of the thermal management strategy is tested through simulated overheating scenarios to ensure timely response to temperature changes.

[0083] Example 2

[0084] A computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the steps in a hardware-software co-optimization method for a BMC chip based on a RISC-V architecture as described in Example 1.

[0085] Example 3

[0086] An electronic device includes a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the hardware-software co-optimization method for a BMC chip based on a RISC-V architecture as described in Example 1.

Claims

1. A hardware-software co-optimization method for a BMC chip based on a RISC-V architecture, characterized in that, The design includes the following: (1) Hardware design The RV32E or RV64I core is selected as the core processing unit of the BMC. A dedicated bus interface is designed between the processor core and the peripheral circuits. A memory subsystem is designed, and a low-power SRAM controller and DDR memory controller are directly deployed on the processor bus. A dedicated storage management unit is configured, and SPI Flash is used for firmware storage to support remote firmware updates. Supports at least one peripheral interface; (2) Software optimization Based on the RISC-V architecture, a lightweight real-time operating system for BMC is built by trimming the kernel, customizing the scheduler, and configuring security isolation mechanisms. Based on the RISC-V security extension instruction set, a multi-stage boot firmware bootloader is constructed, integrating a hardware encryption engine, an image signature verification module, and a trusted boot verification process. The RISC-V security extension instruction set is a standardized instruction set defined by RISC-V for accelerating symmetric encryption, hash algorithms, and public-key cryptography. For the BMC management interface, the IPMI and Redfish protocol stack implementations were refactored to enable it to perform protocol communication functions on an operating system under the RISC-V architecture. (3) Security function optimization An integrated hardware-accelerated encryption engine; Implement a secure boot mechanism; By leveraging the extended instructions of the RISC-V architecture, a secure boot process for the BMC chip is provided. Specifically, a dedicated secure boot hardware module is used, employing the RISC-V Z extended instructions, which provide hardware cryptographic primitives, secure hash calculations, and signature verification functions. Specifically, it includes: Design a RISC-V-based secure bootloader that interacts directly with the hardware acceleration module. The bootloader uses a hardware accelerator to perform integrity verification and authentication of the boot code, ensuring that only authenticated firmware can boot. The hardware accelerator accelerates the encryption algorithm, and the integrity and speed of secure boot are tested and verified. Encryption and decryption hardware acceleration: Hardware Accelerator Design: Design or integrate a hardware accelerator that supports common encryption algorithms, ensuring compatibility with the RISC-V core; integrate the hardware accelerator into the RISC-V BMC chip, ensuring it can be directly invoked by the operating system and application layer; develop drivers that allow the openBMC operating system to recognize and use this hardware accelerator for encryption and decryption operations; link the openBMC encryption library, prioritizing the use of the hardware accelerator for encryption and decryption operations; conduct performance testing to compare the efficiency of hardware acceleration and software encryption, preventing unauthorized access and use. (4) Optimization of power management unit Design a dedicated power management unit (PMU); Leveraging the programmability of RISC-V, power management strategies can be dynamically adjusted to adapt to different workloads.

2. The hardware and software co-optimization method for a BMC chip based on RISC-V architecture according to claim 1, characterized in that, In step (1), peripheral interfaces include, but are not limited to, I2C / SMBus, UART, GPIO, PCIe, and Ethernet interfaces.

3. The hardware and software co-optimization method for a BMC chip based on RISC-V architecture according to claim 1, characterized in that, In step (1), the firmware update of the firmware storage includes the following steps: implementing a firmware update mechanism, designing a firmware update mechanism that supports remote updates via network or other interfaces; the specific process includes downloading, verifying, storing and applying the update, while providing a rollback mechanism to deal with update failures. The rollback mechanism includes: designing a dual-partition storage strategy, which can quickly switch to the backup partition and restore to the previous stable state when the firmware update fails; using the network interface to transmit encrypted firmware to Flash; using Flash to complete firmware storage; using the BMC operating system to identify the firmware name and analyze whether it is BMC firmware or Host firmware; and decrypting and verifying through the decryption module to finally complete the update of the corresponding firmware.

4. The hardware and software co-optimization method for a BMC chip based on RISC-V architecture according to claim 1, characterized in that, In step (2), a lightweight real-time operating system for BMC is constructed. The specific construction steps include: Step S1: Kernel trimming; Select an open-source real-time operating system that supports the RISC-V architecture as the base, and trim its kernel according to the functional requirements of the BMC chip; Step S2: Scheduler customization; To meet the real-time requirements of BMC tasks, customize the operating system's task scheduler; Adopt a priority-based preemptive scheduling strategy, assigning the highest preemptive priority to high-priority tasks and assigning lower priority to low-priority tasks, which will be executed when the system is idle; Step S3: Configure security isolation mechanism; Utilize the physical memory protection function of RISC-V architecture to configure independent memory protection areas for tasks; By configuring the PMP register, restrict different tasks to only access their authorized memory address space and peripherals.

5. The hardware and software co-optimization method for a BMC chip based on RISC-V architecture according to claim 1, characterized in that, In step (2), the multi-stage boot firmware bootloader includes the following steps: Bootloader and firmware: Optimize boot and boot processes for BMC chips based on RISC-V architecture. For chips based on RISC-V architecture, a step-by-step boot method is used for initialization, specifically including the following stages: ZSBL, SBI, U-Boot, and linux. Hardware Abstraction Layer (HAL): Located between the operating system and physical hardware, it shields the implementation differences of the underlying hardware. In the RISC-V environment, openSBI is used as the implementation of HAL. It encapsulates the privilege mode switching, interrupt management, and timer access details of the underlying CPU, thereby providing a standardized hardware access interface for the upper-level operating system, so that different operating systems can run without modification for specific hardware. Operating system: Selected and optimized based on the specific architecture and application scenario of the BMC chip; 1) When the BMC chip uses the resource-constrained RV32 architecture, or when there are strict real-time requirements for precise fan speed control and emergency power failure handling tasks, a lightweight real-time operating system can be built using the method described above. 2) When the BMC chip adopts the relatively resource-rich RV64 architecture and needs to support a complete network protocol stack and complex web server management functions, the full-featured Linux operating system should be selected, and customized development can be carried out based on the open-source OpenBMC project. Firmware and drivers are software modules written or ported based on HAL for each peripheral interface integrated into the BMC chip; Based on the hardware specifications of each interface, design and implement drivers that include device initialization, data transmission, interrupt handling, and error handling functions; these drivers interact with the hardware through HAL. Application Layer and BMC Management Software: This layer primarily develops or ports BMC-specific application software, specifically independent application modules for power management, temperature monitoring, and fan control. These modules exchange data with the hardware layer using standard APIs, handle system management tasks, and perform power management, temperature control, and fan control. The software can interact with the underlying hardware through the operating system's APIs. It provides a user-friendly interface, including a web interface or command-line interface (CLI). The web interface is provided via an HTTP / HTTPS server, while the CLI is implemented through specific command-line tools.

6. The hardware and software co-optimization method for a BMC chip based on RISC-V architecture according to claim 1, characterized in that, In step (2), the IPMI and Redfish protocol stack implementation is reconstructed, specifically including: completing the configuration of the BMC management software, specifically implementing a centralized management configuration tool that allows users to set various management parameters through a graphical interface or CLI; implementing the IPMI and Redfish interface, specifically based on RISC-V security extensions; reconstructing the IPMI and Redfish protocol stack; implementing an end-to-end encrypted communication channel; supporting multi-factor authentication and fine-grained access control policies; implementing system status acquisition and analysis functions; recording system events, errors, and alarm information; providing real-time monitoring and logging; supporting KVM over LAN functionality, allowing remote management and control of the system, while providing a remote access interface; supporting power on / off, restart, and configuration operations; implementing multiple authentication and authorization mechanisms, specifically setting role-based access control. Define different roles such as administrator, operator, and ordinary user, and assign different operation permissions to each role; implement multi-factor authentication: add a second authentication factor on the basis of traditional username and password authentication, and enforce access control: use the operating system kernel-level security policy to set fixed security labels and access rules for processes and files, forcibly restrict the permission scope of critical processes, ensure that only authorized users can access BMC, and provide data encryption and secure transmission functions.

7. The hardware and software co-optimization method for a BMC chip based on RISC-V architecture according to claim 1, characterized in that, In step (4), a power management unit (PMU) is designed. Based on the existing IPMI power management specification and OpenPOWER standard, and combined with the RISC-V architecture power management unit, active, sleep, and standby modes are implemented. The control of the PMU is implemented in openBMC. A DBus-based powered daemon process is developed, a state transition event listening mechanism is constructed, and RESTful API and systemd service interfaces are provided. Specifically, a multi-dimensional intelligent power state automatic switching mechanism is constructed: when the CPU utilization is 0-30%, it enters shallow sleep; when it is 30-60%, it remains active; and when it is above 60%, it maintains high-performance mode. Combined with temperature management, the power state is automatically reduced when the chip temperature exceeds 75°C. The depth of the energy-saving mode is intelligently adjusted according to the system idle time. Dynamic energy consumption optimization is performed, and the system automatically switches to the optimal power state according to the current state of the system.

8. The hardware and software co-optimization method for a BMC chip based on RISC-V architecture according to claim 1, characterized in that, In step (4), the power management unit optimization also includes thermal management: monitoring the temperature of the BMC chip, adjusting the power state according to the temperature, integrating temperature monitoring function in openBMC, specifically integrating multiple temperature sensors through the I2C bus, configuring a temperature acquisition cycle of 1-2 seconds, developing a temperature data communication daemon process based on DBus thermal-monitor, building a monitoring system including temperature threshold configuration, real-time monitoring, and alarm notification, providing a RESTful API interface to realize remote query of temperature data, and the system obtains temperature data in real time; designing a thermal management strategy, further specifically, building a four-level temperature response mechanism: full performance operation at 0-60°C, reducing CPU frequency by 15-25% at 60-75°C, starting active frequency reduction and shutting down non-critical modules at 75-85°C, and executing emergency power-down protection above 85°C; realizing dynamic voltage and frequency adjustment through DVFS technology, controlling fan speed, accurately adjusting the power supply strategy according to the real-time temperature curve, and establishing a temperature-power-performance mapping model, which specifically constitutes a three-dimensional lookup table, whose three dimensions are real-time temperature T, target power consumption P, and performance requirement level L, and each entry T in the table, P and L correspond to a preset CPU operating frequency and core voltage F and V combination; the thermal management strategy queries this table based on the current input parameters to determine the optimal power state and dynamically adjusts the power state based on temperature data.

9. A computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the steps in the hardware-software co-optimization method for a BMC chip based on a RISC-V architecture as described in claim 1.

10. An electronic device, comprising a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps in the hardware-software co-optimization method for a BMC chip based on a RISC-V architecture as described in claim 1.

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