Memory device, computer system and memory die

Abstract

The invention discloses a storage device, a computer system and a storage bare chip, which can meet high-speed data transmission requirements of AI reasoning tasks and the like. The storage device comprises a logic layer and a storage layer. The logic layer comprises: a centralized power management subsystem configured to convert a base voltage into a preset adaptive voltage; and the power distribution network is configured to be electrically connected with the voltage distribution channel so as to distribute the preset adaptive voltage to each storage bare chip. Each storage bare chip is configured with a sub-array level parallelism control circuit which is electrically connected with the plurality of independent sub-arrays and the signal synchronization channel and is used for carrying out parallel access scheduling on the plurality of independent sub-arrays based on a control signal so as to adapt to write-in transmission of write-in parallel data signals and read transmission of read parallel data signals; and the voltage input interface is electrically connected with the voltage distribution channel so as to receive the preset adaptive voltage. In each storage die, a local mating circuit is electrically connected with the parallel data channel to receive a write parallel data signal or output a read parallel data signal.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and more specifically, to a storage device, a computer system, and a storage die. Background Technology

[0002] With the rapid development of scenarios such as artificial intelligence inference and high-performance computing, the scale of data processing continues to expand, placing increasingly stringent demands on the bandwidth, latency, and power supply stability of storage systems. To meet these needs, high-bandwidth storage architectures (such as high-bandwidth memory HBM and high-bandwidth flash memory HBF) have emerged. These storage architectures generally adopt a 3D stacked integration design, which vertically stacks multiple layers of storage dies with logic layers and uses interconnect components such as through-silicon vias (TSVs) and bonding layers to achieve inter-layer signal and power transmission, significantly improving the parallelism of data transmission and space utilization.

[0003] In existing high-bandwidth storage architectures, each layer of storage dies is typically configured with an independent power management component to perform power-related functions such as voltage conversion and stabilization, ensuring the normal operation of its own storage cells and associated circuits. However, this distributed power supply design has significant drawbacks: because the power management components of each die operate independently, the lack of global coordinated control can easily lead to deviations in the power supply voltage of different dies, making it difficult to guarantee consistency; at the same time, configuring power components for each layer of dies increases the transmission loss of cross-layer power supply, and the redundant power component design also occupies valuable space resources inside the die, limiting the layout of storage cells or parallel scheduling-related circuits, making it difficult to support the stringent power supply stability requirements of parallel transmission of multiple dies and multiple subarrays.

[0004] On the other hand, existing parallel scheduling mechanisms in storage architectures are mostly concentrated at the die level or chip level, that is, controlling multiple storage dies to read and write data simultaneously through the logic layer to improve parallelism. However, as the capacity of storage cell arrays continues to increase, a single die storage cell array is divided into multiple independent subarrays to further improve access flexibility, but existing scheduling mechanisms lack precise scheduling schemes for these independent subarrays. When multiple independent subarrays are accessed in parallel, due to the lack of dedicated scheduling and channel configuration, channel conflicts and resource contention are prone to occur, resulting in limited data transmission efficiency and failing to fully realize the parallel access potential of the 3D stacked architecture. Consequently, it is difficult to meet the core requirements of high bandwidth and low latency for massive model weights and feature map data interaction in AI inference scenarios. Summary of the Invention

[0005] This disclosure was developed to address the aforementioned technical problems, and its purpose is to provide a storage device capable of meeting the high-speed data transmission requirements of AI inference tasks, etc. Furthermore, this disclosure also provides a computer system including the storage device and a storage die for the storage device.

[0006] This disclosure provides a storage device, including a logic layer and a storage layer. The logic layer and the memory layer are communicatively connected via bonding layers and through-silicon vias. The storage layer comprises multiple layers of vertically stacked storage dies, each of which is provided with a storage cell array and local supporting circuitry. The storage cell array is divided into multiple independent sub-arrays. The logic layer is configured as follows: It can provide inputs of external base voltage, access requests from external devices, external data, and read parallel data signals from the storage layer; and It can output a preset adaptation voltage adapted to the operation of each of the memory dies in the memory layer, as well as a control signal and a write parallel data signal formed after the logic layer processes the access request and the external data respectively. None of the aforementioned memory dies are equipped with die-level power management components. The through-silicon via includes a voltage distribution channel and a signal synchronization channel. The bonding layer includes a parallel data channel capable of transmitting the read parallel data signal and the write parallel data signal. The logical layer includes: A centralized power management subsystem, configured to convert the base voltage to the preset adaptive voltage; and A power distribution network, configured to be electrically connected to the voltage distribution channel, to distribute the preset adaptive voltage to each of the memory dies. Each of the aforementioned memory dies is configured with: A subarray-level parallelism control circuit, electrically connected to the plurality of independent subarrays and the signal synchronization channel, receives the control signal and performs parallel access scheduling of the plurality of independent subarrays based on the control signal to adapt to the write transmission of the write parallel data signal and the read transmission of the read parallel data signal; and A voltage input interface, electrically connected to the voltage distribution channel, is provided to receive the preset adaptive voltage. Furthermore, in each of the aforementioned memory dies, the local supporting circuitry is electrically connected to the parallel data channel to receive the write parallel data signal or output the read parallel data signal.

[0007] According to the storage device described in this technical solution, by extracting the die-level power management components from each storage die, a centralized power management subsystem and power distribution network are integrated at the logic layer. Combined with the voltage distribution channels of through-silicon vias (TSVs), this achieves unified conversion and precise allocation of preset adaptive voltages, effectively avoiding problems such as poor voltage consistency and high cross-layer transmission loss caused by decentralized power supply. This provides stable and reliable power support for the parallel operation of multiple dies and subarrays. Simultaneously, the space freed up by extracting the die-level power management components is used to add a subarray-level parallelism control circuit. This circuit receives control signals through a signal synchronization channel and performs parallel access scheduling for multiple independent subarrays. Combined with the parallel data channel of the bonding layer, it achieves efficient transmission of write and read parallel data signals, significantly improving the scheduling accuracy of subarray access and the parallelism of data transmission. This avoids channel conflicts and resource contention during parallel access of multiple subarrays, effectively reducing data transmission latency and fully leveraging the parallel access potential of the 3D stacked architecture, thereby better meeting the needs of high-bandwidth, low-latency storage applications. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating a computer system using a storage device according to an embodiment of this application.

[0009] Figure 2 This is a main architecture diagram illustrating a storage device according to an embodiment of this application.

[0010] Figure 3 It means based on Figure 2 The diagram shows a data write operation implemented by the storage device.

[0011] Figure 4 It means based on Figure 2 The diagram shows a data read operation performed by the storage device. Detailed Implementation

[0012] Figure 1 A schematic diagram of a computer system O employing a storage device S according to an embodiment of this application is shown. In some embodiments, the computer system O is a high-performance computer system designed specifically for AI inference scenarios, capable of meeting the requirements for high bandwidth, low latency, and stable power supply during large model inference processes, and effectively improving the computational efficiency and data processing rate of AI inference tasks.

[0013] (Overall architecture of computer system O)

[0014] like Figure 1 As shown, the computer system O mainly includes a package substrate 7, an interposer 6, an external device 1, and a storage device S.

[0015] From a physical structure perspective, the computer system O adopts a top-down hierarchical integrated architecture. The packaging substrate 7 serves as the bottom layer carrier and interconnection foundation for the entire system. The interposer layer 6 is integrated on top of the packaging substrate 7. External devices 1 and storage devices S are both mounted on the interposer layer 6, through which electrical connections are achieved with the packaging substrate 7. Thus, a complete functional system of "bottom layer carrier - intermediate interconnection - upper layer computing and storage" is formed.

[0016] The following sections will describe each of the core components in detail, from bottom to top.

[0017] (Packaging substrate 7)

[0018] The packaging substrate 7 is a core basic component in the semiconductor packaging process and also serves as the physical support and electrical connection basis for this computer system.

[0019] First, the packaging substrate 7 provides a stable installation environment for the upper interlayer 6, external device 1 and storage device S, protecting each component from external environmental factors such as dust and moisture.

[0020] Secondly, the packaging substrate 7 uses its internal wiring structure to realize the signal transmission and power distribution links between each upper-layer component and the external circuit, and build a low-noise, low-latency signal loop.

[0021] In addition, the packaging substrate 7 can conduct the heat generated during the operation of the external device 1 and the storage device S to the external heat dissipation structure, while alleviating the mechanical stress generated during the component integration process.

[0022] In particular, in AI inference scenarios, the design of wiring density and electrical performance ensures that the package substrate 7 can meet the high bandwidth data transmission requirements, thereby ensuring the continuous and stable operation of AI inference tasks.

[0023] (Intermediary layer 6)

[0024] Intermediate layer 6 is an interconnect component located between the packaging substrate 7 and the external device 1 and storage device S, and is a high-density circuit conversion board.

[0025] First, the interposer layer 6 ensures high-bandwidth, low-latency signal transmission between the external device 1 and the storage device S through its integrated redistribution layer (RDL) and through-silicon via (TSV) structure, minimizing the signal trace length between the two and reducing data transmission power consumption and latency.

[0026] Furthermore, by employing intermediary layer 6, it is possible to adapt to chips with different processes and functions (such as computing chips and memory chips), thereby enabling heterogeneous integration at the packaging level, achieving system-level collaborative operation without integrating all functions onto a single chip.

[0027] In particular, in AI inference application scenarios, the storage device S and the external device 1 exchange a large amount of inference data rapidly through the intermediary layer 6. The interconnection density and transmission efficiency affect the response speed of AI inference tasks.

[0028] (External device 1)

[0029] External device 1 is the core of computer system O's computation, such as a GPU, CPU, TPU, SoC, or other functional chips. This external device 1 establishes data interaction with the storage device S through the aforementioned intermediary layer 6 to realize the computational flow of AI inference tasks. Here, for ease of understanding, the various functional chips mentioned above are briefly described.

[0030] The CPU (Central Processing Unit) is the general-purpose computing and control core of a computer system. Through the integration of an arithmetic logic unit (ALU), high-speed cache memory, and data bus, it is responsible for interpreting computer instructions and processing various types of data in the system. The VPU is characterized by its strong versatility, ability to efficiently handle complex serial tasks, and overall coordination of the workflow of various components in the system. It is the "central brain" of the AI ​​inference system, responsible for task scheduling and resource allocation.

[0031] GPU (Graphics Processing Unit), also known as a display core, employs a massively parallel computing architecture and possesses a large number of computing units. Compared to CPUs, GPUs have stronger parallel data processing capabilities, enabling them to handle a large number of repetitive matrix operations and data parallel processing tasks during large model inference more efficiently, thus significantly improving the throughput of inference operations.

[0032] TPU (Tensor Processing Unit) is an application-specific integrated circuit (ASIC) designed for machine learning tasks, specifically for tensor operations. Therefore, it requires fewer transistors and is more energy efficient when performing operations such as matrix multiplication and convolution required for AI inference, significantly reducing power consumption and latency during the inference process.

[0033] A SoC (System-on-Chip) is a highly integrated component that integrates the core functions of a computer system (such as CPU core, GPU core, memory controller, I / O interface, etc.) onto a single chip. SoCs are characterized by high integration, small size, and low power consumption, providing the comprehensive computing power required for AI inference within a limited space, making them suitable for AI inference scenarios with strict size and power consumption requirements, such as edge computing and device-side computing.

[0034] In some embodiments, the package substrate 7 and the interposer 6 are mechanically and electrically connected, for example, using arrayed solder balls (such as BGA solder balls) or microbumps. The surface of the package substrate 7 is treated with surface treatment processes such as ENEPIG to improve soldering reliability. The interposer 6 forms vertical interconnect channels with the back copper bumps through through-silicon vias (TSVs), forming ohmic contacts with the pads of the package substrate to construct interconnect links. Alternatively, the stress effects of package warpage can be mitigated by adjusting the solder ball spacing. Based on this, power signals, control and feedback signals, and ground signals are transmitted between the package substrate 7 and the interposer 6.

[0035] Intermediate layer 6 and external device 1 are heterogeneously integrated using high-density interconnect technology. For example, in some embodiments, intermediate layer 6 and external device 1 are flip-chip bonded via a micron-level microbump array, or copper-copper hybrid bonding can be used. Furthermore, intermediate layer 6 integrates a multilayer redistribution layer (RDL) and a TSV structure to form horizontal and vertical interconnect channels. Based on this, data signals, control signals, and power signals are transmitted between intermediate layer 6 and external device 1. Specifically, regarding data signals, external device 1 transmits model weight data, feature map data, and intermediate computation results required for AI inference to intermediate layer 6, while intermediate layer 6 transmits the inference data read results returned by storage device S to external device 1. Regarding control signals, these include read / write control commands, address selection commands, and timing synchronization clocks output by external device 1. Regarding power signals, the voltage provided by the package substrate 7 is distributed to external device 1 through the power distribution network built into intermediate layer 6, maintaining power supply stability.

[0036] In some implementations, the intermediary layer 6 and the storage device S are mechanically and electrically connected, for example, through hybrid bonding (CBA) technology or a high-density microbump array. Based on this, data signals, control and verification signals, and power signals are transmitted between the intermediary layer 6 and the storage device S. Regarding data signals, for example, the intermediary layer 6 transmits stored AI inference data (such as model weights and feature caches) issued by the external device 1 to the storage device S, and the storage device S transmits stored inference data and partially processed computation results to the intermediary layer 6. Regarding control and verification signals, the intermediary layer 6 transmits control commands from the external device 1, such as read / write enable and subarray selection, as well as corresponding CRC check signals and timing synchronization signals, to the storage device S. Regarding power signals, the base voltage required by the centralized power management subsystem 23 of the storage device S (described later) is transmitted to the storage device S through the power supply channel formed by the TSV and RDL of the intermediary layer, while simultaneously feeding back the power supply status signal of the storage device S.

[0037] It should be noted that external device 1 and storage device S are not directly physically connected, but are indirectly interconnected through intermediary layer 6. External device 1 and storage device S perform downlink (external device 1 → storage device S) and uplink (storage device S → external device 1) data transmission. Downlink data includes external data related to the AI ​​inference task (e.g., large model weight data to be written, feature map data during inference), supporting read / write control commands (e.g., data write address, read range, parallel operation mode selection commands), and timing synchronization signals to ensure timing alignment of multi-channel data transmission. Uplink data includes inference data read by storage device S, operating status feedback signals of storage device S (e.g., storage cell occupancy rate, power supply stability, subarray parallel operation status), and abnormal alarm signals (e.g., data verification errors, storage cell fault indications, etc.).

[0038] (Storage device S)

[0039] Next, we will refer to Figure 2 The main architecture of the storage device S according to one embodiment of this application will be described.

[0040] like Figure 1 As shown, the storage device S according to one embodiment of this application adopts a vertically stacked integrated architecture, mainly including a logic layer 2, a bonding layer 3, through-silicon vias (TSVs) 4, and a storage layer 5. The logic layer 2 and the storage layer 5 are communicatively connected through the bonding layer 3 and the TSVs 4. The bonding layer 3 is located between the upper surface of the logic layer 2 and the lower surface of the storage layer 5 (more precisely, the lower surface of the bottommost storage die 51 in the storage layer 5) and between two adjacent storage dies 51 in the storage layer 5. Thus, the bonding layer 3 serves as a lateral interconnect within the storage layer 5. The TSVs 4 vertically penetrate the storage layer 5 and are electrically connected to the logic layer 2 and the bonding layer 3. Thus, the TSVs 4 serve as a vertical interconnect within the storage layer 5.

[0041] (Logical Layer 2)

[0042] Logic layer 2 is the control core and power conversion center of storage device S. Logic layer 2 mainly includes a signal receiving unit 21, a control signal and synchronization clock generation unit 22, a centralized power management subsystem 23, and a power distribution network 24. These sub-components are electrically connected through the wiring structure within logic layer 2, working together to complete signal processing, voltage conversion, and global scheduling functions. This will be explained in detail later.

[0043] The signal receiving unit 21 is configured to receive access requests from external device 1, external data, and feedback signals from storage layer 5, and transmit the access requests to control signal and synchronization clock generation unit 22. Furthermore, for external data (e.g., AI model weights), the signal receiving unit 21 generates and feeds back a splitting rule for external data (including the number of target independent subarrays, data block size, transmission protocol format, etc.) based on the access requests parsed by the control signal and synchronization clock generation unit 22. This splits the originally serial external data into multiple subarray-specific data blocks (the number of splits is adapted to the number of independent subarrays 5111 of the storage die 51, for example, 8 or 16 channels). Then, the signal receiving unit 21 performs format conversion on each subarray-specific data block to generate parallel data signals (also known as core data) adapted to the transmission requirements of the parallel data channel 31 of the bonding layer 3.

[0044] The control signal and synchronization clock generation unit 22 is configured to parse the access request to generate control signals containing the target memory die identifier, independent subarray address and parallel scheduling instructions, and generate synchronization clock signals for calibrating the parallel timing of the multi-subarray.

[0045] The centralized power management subsystem 23 includes a boost module 231, a voltage regulator module 232, and a global voltage detection unit 233. The boost module 231 is used to boost the aforementioned base voltage from the outside to a preset high voltage (e.g., 10V). The voltage regulator module 232 is used to regulate the aforementioned preset high voltage to a first preset adaptation voltage (e.g., 7V) and a second preset adaptation voltage (e.g., 3.3V).

[0046] The global voltage detection unit 233 is used to monitor the output stability of the first preset adaptation voltage and the second preset adaptation voltage in real time.

[0047] The power distribution network 24 includes a voltage shunting unit 241 and a feedback adjustment unit 242. The voltage shunting unit 241 is configured to receive the control signal to determine the target memory die to be powered, and to shun the preset adapted voltage to each target memory die according to a preset ratio. The feedback adjustment unit 242 is configured to adjust the shunting ratio according to the actual power supply voltage (or actual power supply voltage signal) fed back from the memory layer 5.

[0048] In terms of location and connectivity, logic layer 2 is located in the lower part of the memory device S, and it establishes signal and power links with external device 1 and packaging substrate 7 through intermediary layer 6. The signal output terminal of logic layer 2 is electrically connected to the parallel data channel 31 of bonding layer 3. The output terminal of centralized power management subsystem 23 is electrically connected to power distribution network 24. The voltage shunt unit 241 of power distribution network 24 is electrically connected to the voltage distribution channel 41 of through-silicon via 4. The output terminal of control signal and synchronization clock generation unit 22 is electrically connected to the signal synchronization channel 42 of through-silicon via 4.

[0049] From an input and output perspective, the inputs received by logic layer 2 include the base voltage (e.g., 2.5V) transmitted from the packaging substrate 7 via the interposer layer 6, access requests from external device 1 (including target address, read / write type, and priority) and external data (e.g., AI model weights), as well as the actual power supply voltage signal and storage status feedback signal from the storage layer 5. The outputs of logic layer 2 include a first preset adaptation voltage and a second preset adaptation voltage generated by the centralized power management subsystem 23, control signals and synchronization clock signals generated by the control signal and synchronization clock generation unit 22, and voltage regulation commands generated by the feedback regulation unit 242.

[0050] (Bonding layer 3)

[0051] The bonding layer 3 is configured to function as a high-speed data interconnect component between the logic layer 2 and the memory layer 5, and between adjacent memory dies 51 in the memory layer 5, for example, using CBA (CMOS Direct Bonding to Array) technology. That is, the bonding layer 3 includes a bottom bonding layer disposed between the upper surface of the logic layer 2 and the lower surface of the memory layer 5, and an interlayer bonding layer disposed between adjacent memory dies 51 in the memory layer 5.

[0052] Furthermore, the bonding layer 3 includes an array of parallel data channels 31. In some embodiments, the parallel data channels 31 employ a copper-copper (Cu-Cu) direct interconnect structure with a small spacing between channels (e.g., 400 nm). Each parallel data channel 31 is an independent differential signal transmission link, containing a positive signal terminal and a negative signal terminal. Depending on the location of the bonding layer 3, the parallel data channels 31 can also be divided into bottom-layer parallel data channels and inter-layer parallel data channels. The bottom-layer parallel data channels are located in the bottom bonding layer between the upper surface of the logic layer 2 and the lower surface of the bottommost memory die 51 of the memory layer 5. The number of channels is, for example, 16 to 32. The transmission rate of a single channel is, for example, 20 Gbps to 25 Gbps. Furthermore, each channel is electrically connected to the signal output interface of logic layer 2 in a one-to-one correspondence, and forms an ohmic contact with the edge interface built into the local supporting circuit 512 of the bottom-layer memory die 51. This is used to synchronously transmit the aforementioned parallel data signals (sometimes referred to as core data) output from logic layer 2 to the corresponding signal receiving node of the bottom-layer memory die 51 according to the word array address allocation rules. On the other hand, inter-layer parallel data channels are deployed in the inter-layer bonding layer between adjacent memory dies 51 of memory layer 5, and the number of channels is consistent with that of the bottom-layer parallel data channels. The two ends of this inter-layer parallel data channel are electrically connected to the edge interface of the local supporting circuit 512 of the adjacent memory die 51, respectively. Furthermore, each interlayer parallel data channel is linked with the signal synchronization channel 42 of the through-silicon via 4 that vertically penetrates the storage layer 5, thereby receiving the timing synchronization signal transmitted by the through-silicon via 4 to ensure the timing alignment of data transmission between adjacent storage dies 51, and realizing the horizontal parallel forwarding of parallel data signals between adjacent storage dies 51 within the storage layer 5 (i.e., parallel data transmission from the lower storage die to the adjacent upper storage die).

[0053] (Through Silicon Via 4)

[0054] Through-silicon vias 4 are interconnect components that vertically penetrate the memory layer 5. Their number can be set according to the number of stacked layers of the memory layer 5 and the parallel transmission requirements (e.g., 4 sets of voltage distribution channels and 8 sets of signal synchronization channels). Each through-silicon via 4 includes a voltage distribution channel 41 and a signal synchronization channel 42.

[0055] In terms of location, the through-silicon via 4 vertically penetrates all the memory dies 51 of the memory layer 5. Its lower end is electrically connected to the logic layer 2, and its upper end extends to the topmost memory die 51 of the memory layer 5. It also interconnects with the corresponding functional interfaces of each layer of memory dies 51, thereby adapting to the vertical interconnection requirements of the 3D stacking architecture.

[0056] In terms of connectivity, one end of the voltage distribution channel 41 of the through-silicon via 4 is electrically connected to the voltage shunt unit 241 of the power distribution network 24 of the logic layer 2, and the other end is connected to the voltage input interface 514 of each layer of memory die 51. One end of the signal synchronization channel 42 is electrically connected to the control signal and synchronization clock generation unit 22 of the logic layer 2, and the other end is electrically connected to the sub-array level parallelism control circuit 513 of each layer of memory die 51.

[0057] The voltage distribution channel 41 is configured to receive a first preset adaptation voltage and a second preset adaptation voltage, as well as a voltage shunting command, from the power distribution network 24 of logic layer 2, which are converted by the centralized power management subsystem 23. The voltage shunting command includes a target memory die identifier, an adaptation voltage type, and output voltage amplitude fine-tuning parameters. Furthermore, the voltage distribution channel 41 is configured to output the first preset adaptation voltage, the second preset adaptation voltage, and the voltage shunting command to the voltage input interface 514 of each layer of memory die 51 in memory layer 5, so that the voltage input interface 514 distributes the first preset adaptation voltage and the second preset adaptation voltage to the read / write drive circuit 5121 and the subarray-level parallelism control circuit 513 in the local supporting circuit 512 of the target memory die according to the received voltage shunting command.

[0058] On the other hand, in some embodiments, voltage acquisition contacts are provided on the inner wall of the voltage distribution channel 41. When the voltage distribution channel 41 outputs the aforementioned preset adaptation voltages to each layer of memory dies 51, the voltage acquisition contacts monitor in real time the actual received voltage (i.e., actual power supply voltage) of the voltage input port 514 of each memory die 51. After acquiring the actual power supply voltage signal, the actual power supply voltage signal is sent to the signal feedback unit 515 electrically connected to it. After receiving the actual power supply voltage signal, the signal feedback unit 515 transmits the actual power supply voltage signal and the storage status signal of the memory die 51 to the global voltage detection unit 233 of the centralized power management subsystem 23 of the logic layer 2 via the signal synchronization channel 42 of the through-silicon via 4. After receiving the actual power supply voltage signal, the global voltage monitoring unit 233 determines whether the difference between the actual power supply voltage signal and the preset adaptation voltage is greater than a preset reference. If it is determined to be greater than the preset reference, the global voltage monitoring unit 233 notifies the feedback adjustment unit 242 of the power distribution network 24. In this case, the feedback regulation unit 242 generates and sends a voltage regulation command to adjust the shunt ratio.

[0059] The signal synchronization channel 42 is configured to receive control signals from logic layer 2 and control signals and synchronization clock signals from synchronization clock generation unit 22, and transmit these control signals and synchronization clock signals to the subarray-level parallelism control circuit 513 of each memory die 51. Furthermore, the signal synchronization channel 42 is further configured to receive voltage adjustment commands from feedback adjustment unit 242 of power distribution network 24 of logic layer 2, and transmit these voltage adjustment commands to the voltage input interface 514 of each layer of memory die 51, so that the voltage input interface 514 can be linked with the voltage distribution channel 41 for fine-tuning. Specifically, the signal synchronization channel 42 includes a control sub-channel, a clock sub-channel, and a feedback sub-channel. The control sub-channel is configured to receive and transmit control signals. The clock sub-channel is configured to receive and transmit synchronization clock signals. The feedback sub-channel is configured to receive and transmit voltage adjustment commands. Additionally, in some embodiments, if there is a requirement for direct cross-layer transmission of core data (i.e., parallel data signals), the signal synchronization channel 42 also includes a data direct transmission sub-channel.

[0060] (Storage layer 5)

[0061] Storage layer 5 functions as the data storage core of storage device S, comprising vertically stacked multi-layer storage dies 51.

[0062] The storage die 51 can be selected according to different storage scenario requirements. In some embodiments, the storage die 51 is, for example, a DRAM die, while in other embodiments, the storage die 51 is, for example, a flash memory die (such as a NAND Flash Die). In particular, in this disclosure, each layer of storage die 51 is not configured with die-level power management components. Instead, a subarray-level parallelism control circuit 513 is provided in the space created by omitting the configuration of die-level power management components.

[0063] Specifically, each layer of memory die 51 includes a memory cell array 511, a local supporting circuit 512, the aforementioned subarray-level parallelism control circuit 513, a voltage input interface 514, and a signal feedback unit 515.

[0064] The storage cell array 511 is divided into multiple (e.g., 8) independent subarrays 5111, each of which is an independent data storage unit that supports parallel read and write operations.

[0065] The local supporting circuit 512 includes a read / write drive circuit 5121, which is configured to drive data read / write under the first preset adaptation voltage. Additionally, the local supporting circuit 512 also includes a write buffer module 5122. The write buffer module 5122 is configured to temporarily store core data transferred to its corresponding memory die 51.

[0066] The subarray-level parallelism control circuit 513 includes a subarray dynamic scheduler 5131, an independent channel controller 5132, and a data prefetch buffer 5133.

[0067] The subarray dynamic scheduler 5131 is configured to receive control signals from logic layer 2 and monitor the load status of each independent subarray 5111. Furthermore, the subarray dynamic scheduler 5131 is configured to allocate subarray access tasks corresponding to the received control signals based on the target independent subarray identifier, read / write instructions, and load balancing principles, thereby enabling the independent channel controller 5132 and the memory cell array 511 to drive the target independent subarrays to perform data read / write operations.

[0068] The independent channel controller 5132 is configured to configure a data transmission channel for each independent subarray 5111 to enable parallel data transmission of multiple independent subarrays 5111.

[0069] The data prefetch buffer 5133 is configured to read and temporarily store the target read data associated with the access request from the target independent subarray when the access request is a data read request.

[0070] The voltage input interface 514 is configured to receive a first preset adaptation voltage and a second preset adaptation voltage transmitted through the press-distribution channel 41 of the through-silicon via 4, and to distribute the first preset adaptation voltage and the second preset adaptation voltage to the read / write drive circuit 5121 of the local supporting circuit 512 and the sub-array level parallelism control circuit 513. Furthermore, the voltage input interface 514 is also configured to receive voltage adjustment commands generated by the feedback adjustment unit 242, thereby coordinating with the voltage distribution channel 41 to perform voltage fine-tuning.

[0071] The signal feedback unit 515 is configured to receive the actual power supply voltage signal collected by the voltage distribution channel 41 and the working status signal of the memory die 51 to which it belongs (such as the data read / write completion status signal and the subarray load status signal), and feed these signals back to the logic layer 2 (control signal and synchronous clock generation unit 22 and feedback adjustment unit 24).

[0072] (Technical effect)

[0073] According to the storage device S described in this embodiment, by extracting the die-level power management components of each layer of storage dies and integrating a centralized power management subsystem at the logic layer, and by using the internal space freed up to add a sub-array level parallelism control circuit, combined with the collaborative interconnection mechanism of the bonding layer and through-silicon vias (TSVs), a multi-dimensional performance leap in power supply stability, parallel scheduling accuracy and data transmission bandwidth can be achieved, which can better meet the data transmission needs in AI inference scenarios.

[0074] Regarding power supply performance, in existing high-bandwidth storage architectures, each storage die is independently configured with power management components, resulting in poor power supply voltage consistency, large cross-layer power supply losses, high redundancy design costs, and the distributed power supply control is difficult to adapt to the stringent voltage stability requirements of multi-die parallel transmission. According to the storage device S described in this embodiment, by centralizing the power management function at the logic layer, the boost module and voltage regulator module of the resulting centralized power management subsystem generate a unified and stable first preset adaptation voltage and a second preset adaptation voltage. These are then precisely distributed to each layer of storage dies via the voltage shunting unit of the power distribution network, and a closed-loop control is formed with the global voltage monitoring unit and feedback adjustment unit, thus avoiding voltage deviation problems caused by distributed power supply. Simultaneously, the centralized power supply architecture significantly reduces the space occupied and power consumption of the internal power components of the dies, reduces cross-layer power supply transmission losses, and provides stable and reliable power supply support for high-parallel data transmission of multiple dies and multiple subarrays, thereby ensuring uninterrupted power supply and no timing deviations during large-scale parallel read / write operations.

[0075] Regarding parallel scheduling and transmission efficiency, the storage device S described in this embodiment utilizes the internal space freed up by removing the die-level power management components to specifically add subarray-level parallelism control circuits, thereby enabling the construction of a parallel management and control system. By monitoring the load status of each independent subarray in real time through a subarray dynamic scheduler, and combining control commands issued from the logic layer with load balancing principles, subarray access tasks can be allocated more accurately. Furthermore, by configuring a dedicated data transmission channel for each independent subarray through an independent channel controller, channel conflicts and resource contention during parallel access by multiple subarrays can be avoided. Additionally, by setting a data prefetch buffer to pre-store target data for read operations, data access latency can be significantly reduced. Thus, parallel read and write operations of multiple independent subarrays on each layer of storage die can be achieved. Based on this, with timing calibration of the high-speed parallel data channel and TSV signal synchronization channel of the bonding layer array, strict timing alignment of lateral forwarding between adjacent dies and vertical transmission across layers can be ensured, maximizing the parallel access potential of the 3D stacked architecture and significantly improving the parallelism and response efficiency of data transmission.

[0076] In terms of bandwidth performance and scenario adaptability, existing high-bandwidth flash (HBF) architectures are limited by the parallelism constraints caused by distributed power supply, insufficient scheduling accuracy, and interconnection link efficiency bottlenecks. Their data transmission bandwidth is typically only 100GB / s to 200GB / s, which is insufficient to meet the massive data access demands of AI inference scenarios. During AI inference, the weight parameters of large models (typically ranging from tens to hundreds of GB), feature map data, and intermediate computation results need to interact frequently with computing cores (such as GPUs and TPUs) through high-bandwidth, low-latency storage links. The bandwidth bottleneck of existing storage architectures causes the data supply rate to lag behind the processing demands of the computing cores, resulting in efficiency losses due to "computing core idleness," which seriously affects the throughput and response speed of inference tasks. According to the storage device described in this embodiment, through multi-subarray parallel scheduling supported by centralized power supply, combined with the coordinated transmission of multiple high-speed parallel data channels, the peak data transmission bandwidth of storage device S is significantly improved compared to existing bandwidths. This can better match the high parallelism and low-latency access demands for massive data in AI inference scenarios, ensuring efficient coordination between data transmission and computation.

[0077] (An example of a data write operation)

[0078] Next, refer to Figure 3 The process of performing a data write operation on a computer system O based on the storage device S described in the above embodiments will be described. In this example, it is assumed that 16 layers of storage dies 51 are vertically stacked on the storage layer 5, and the storage cell array 511 of each layer of storage die 51 is fixedly divided into 8 independent subarrays 5111.

[0079] In this example, external device 1 is a GPU, which needs to write feature map data of the AI ​​large model to the 3rd, 7th and 12th layers of the 16-layer storage die of storage device S. The specific access request is "WRITEADDR=0x2000-0x27FF,DIE=3 / 7 / 12,SUBARRAY=1-4 / 2-5 / 0-3,DATA=FEATURE_MAP_001-003", which means writing 256B of data to subarrays 1-4 of the 3rd layer die, subarrays 2-5 of the 7th layer die, and subarrays 0-3 of the 12th layer die, for a total of 768B of serial data. All target subarrays perform the write operation in parallel.

[0080] After the GPU generates the write access request, it transmits the request instruction, 768B of serial data, and a 1GHz timing synchronization clock to the logic layer 2 of the memory device S through the micron-level microbump array and redistribution layer (RDL) of the intermediary layer 6. The signal receiving unit 21 of the logic layer 2 first receives this information and forwards the access request to the control signal and synchronization clock generation unit 22. This unit parses the target die identifier (3 / 7 / 12), subarray address (1-4 / 2-5 / 0-3), and data length in the request, and then generates the corresponding control signals (including the subarray enable instructions "DIE3_SUB1-4_EN, DIE7_SUB2-5_EN, DIE12_SUB0-3_EN", and the parallel scheduling instruction "PARALLEL_WRITE_MODE=8CH"). At the same time, it reuses the received 1GHz synchronization clock signal to ensure full-link timing alignment. For 768B serial data, the signal receiving unit 21 divides it into 8 dedicated data blocks for each subarray (96B each) according to the splitting rules of the control signal feedback (to adapt to the parallel requirements of 8 independent subarrays of each die layer). After format conversion, it generates parallel data signals adapted to the parallel data channel 31 of the bonding layer 3, with the signal rate of each channel matching the 20Gbps transmission specification of the channel.

[0081] Meanwhile, the centralized power management subsystem 23 of logic layer 2 receives the 2.5V base voltage transmitted by the intermediate layer 6, boosts it to a preset high voltage of 10V through the boost module 231, and then regulates it to a first preset adaptation voltage of 7V (for the read / write drive circuit 5121) and a second preset adaptation voltage of 3.3V (for the subarray level parallelism control circuit 513) through the voltage regulator module 232. The global voltage detection unit 233 monitors the two types of voltage in real time to ensure that the fluctuation does not exceed ±0.01V. The voltage shunting unit 241 of the power distribution network 24 receives the target die information in the control signal and shunts the two types of preset adapter voltages according to the ratio of "DIE3:DIE7:DIE12=1:1:1". The voltages are vertically transmitted to the voltage input interface 514 of the storage die 51 on the 3rd, 7th and 12th layers through the four voltage distribution channels 41 of the through silicon via 4. At the same time, a voltage shunting command containing "target die=3 / 7 / 12, voltage type=7V / 3.3V, fine-tuning parameter=+0.005V" is issued.

[0082] Control signals and synchronization clock signals are transmitted through eight signal synchronization channels 42 of the through-silicon via 4. Among them, three control sub-channels carry sub-array enable and parallel scheduling instructions, two clock sub-channels carry 1GHz synchronization clock signals, which vertically penetrate 16 layers of memory die and are precisely connected to the sub-array level parallelism control circuit 513 of the 3rd, 7th and 12th layers of memory die 51; the remaining three channels (including two feedback sub-channels and one data direct transmission sub-channel) are in standby mode. The bottom parallel data channel 31 (16 channels) of the bonding layer 3 receives 8 parallel data signals output from the logic layer 2 and transmits them laterally to the local supporting circuit 512 of the bottom die 1. The die 1 acts as a relay and forwards the signals to the 3rd, 7th and 12th dies respectively through the parallel data channel 31 (16 channels) of the interlayer bonding layer. The 3rd die receives the parallel data signals of channels 1-4, the 7th die receives the signals of channels 2-5, and the 12th die receives the signals of channels 0-3. During the forwarding process, the interlayer parallel data channel receives the timing synchronization signal derived from the signal synchronization channel 42 to ensure that the signal reception phase of each layer is consistent.

[0083] After receiving the parallel data signal, the local supporting circuit 512 of the third-layer storage die 51 temporarily stores it through the write buffer module 5122 and then transmits it to the sub-array level parallelism control circuit 513. The sub-array dynamic scheduler 5131 receives the control signal and the synchronization clock signal, monitors the load status of its eight independent sub-arrays 5111 in real time (sub-arrays 1-4 are idle, and 5-7 are lightly loaded), allocates write tasks based on the load balancing principle, and links the independent channel controller 5132 to configure dedicated data transmission channels for sub-arrays 1-4 respectively (channel 1 corresponds to sub-array 1, channel 2 corresponds to sub-array 2, channel 3 corresponds to sub-array 3, and channel 4 corresponds to sub-array 4). The voltage input interface 514 receives the 7V and 3.3V voltages transmitted by the voltage distribution channel 41 and distributes them to the read / write drive circuit 5121 and the subarray level parallelism control circuit 513 according to the current distribution command. Under the drive of the 7V first preset adaptation voltage, the read / write drive circuit 5121 starts the write drive and writes the 96B parallel data signals into the address segments 0x2000-0x203F, 0x2040-0x207F, 0x2080-0x20BF, and 0x20C0-0x20FF of subarrays 1-4 respectively.

[0084] The 7th and 12th layer storage die 51 repeats the above die process: the 7th layer subarray dynamic scheduler 5131 activates subarray 2-5, configures channel 2-5 through independent channel controller 5132, and writes data into the address ranges 0x2100-0x213F, 0x2140-0x217F, 0x2180-0x21BF, and 0x21C0-0x21FF; the 12th layer activates subarray 0-3, configures channel 0-3, and writes data into the address ranges 0x2200-0x223F, 0x2240-0x227F, 0x2280-0x22BF, and 0x22C0-0x22FF. Throughout the writing process, the signal feedback unit 515 of each die layer, in conjunction with the voltage input interface 514, acquires the actual power supply voltage signal (both stable at 7.005V and 3.305V), and simultaneously acquires the "subarray write complete" status signal. After integration, these signals are transmitted back to logic layer 2 via two sets of feedback sub-channels of the signal synchronization channel 42. The global voltage detection unit 233 confirms that the actual voltage meets the standard, and the feedback adjustment unit 242 does not need to generate adjustment instructions. After receiving the write completion feedback from all target subarrays, the control signal and synchronization clock generation unit 22 returns a "WRITE_SUCCESS" confirmation signal to the GPU, completing the parallel write operation of the entire multi-die, multi-subarray process.

[0085] (An example of a data read operation)

[0086] Next, refer to Figure 4 The process of performing a data reading operation based on a computer system O including the storage device S described in the above embodiments will be described. In this example, it is also assumed that 16 layers of storage dies 51 are vertically stacked on the storage layer 5, and the storage cell array 511 of each layer of storage die 51 is fixedly divided into 8 independent subarrays 5111.

[0087] In this example, external device 1 is still the GPU. During AI inference, it needs to call the three sets of feature map data previously written. The specific access request is "READADDR=0x2000-0x27FF,DIE=3 / 7 / 12,SUBARRAY=1-4 / 2-5 / 0-3,LEN=256B,MODE=PREFETCH". The target is the storage die 51 of the 3rd, 7th and 12th layers of storage layer 5. It needs to read the corresponding data from the four independent subarrays 5111 of each layer of die. All target subarrays perform the read operation in parallel, and the data prefetch function is enabled synchronously.

[0088] After the GPU generates the read access request, it transmits the request instruction and a 1.2GHz timing synchronization clock (adapted to the low latency requirements of DRAM dies) to the logic layer 2 of the memory device S through the redistribution layer and through-silicon via (TSV) structure of the interposer layer 6. After receiving the request, the signal receiving unit 21 of the logic layer 2 forwards the access request to the control signal and synchronization clock generation unit 22. After parsing the address range, target die and subarray information in the request, the unit generates the corresponding control signals (including read enable instructions "DIE3_SUB1-4_RD_EN, DIE7_SUB2-5_RD_EN, DIE12_SUB0-3_RD_EN" and data prefetch instruction "PREFETCH_LEN=128B"), and calibrates the 1.2GHz synchronization clock signal to adapt to the timing reference of the memory device. Control signals and synchronization clock signals are transmitted through eight signal synchronization channels 42 of the through-silicon via 4. The control sub-channel carries read enable and prefetch instructions, and the clock sub-channel carries a calibrated 1.2GHz clock signal, which is accurately delivered to the sub-array level parallelism control circuit 513 of the 3rd, 7th and 12th layer memory dies 51.

[0089] The voltage shunting unit 241 of the power distribution network 24, based on the target die information in the control signal, continues the voltage distribution ratio during the write operation and transmits a 7V first preset adaptation voltage and a 3.3V second preset adaptation voltage to the voltage input interfaces 514 of the 3rd, 7th, and 12th layer dies through the voltage distribution channel 41. The voltage input interfaces 514 distribute the voltage to the read / write drive circuit 5121 and the subarray-level parallelism control circuit 513 as needed, providing stable power for the read operation. After receiving the control signal and the synchronization clock signal, the subarray-level parallelism control circuit 513 of each layer die monitors the load status of its 8 independent subarrays in real time (the target subarrays are all lightly loaded). After confirming that there are no access conflicts, it allocates the read task, and the independent channel controller 5132 activates the dedicated data transmission channel of the corresponding subarray (consistent with the channel configuration during the write operation). According to the instruction "PREFETCH_LEN=128B", the data prefetch buffer 5133 reads data from the target subarray two clock cycles in advance and temporarily stores it. Subarray 1-3 of layer 3 reads 128B of data in the address range of 0x2000-0x207F, subarray 2-4 of layer 4 reads the address range of 0x2100-0x217F, and subarray 0-2 of layer 6 reads the address range of 0x2200-0x227F.

[0090] Supported by a second preset adaptation voltage of 3.3V, the subarray-level parallelism control circuit 513 converts the 256B data temporarily stored in the data prefetch buffer 5133 into parallel data signals, which are then transmitted to the local supporting circuit 512 through an independent data transmission channel. After being driven by the read / write driver circuit 5121, the signals are connected to the interlayer parallel data channel 31 of the bonding layer 3. The parallel data signals of the 3rd, 7th, and 12th layer dies are laterally forwarded to the bottommost die 1 through the interlayer bonding layer, during which the timing synchronization signal of the signal synchronization channel 42 is received to ensure the timing alignment of the 8 parallel signals. Finally, all read data converges to the local supporting circuit 512 of die 1 and is laterally transmitted to the signal receiving unit 21 of the logic layer 2 through the bottom parallel data channel 31.

[0091] Signal receiving unit 21 integrates 8 parallel data signals into a 768B serial data format, reassembles them into 3 groups of 256B feature map data blocks according to the original requested address order, and transmits them to the GPU through the redistribution layer and microbump array of intermediate layer 6 to provide data support for AI inference. During the reading process, the signal feedback unit 515 of each die continuously collects the subarray reading completion status, load status, and actual power supply voltage signals (7.005V, 3.305V), integrates them, and sends them back to logic layer 2 through the feedback subchannel of signal synchronization channel 42. Control signal and synchronization clock generation unit 22 confirms that no data is missing based on the reading completion status, and global voltage detection unit 233 confirms that the power supply is stable. The entire parallel reading operation of multiple dies and multiple subarrays is completed.

[0092] It should be understood that this disclosure is not limited to the precise structures and specific implementations described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A storage device (S) comprising a logic layer (2) and a storage layer (5). The logic layer (2) and the memory layer (5) are communicatively connected through a bonding layer (3) and through-silicon vias (4). The storage layer (5) includes vertically stacked multilayer storage dies (51), each of the storage dies (51) is provided with a storage cell array (511) and local supporting circuits (512), and the storage cell array is divided into multiple independent sub-arrays (5111). Its features are, The logic layer (2) is configured as follows: It can provide inputs of base voltage from the outside, access requests from external devices (1) and external data, as well as read parallel data signals from the storage layer (5); and It can output the preset adaptation voltage of each of the memory dies (51) adapted to the operation of the memory layer (5), as well as the control signal and write parallel data signal formed after the access request and the external data are processed by the logic layer (2). Each of the aforementioned storage dies (51) is not equipped with a die-level power management component. The through-silicon via (4) includes a voltage distribution channel (41) and a signal synchronization channel (42). The bonding layer (3) includes a parallel data channel (31) capable of transmitting the read parallel data signal and the write parallel data signal. The logic layer (2) includes: A centralized power management subsystem (23), the centralized power management subsystem (23) being configured to convert the base voltage to the preset adaptive voltage; and A power distribution network (24) is configured to be electrically connected to the voltage distribution channel (41) to distribute the preset adaptation voltage to each of the memory dies (51). Each of the aforementioned memory dies (51) is configured with: A subarray-level parallelism control circuit (513) is electrically connected to the plurality of independent subarrays (5111) and the signal synchronization channel (42) to receive the control signal and perform parallel access scheduling on the plurality of independent subarrays (5111) based on the control signal to adapt to the write transmission of the write parallel data signal and the read transmission of the read parallel data signal; and A voltage input interface (514) is electrically connected to the voltage distribution channel (41) to receive the preset adaptive voltage. Furthermore, in each of the aforementioned storage dies (51), the local supporting circuit (512) is electrically connected to the parallel data channel (31) to receive the write parallel data signal or output the read parallel data signal.

2. The storage device (S) as claimed in claim 1, characterized in that, The centralized power management subsystem (23) includes a boost module (231) and a voltage regulator module (232). The boost module (231) is used to boost the base voltage to a preset high voltage, and the voltage regulator module (232) is used to regulate the preset high voltage to the preset adaptive voltage.

3. The storage device (S) as claimed in claim 2, characterized in that, The centralized power management subsystem (23) also includes a global voltage monitoring unit (233). The global voltage monitoring unit (233) is configured to be electrically connected to the voltage regulator module (232) to monitor the stability of the preset adaptive voltage output by the voltage regulator module (232). The global voltage monitoring unit (233) is configured to be electrically connected to the signal synchronization channel (42) to receive the actual power supply voltage signal fed back by each of the memory dies (51), and to send a voltage adjustment notification to the power distribution network (24) when the deviation between the actual power supply voltage and the preset adaptation voltage exceeds the preset reference.

4. The storage device (S) as claimed in claim 1, characterized in that, The subarray-level parallelism control circuit (513) includes: Subarray dynamic scheduler (5131) is configured to receive the control signal from the logic layer (2) through the signal synchronization channel (42), monitor the load status of the independent subarray (5111), and generate a subarray read / write scheduling instruction corresponding to the control signal based on the monitored load status, so as to drive each target independent subarray (5111) to adapt to the write transmission of the write parallel data signal and the read transmission of the read parallel data signal; An independent channel controller (5132) is configured to configure data transmission channels for each of the independent subarrays (5111) to perform write transmission of the write parallel data signal or read transmission of the read parallel data signal, respectively; and A data prefetch buffer (5133) is configured to read and temporarily store target read data from the target independent subarray pointed to by the control signal when the data access type corresponding to the control signal is read. The target read data is processed by the independent channel controller (5132) and driven by the local supporting circuit (512) to form the read parallel data signal.

5. The storage device (S) as claimed in claim 3, characterized in that, The power distribution network (24) includes a voltage shunt unit (241). The voltage shunt unit (241) is configured to receive the control signal, determine the target memory die to be powered based on the control signal, and shunt the preset adaptation voltage to the target memory die via the voltage distribution channel (41) according to the preset shunt ratio.

6. The storage device (S) as claimed in claim 5, characterized in that, The power distribution network (24) also includes a feedback regulation unit (242). The feedback regulation unit (242) is configured to be electrically connected to the global voltage monitoring unit (233) to receive the voltage regulation notification, and The feedback adjustment unit (242) is further configured to be electrically connected to the voltage shunt unit (241) to generate a voltage adjustment command based on the voltage adjustment notification. The voltage adjustment command is used to adjust the preset shunt ratio of the voltage shunt unit (241) so that the deviation between the actual power supply voltage of each target memory die and the preset adaptation voltage conforms to the preset reference.

7. The storage device (S) as claimed in claim 1, characterized in that, The preset adaptation voltage includes at least a first preset adaptation voltage and a second preset adaptation voltage. The first preset adaptation voltage is used to power the read / write drive circuit of each of the memory dies (51), and the second preset adaptation voltage is used to power the subarray level parallelism control circuit (513) of each of the memory dies (51).

8. The storage device (S) as claimed in any one of claims 1 to 7, characterized in that, The storage die (51) is a NAND flash memory die or a DRAM die.

9. A computer system (O) comprising a package substrate (7), an interposer (6), an external device (1), and a storage device, wherein the interposer (6) is integrated on the package substrate (7), the external device (1) and the storage device are mounted on the interposer (6) and electrically connected to the package substrate (7) through the interposer (6), characterized in that, The storage device is the storage device (S) according to any one of claims 1 to 8.

10. A storage die (51), characterized in that, The storage die (51) is used in the storage device (S) according to any one of claims 1 to 8.

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