Memory

Abstract

The embodiment of the invention provides a memory. The memory comprises at least one memory block; each memory block includes: a memory array; the storage array comprises a plurality of conductive wires and a plurality of storage units located among the conductive wires; the first dummy structure at least surrounds the storage array and is used for providing a fixed potential for testing; the first dummy structure comprises a plurality of first dummy conductive wires; the redundant structure is located between the storage array and the first dummy structure and used for repairing the damaged conductive wire; the redundant structure comprises a plurality of redundant conductive wires; wherein the ratio of the number of the redundant conductive wires to the sum of the number of the first dummy conductive wires and the number of the redundant conductive wires is greater than a preset value.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a memory. BACKGROUND

[0002] Memory, such as phase change memory, as a new emerging non-volatile memory device, has great advantages in read / write speed, read / write times, data retention time, cell area, multi-value implementation and many other aspects. However, with the use and development of phase change memory, there is still room for improvement. SUMMARY

[0003] Embodiments of the present disclosure provide a memory, comprising: at least one memory block; each of the memory blocks comprises:

[0004] a memory array; the memory array comprises a plurality of conductive lines and a plurality of memory cells located between the conductive lines;

[0005] a first dummy structure, at least surrounding the memory array, for providing a fixed potential for testing; the first dummy structure comprises a plurality of first dummy conductive lines;

[0006] a redundancy structure, located between the memory array and the first dummy structure, for repairing damaged conductive lines; the redundancy structure comprises a plurality of redundant conductive lines;

[0007] wherein the ratio of the number of redundant conductive lines to the sum of the number of first dummy conductive lines and the number of redundant conductive lines is greater than a preset value.

[0008] In some embodiments, the preset value is greater than 0.6.

[0009] In some embodiments, the memory further comprises:

[0010] a second dummy structure, at least surrounding the first dummy structure, for providing protection for the memory array; the second dummy structure comprises a plurality of second dummy conductive lines; the number of second dummy conductive lines is greater than the number of first dummy conductive lines.

[0011] In some embodiments, the conductive lines comprise a plurality of first conductive lines extending in a first direction and a plurality of second conductive lines extending in a second direction; the first direction and the second direction intersect; the memory cells are located between the first conductive lines and the second conductive lines;

[0012] The first dummy conductive lines include a plurality of first sub dummy conductive lines extending along a first direction, and a plurality of second sub dummy conductive lines extending along a second direction; the first sub dummy conductive lines are located on opposite first and second sides of the memory array along the second direction, and the second sub dummy conductive lines are located on opposite third and fourth sides of the memory array along the first direction.

[0013] The second dummy conductive lines include a plurality of third sub dummy conductive lines extending along a first direction, and a plurality of fourth sub dummy conductive lines extending along a second direction; the third sub dummy conductive lines are located on the first and second sides of the memory array, and the fourth sub dummy conductive lines are located on the third and fourth sides of the memory array.

[0014] The redundant conductive lines include a plurality of first redundant conductive lines extending along a first direction, and a plurality of second redundant conductive lines extending along a second direction; the first redundant conductive lines are located on the first and / or second sides of the memory array, and the second redundant conductive lines are located on the third and / or fourth sides of the memory array.

[0015] In some embodiments, the number of the first sub dummy conductive lines is equal to the number of the second sub dummy conductive lines, and the number of the third sub dummy conductive lines is equal to the number of the fourth sub dummy conductive lines.

[0016] In some embodiments, the leakage of the second conductive lines has a greater impact on the performance of the memory than the leakage of the first conductive lines, and the number of the second redundant conductive lines is greater than the number of the first redundant conductive lines.

[0017] In some embodiments, the number of the first redundant conductive lines and the number of the second redundant conductive lines are both even.

[0018] In some embodiments, the memory further includes a peripheral circuit.

[0019] The peripheral circuit and the memory array are sequentially stacked along a third direction; the third direction is perpendicular to the first direction and the second direction.

[0020] The first dummy conductive lines are connected to the peripheral circuit through first contact structures; the second dummy conductive lines are floating relative to the peripheral circuit; the redundant conductive lines are connected to the peripheral circuit through second contact structures; and the conductive lines are connected to the peripheral circuit through third contact structures.

[0021] In some embodiments, the memory array includes a first bit line layer, a first memory cell layer, a word line layer, a second memory cell layer, and a second bit line layer, which are sequentially stacked along the third direction.

[0022] The first bit line layer and the second bit line layer each include a plurality of second conductive lines, the first memory cell layer and the second memory cell layer each include a plurality of memory cells, and the word line layer includes a plurality of first conductive lines.

[0023] The word line layer includes a plurality of first conductive lines, and there is a blank area in the plurality of first conductive lines.

[0024] In some embodiments, the first dummy conductive lines further include a plurality of fifth sub-dummy conductive lines extending in the first direction, and the fifth sub-dummy conductive lines are arranged on both sides of the blank area in the second direction.

[0025] The second dummy conductive lines further include a plurality of sixth sub-dummy conductive lines extending in the first direction, and the sixth sub-dummy conductive lines are arranged between the blank area and the fifth sub-dummy conductive lines.

[0026] In some embodiments, the number of the sixth sub-dummy conductive lines is less than the number of the third sub-dummy conductive lines.

[0027] In some embodiments, the memory includes a plurality of memory blocks, and the plurality of memory blocks are arranged in an array in the direction in which the conductive lines extend.

[0028] The memory provided by the embodiments of the present disclosure includes at least one memory block, each of the memory blocks includes a memory array, the memory array includes a plurality of conductive lines and a plurality of memory cells located between the conductive lines, a first dummy structure is arranged at least around the memory array to provide a fixed potential for testing, the first dummy structure includes a plurality of first dummy conductive lines, a redundancy structure is located between the memory array and the first dummy structure to repair damaged conductive lines, and the redundancy structure includes a plurality of redundancy conductive lines. The ratio of the number of the redundancy conductive lines to the sum of the number of the first dummy conductive lines and the number of the redundancy conductive lines is greater than a preset value. In this way, in the embodiments of the present disclosure, by setting the ratio of the number of the redundancy conductive lines to the sum of the number of the first dummy conductive lines and the number of the redundancy conductive lines to be greater than a preset value, the number of the redundancy conductive lines in the memory block can have a relatively large proportion, that is, a relatively large number of redundancy conductive lines can be included. A relatively large number of redundancy conductive lines helps to improve the repair capability and reduce the risk of failure of the memory block due to the fact that the memory block cannot provide sufficient repair capability because the number of the redundancy conductive lines is small. The increase in the number of the redundancy structure helps to improve the design window when the redundancy structure is designed, and the improvement in the repair capability is also conducive to repairing and improving the capacity of the memory.

[0029] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0031] Figure 1 A structural schematic diagram of a storage block structure provided by the embodiments of the present disclosure;

[0032] Figure 2 A structural schematic diagram of another storage block structure provided by the embodiments of the present disclosure;

[0033] Figure 3 A structural schematic diagram of still another storage block structure provided by the embodiments of the present disclosure;

[0034] Figure 4 A structural schematic diagram of still another storage block structure provided by the embodiments of the present disclosure;

[0035] Figure 5 A partial perspective view of the storage block structure provided by the embodiments of the present disclosure;

[0036] Figure 6 And Figure 7 A partial sectional view of the storage block structure provided by the embodiments of the present disclosure;

[0037] Figure 8 A partial top view of the storage block structure provided by the embodiments of the present disclosure.

[0038] Figure 9a And Figure 9b A component schematic diagram of the memory structure provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] Exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood, and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0040] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the disclosure. Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation including modifi cations and variants thereof. For example, the terms "including" and "comprising" should be given their broadest interpretative meanings, that is, "including", but not limited to.

[0041] In the drawings, the size of layers, regions, elements, and the like, can be exaggerated for clarity. Like reference numerals in different drawings denote like elements.

[0042] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure. The terminology used herein, such as "on," "over," "positioned on," etc., is used in the context of the figures. Unless otherwise specifically stated, such terminology indicates that a element or feature is present "above" or "on" another element or feature in the drawing figure, and does not necessarily require a direct physical "contact" relationship between elements or features. For example, an element or feature "over" or "on" another element or feature can be directly in contact with the other element or feature, or can have one or more intervening elements or features present therebetween.

[0043] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] A phase change memory structure generally includes a plurality of memory blocks, each of which in turn includes a memory array region that can further include a plurality of conductive lines extending in a first direction and a plurality of conductive lines extending in a second direction, both directions being parallel to the same plane and intersecting. However, as phase change memory is used and developed, there is a risk of damage to these conductive lines, and generally, to maintain the integrity of the performance of the memory array, repair operations need to be performed on damaged conductive lines.

[0046] However, due to the layout of the memory array region of the conventional technology, a large number of dummy structures are often designed around the conductive lines in the memory array region to protect the conductive lines from damage during the manufacturing process, which compresses the design space of the redundant structure to a small level.

[0047] Based on this, the following technical solutions of the embodiments of the disclosure are proposed:

[0048] The embodiments of the disclosure provide a memory, comprising:

[0049] at least one memory block; each memory block comprises:

[0050] a memory array; the memory array comprises a plurality of conductive lines and a plurality of memory cells located between the conductive lines;

[0051] a first dummy structure, at least surrounding the memory array, for providing a fixed potential for testing; the first dummy structure comprises a plurality of first dummy conductive lines;

[0052] a redundant structure located between the memory array and the first dummy structure, for repairing damaged conductive lines; the redundant structure comprises a plurality of redundant conductive lines;

[0053] wherein the ratio of the number of redundant conductive lines to the sum of the number of first dummy conductive lines and the number of redundant conductive lines is greater than a preset value.

[0054] Therefore, in the embodiments of the present disclosure, by setting the ratio of the number of redundant conductive lines to the sum of the number of first dummy conductive lines and the number of redundant conductive lines to be greater than a preset value, the number of redundant conductive lines in the storage block can have a relatively large proportion, that is, a relatively large number of redundant conductive lines can be contained, and a relatively large number of redundant conductive lines helps to improve the repair capability and reduce the risk of failure of the storage block due to the fact that the storage block cannot provide sufficient repair capability because of a small number of redundant conductive lines. The increase in the number of redundant structures helps to improve the design window when designing the redundant structure, and the improvement of the repair capability is also conducive to repairing and improving the memory capacity.

[0055] To make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure will be described in detail below in combination with the drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagrams will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the protection scope of the present disclosure.

[0056] Figure 1 A structural schematic diagram of a storage block structure provided by an embodiment of the present disclosure is shown in FIG. 1; Figure 2 A structural schematic diagram of another storage block structure provided by an embodiment of the present disclosure is shown in FIG. 2; Figure 3 A structural schematic diagram of still another storage block structure provided by an embodiment of the present disclosure is shown in FIG. 3; Figure 4 A structural schematic diagram of still another storage block structure provided by an embodiment of the present disclosure is shown in FIG. 4; Figure 5 A partial perspective view of a storage block structure provided by an embodiment of the present disclosure is shown in FIG. 5; Figure 6 A partial perspective view of a storage block structure provided by an embodiment of the present disclosure is shown in FIG. 6; Figure 7 A partial sectional view of a storage block structure provided by an embodiment of the present disclosure is shown in FIG. 7; Figure 8 A partial top view of a storage block structure provided by an embodiment of the present disclosure is shown in FIG. 8. Figure 9a A partial top view of a storage block structure provided by an embodiment of the present disclosure is shown in FIG. 9; Figure 9b A composition schematic diagram of a memory structure provided by an embodiment of the present disclosure is shown in FIG. 10.

[0057] The memory structure provided by the embodiments of the present disclosure will be further described in detail below in combination with the drawings.

[0058] As shown in FIG. 1, Figures 1 to 5 The memory includes at least one storage block 10; each storage block 10 includes:

[0059] a storage array A; the storage array A includes a plurality of conductive lines L and a plurality of storage cells C located between the conductive lines L;

[0060] a first dummy structure D1 arranged at least around the storage array A for providing a fixed potential for testing; the first dummy structure A includes a plurality of first dummy conductive lines D1L;

[0061] A redundant structure R is located between the storage array A and the first dummy structure D1, and is used to repair damaged conductive lines L; the redundant structure R includes several redundant conductive lines RL.

[0062] Among them, the ratio of the number of redundant conductive lines RL to the sum of the number of the first dummy conductive lines D11 and the number of redundant conductive lines RL is greater than a preset value.

[0063] In some embodiments, such as Figure 5 As shown, the conductive line L includes a plurality of first conductive lines L1 extending along a first direction and a plurality of second conductive lines L2 extending along a second direction; the first direction and the second direction intersect; the storage unit C is located between the first conductive lines L1 and the second conductive lines L2.

[0064] In some embodiments, the memory may include, but is not limited to, phase-change memory, and the memory cell C may be a phase-change memory cell, such as... Figure 5 As shown, when the memory cell C is a phase-change memory cell, it may include a bottom electrode (not shown), a gate layer (not shown), an intermediate electrode (not shown), a memory layer (not shown), and a top electrode (not shown) stacked along a third direction. Here, the third direction is perpendicular to both the first and second directions.

[0065] In some embodiments, the first conductive line L1 and the second conductive line L2 can be used as a bit line and a word line, respectively, and the phase-change memory cell is located at the intersection of the word line and the bit line. However, this is not a limitation; in other embodiments, the first conductive line L1 and the second conductive line L2 can also be used as a word line and a bit line, respectively, and the phase-change memory cell C is located at the intersection of the word line and the bit line. The specific choice can be made according to the actual situation, and no specific limitation is made here.

[0066] Optionally, in some embodiments, the materials of the first conductive line L1 and the second conductive line L2 may include, but are not limited to, at least one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides. In some specific embodiments, the materials of the first conductive line L1 and the second conductive line L2 may be the same or different, and no specific limitation is made here.

[0067] In some embodiments, the bottom electrode (not shown), the middle electrode (not shown), and the top electrode (not shown) may be made of the same or different materials. In some specific embodiments, each of the bottom electrode (not shown), the middle electrode (not shown), and the top electrode (not shown) may include carbon, such as at least one or a combination of amorphous carbon (aC), carbon nanotubes, etc.

[0068] In some embodiments, the material of the gating layer (not labeled in the figure) includes, but is not limited to, OTS (Ovonic Threshold Switch) material formation, for example, Zn x Te y , Ge x Te y , Nb x O y , or Si x As y Te z , etc.

[0069] In some embodiments, the material of the storage layer (not labeled in the figure) includes, but is not limited to, alloys of chalcogenides (chalcogenide glasses), such as GST (Ge-Sb-Te) alloys or indium-antimony-tellurium (In-Sb-Te, IST) materials, etc., or includes any other appropriate phase change material. In some specific embodiments, the material of the storage layer (not labeled in the figure) can be at least one of Ge2Sb2Te5, Ge1Sb4Te7, In2Sb2Te5, or In1Sb2Te4, etc., or a combination thereof.

[0070] It can be understood that the first dummy structure D1 can provide a fixed potential for the test operation process by being connected with a structure having a fixed potential, and the more the first dummy structure D1 is provided, the more it helps to meet the supply demand of the fixed potential for the test process. At the same time, the presence of the redundant structure R helps to repair and replace the damaged second conductive line L2, and the more the redundant structure R is provided, the more it helps to improve its repair and replacement ability for the damaged second conductive line L2. However, too many first dummy structures D1 will cause more area occupation, causing the setting space of other structures, such as but not limited to the redundant structure R and the storage array A, to be compressed, so the number of the first dummy conductive line D1L included in the first dummy structure D1 can be as small as possible (at least the number is 1, and a little more can provide an alternative) under the condition of ensuring the supply of the fixed potential, and the number of the redundant structure R should be as large as possible without affecting the setting of the storage array A. On this basis, reducing the number of the first dummy conductive line D1L can free up more space for setting the redundant structure R, for example, the number of the first dummy conductive line D1L can be increased to the number of the redundant conductive line RL, so that more number of the redundant conductive line RL can be set.

[0071] Continuing to refer to Figures 1 to 4 It can be seen that, in some embodiments, the memory further includes:

[0072] A second dummy structure D2 is arranged around the first dummy structure D1 to protect the memory array A. The second dummy structure D2 includes a plurality of second dummy conductive lines D2L. The number of the second dummy conductive lines D2L is greater than the number of the first dummy conductive lines D1L.

[0073] It can be understood that after the first conductive material layer and the second conductive material layer are formed, a plurality of etching or planarization process steps need to be performed to obtain the first conductive lines L1 and the second conductive lines L2. If the second dummy structure D2 does not exist, when the etching step and the planarization process step occur at the edge position of the first conductive material layer and the second conductive material layer, damage to the first conductive material layer and the second conductive material layer near the edge region is easy to occur. These damages can easily reduce the production yield and even cause a broken circuit, which adversely affects the execution of the production process and the performance of the final product.

[0074] In the embodiments of the present disclosure, by arranging the second dummy structure D2 around the first dummy structure D1 (the first dummy structure D1 surrounds the memory array A), the second dummy structure D2 can provide good protection to the first dummy structure D1 and the memory array A surrounded thereby during the above process, which can effectively prevent the first dummy structure D1 and the memory array A from being damaged to reduce the yield or even cause poor electrical performance, thereby helping to improve the production yield and the electrical performance and structural stability of the final product.

[0075] The number of the second dummy conductive lines D2L included in the second dummy structure D2 can be adjusted according to the actual process. It can be understood that the more the number of the second dummy conductive lines D2L included in the second dummy structure D2, the more advantageous the protection of the memory array A, but the area occupied by the second dummy structure D2 will be larger. The number of the second dummy conductive lines D2L included in the second dummy structure D2 can be as small as possible under the condition that the memory array A is not damaged. In some specific embodiments, the second dummy conductive lines D2L are arranged on each side of the memory array A, and the number of the second dummy conductive lines D2L arranged on each side ranges from 4 to 12. For example, the number of the second dummy conductive lines D2L arranged on each side is 4, 6, 8, 10, or 12.

[0076] In some embodiments, the number of the second dummy conductive lines D2L is greater than the number of the first dummy conductive lines D1L. This makes the second dummy structure D2 provide better protection to the first dummy structure D1 and the memory array A surrounded thereby, which helps to further improve the production yield while further improving the electrical performance and structural stability of the memory.

[0077] Compared with the case where a plurality of discrete memory arrays are included in the memory block 10 and a protection structure is arranged around each of the discrete memory arrays, the difference is that in the embodiment of the present disclosure, each memory block 10 can include only one memory array A, which significantly reduces the number of areas where the protection structure needs to be arranged (the number of areas is reduced from a plurality to one), thereby reducing the area occupied by the protection structure. In the embodiment of the present disclosure, a series of protection structures are arranged only around the memory array A to achieve a better protection effect on the memory array A, so that the structure surrounded thereby is well protected by the second dummy conductive lines D2L arranged around the memory array A, which improves the problem of excessive area occupied by the dummy structure due to the discrete arrangement of the memory array. In addition, in the embodiment of the present disclosure, the number of the first dummy conductive lines D1L is less than the number of the second dummy conductive lines D2L, which means that more space can be left for arranging the redundant structure R on the basis of the above improvement. For example, the number of the first dummy conductive lines D1L can be increased to the number of the redundant conductive lines RL, so that more redundant conductive lines RL can be arranged.

[0078] It can be understood that a larger number of redundant conductive lines helps to improve the repair capability and reduce the risk of failure of the memory block due to the insufficient repair capability of the memory block caused by the small number of redundant conductive lines. At the same time, the increase in the number of redundant structures helps to improve the design window during the design of the redundant structure, improve the repair capability, and is also beneficial to repair and improve the capacity of the memory.

[0079] In addition, in the embodiment of the present disclosure, the arrangement of only one memory array A on each memory block 10 instead of the discrete arrangement of a plurality of memory arrays reduces the area occupied between adjacent memory arrays A, which helps the conductive lines L arranged in the memory array A to extend across a larger distance and area, improves the array area, and helps to improve the design efficiency and the capacity of the obtained memory.

[0080] In the embodiments disclosed herein, the placement of the first dummy conductive line D1L and the second dummy conductive line D2L can include various situations, which will be further described in detail below with reference to the accompanying drawings.

[0081] like Figures 1 to 4 As shown, in some embodiments, the first dummy conductive line D1L includes a plurality of first sub-dummy conductive lines D11 extending along a first direction and a plurality of second sub-dummy conductive lines D12 extending along a second direction; the first sub-dummy conductive lines D11 are located on a first side S1 and a second side S2 oppositely arranged in the storage array A along the second direction, and the second sub-dummy conductive lines D12 are located on a third side S3 and a fourth side S4 oppositely arranged in the storage array A along the first direction.

[0082] The second dummy conductive line D2 includes several third sub-dummy conductive lines D23 extending along the first direction and several fourth sub-dummy conductive lines D24 extending along the second direction; the third sub-dummy conductive lines D23 are located on the first side S1 and the second side S2 of the storage array A, and the fourth sub-dummy conductive lines D24 are located on the third side S3 and the fourth side S4 of the storage array A.

[0083] The redundant conductive line RL includes a plurality of first redundant conductive lines R1 extending along a first direction and a plurality of second redundant conductive lines R2 extending along a second direction; the first redundant conductive lines R1 are located on the first side S1 and / or the second side S2 of the storage array A, and the second redundant conductive lines R2 are located on the third side S3 and / or the fourth side S4 of the storage array A.

[0084] In some embodiments, the first direction and the second direction can be directions on the same plane, and the third direction can be a direction perpendicular to the surface. In some embodiments, the first direction and the second direction can be perpendicular to each other. However, this is not a limitation. In some other embodiments, the angle between the orthographic projections of the first direction and the second direction onto the plane can also be other angles. No specific restrictions are imposed here, and they can be flexibly selected according to the actual situation.

[0085] However, this is not the only possibility. In some other embodiments, the locations of the first redundant conductive line R1 and the second redundant conductive line R2 within the memory block can vary. These embodiments will be described in further detail below with reference to the accompanying drawings. For example:

[0086] In some embodiments, such as Figure 1 As shown, the first redundant conductive line R1 is located on the first side S1 of the storage array A, and the second redundant conductive line R2 is located on the third side S3 of the storage array A.

[0087] In other embodiments, such as Figure 2As shown, the first redundant conductive line R1 is located on the first side S1 and the second side S2 of the storage array A, and the second redundant conductive line R2 is located on the third side S3 of the storage array A.

[0088] In some other embodiments, such as Figure 3 As shown, the first redundant conductive line R1 is located on the first side S1 of the storage array A, and the second redundant conductive line R2 is located on the third side S3 and the fourth side S4 of the storage array A.

[0089] In some other embodiments, such as Figure 4 As shown, the first redundant conductive line R1 is located on the first side S1 and the second side S2 of the storage array A, and the second redundant conductive line R2 is located on the third side S3 and the fourth side S4 of the storage array A.

[0090] Understandable, Figures 1 to 4 In the structure shown, the dummy conductive line located on one side can be placed not only on the side position shown in the figure, but also on the opposite side. For example, a redundant conductive line that is unilaterally located on the first side S1 can also be unilaterally located on the second side S2. Similarly, a redundant conductive line that is unilaterally located on the third side S3 can also be unilaterally located on the fourth side S4. Specifically, the choice can be made flexibly according to the actual situation, and no specific restrictions are imposed here.

[0091] In this embodiment of the disclosure, the placement of the first redundant conductive line R1 and the second redundant conductive line R2 can include various situations in the above embodiments. This helps the operator to flexibly select the number of redundant conductive lines RL that can actually be arranged at each side position according to the actual situation (e.g., the shape or size requirements of other structures set on the side of the storage array A). This has high flexibility and operability, and helps to improve design efficiency, production efficiency and production yield.

[0092] In some embodiments, the number of first sub-dummy conductive lines D11 is equal to the number of second sub-dummy conductive lines D12, and the number of third sub-dummy conductive lines D23 is equal to the number of fourth sub-dummy conductive lines D24.

[0093] In some embodiments, the number of first redundant conductive lines R1 and the number of second redundant conductive lines R2 are both even numbers.

[0094] In some embodiments, the number of the first sub dummy conductive lines D11 can be a positive integer greater than or equal to 1 and less than 8, such as 1, 2, 3, 4, 5, 6, 7, etc., and the number of the second sub dummy conductive lines D12 can also be a positive integer greater than or equal to 1 and less than 8, such as 1, 2, 3, 4, 5, 6, 7, etc.; the number of the third sub dummy conductive lines D23 and the fourth sub dummy conductive lines D24 can be the same value, such as 8 (but not limited to this, and can also be other values); at this time, the number of the first redundant conductive lines R1 can be a positive integer greater than 1 and less than or equal to 15, such as a positive integer greater than 8 and less than or equal to 15, specifically, it can be: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, etc., and the number of the second redundant conductive lines R2 can be a positive integer greater than or equal to 1 and less than or equal to 71, such as a positive integer greater than 64 and less than or equal to 71, specifically, it can be: 65, 66, 67, 69, 70, 71, etc.

[0095] In some specific embodiments, the number of the first sub dummy conductive lines D11 and the second sub dummy conductive lines D12 can both be 2, and the number of the third sub dummy conductive lines D23 and the fourth sub dummy conductive lines D24 can both be 8; the number of the first redundant conductive lines R1 can be 14, and the number of the second redundant conductive lines R2 can be 70.

[0096] But not limited to this, the number of the first redundant conductive lines R1 and the number of the second redundant conductive lines R2 can also contain odd numbers, which are not specifically limited here and can be flexibly selected according to actual conditions.

[0097] It should be noted that the above description of the number of the first sub dummy conductive lines D11, the second sub dummy conductive lines D12, the third sub dummy conductive lines D23, the fourth sub dummy conductive lines D24, and the first redundant conductive lines R1 and the second redundant conductive lines R2 is only an example of some possible implementations and is not the only limit of the application scenario of the present disclosure. In fact, the number of the first sub dummy conductive lines D11, the second sub dummy conductive lines D12, the third sub dummy conductive lines D23, the fourth sub dummy conductive lines D24, and the first redundant conductive lines R1 and the second redundant conductive lines R2 can also be other suitable values, which are not enumerated here.

[0098] It can be understood that, since the leakage of the second conductive line L2 has a greater impact on the performance of the memory than the leakage of the first conductive line L1, in some embodiments, the number of the second redundant conductive lines R2 can be greater than the number of the first redundant conductive lines R1.

[0099] In the embodiments of the present disclosure, by setting the number of the second redundant conductive lines R2 to be greater than the number of the first redundant conductive lines R1, the second conductive lines L2, which have a greater impact on the performance of the memory, can have a greater range of selectable numbers and better operability when encountering a damaged condition that needs to be repaired and replaced, thereby helping to restore the integrity of the electrical performance of the storage array and restore and improve the capacity of the memory.

[0100] However, the number of the second redundant conductive lines R2 can also be less than the number of the first redundant conductive lines R1 in other embodiments, for example, the number of the second redundant conductive lines R2 can also be set to the numerical range of the first redundant conductive lines R1 described in the above content, and the first redundant conductive lines R1 can also be set to the numerical range of the second redundant conductive lines R2 in any of the above embodiments. Specifically, it can be flexibly selected according to actual conditions, which is not limited here.

[0101] In some embodiments, in the setting where the ratio of the number of redundant conductive lines to the sum of the number of first dummy conductive lines and the number of redundant conductive lines is greater than a preset value, the preset value X can be greater than 0.6, for example, between 0.6 < X < 1, such as: 0.6 < X ≤ 0.7, 0.7 ≤ X ≤ 0.8, 0.8 ≤ X ≤ 0.9, or 0.9 ≤ X < 1, etc. Specifically, it can be 0.65, 0.7, 0.75, 0.8, 0.85, 0.875, 0.9, 0.95, etc.

[0102] It can be understood that by setting the ratio of the number of redundant conductive lines to the sum of the number of first dummy conductive lines and the number of redundant conductive lines to be greater than a preset value, the number of redundant conductive lines in the storage block can have a relatively large proportion, i.e., it can contain a larger number of redundant conductive lines, and a larger number of redundant conductive lines can help improve the repair capability and reduce the risk of storage block failure due to insufficient repair capability of the storage block caused by a small number of redundant conductive lines. The increase in the number of redundant structures helps to improve the design window when designing the redundant structure, and the improvement of the repair capability is also beneficial to repair and improve the capacity of the memory.

[0103] In some embodiments, as shown in Figures 5 to 8 the memory further includes a peripheral circuit 10;

[0104] The peripheral circuit 20 and the storage array A are sequentially stacked along a third direction; the third direction is perpendicular to the first direction and the second direction (for details, please refer to Figure 5 );

[0105] The first dummy conductive line D1L is connected with the peripheral circuit 20 through a first contact structure CT1; the second dummy conductive line D2L is arranged in a floating manner relative to the peripheral circuit 20; the redundant conductive line RL is connected with the peripheral circuit 20 through a second contact structure CT2; and the conductive line L is connected with the peripheral circuit 20 through a third contact structure CT3 (for details, refer to FIGS. Figure 6 , Figure 7 and Figure 8 ).

[0106] In some embodiments, the peripheral circuit includes any suitable digital, analog and / or mixed-signal circuit for facilitating the operation of the phase change memory. For example, the peripheral circuit can include control logic, data buffer, decoder (the decoder can also be referred to as a decoder), driver and read-write circuit, etc. When the control logic receives a read-write operation command and address data, under the action of the control logic, the decoder can apply a corresponding voltage generated from the driver to a corresponding bit line and word line based on the decoded address, so as to realize the reading and writing of data, and interact with the outside through the data buffer.

[0107] It can be understood that, in some embodiments, the first dummy conductive line D1L can be connected with a structure having a fixed potential in the peripheral circuit 20, the conductive line L can be connected with a driver and a decoder in the peripheral circuit 20, and the structure connected with the redundant conductive line RL can include but is not limited to a circuit for repair, etc.

[0108] In some embodiments, as shown in FIGS. Figure 8 , the first sub-dummy conductive line D11, the first redundant conductive line R1 and the first conductive line L1 can be provided with the third contact structure CT3 at a position located at the edge of the storage block 10, so as to realize the electrical connection between the conductive lines and the peripheral circuit 20.

[0109] However, the third contact structure CT3 can also be arranged at a position located between the storage blocks 10 in some other embodiments, and the arrangement position of the third contact structure CT3 can be flexibly adjusted according to actual conditions, which is not limited herein.

[0110] In some embodiments, as shown in FIGS. Figure 5 and Figure 8 , the storage array A includes a first bit line layer BL1, a first storage unit layer CL1, a word line layer WL, a second storage unit layer CL2 and a second bit line layer BL2 arranged in a stacked manner along a third direction in sequence;

[0111] The first bit line layer BL1 and the second bit line layer BL2 each include a plurality of second conductive lines L2, the first storage unit layer CL1 and the second storage unit layer CL2 each include a plurality of storage units C, and the word line layer WL includes a plurality of first conductive lines L1.

[0112] The blank region B exists in a plurality of first conductive lines L1 included in the word line layer WL.

[0113] In some embodiments, the first dummy conductive line D1L further includes a plurality of fifth sub-dummy conductive lines D15 extending along the first direction, the fifth sub-dummy conductive lines D15 being disposed on both sides of the blank region B along the second direction.

[0114] The second dummy conductive line D2L further includes a plurality of sixth sub-dummy conductive lines D26 extending along the first direction, the sixth sub-dummy conductive lines D26 being disposed between the blank region B and the fifth sub-dummy conductive lines D15.

[0115] In some embodiments, the first sub-dummy conductive line D11, the third sub-dummy conductive line D23, the fifth sub-dummy conductive line D15, the sixth sub-dummy conductive line D26, the first redundant conductive line R1, and the word line layer WL can be formed by using the same material and in the same process step, in other words, the first sub-dummy conductive line D11, the third sub-dummy conductive line D23, the fifth sub-dummy conductive line D15, the sixth sub-dummy conductive line D26, the first redundant conductive line R1, and the word line layer WL can be the same structure.

[0116] Similarly, in some embodiments, the second sub-dummy conductive line D12, the fourth sub-dummy conductive line D24, the second redundant conductive line R2, the first bit line layer BL1, and the second bit line layer BL2 can also be formed by using the same material and in the same process step, in other words, the second sub-dummy conductive line D12, the fourth sub-dummy conductive line D24, the second redundant conductive line R2, the first bit line layer BL1, and the second bit line layer BL2 can be the same structure.

[0117] In addition, in the embodiments of the present disclosure, the storage unit C is not only arranged in the storage array A, but also arranged between the first sub-virtual conductive line D11 and the conductive line intersecting therewith (including but not limited to the second sub-virtual conductive line D12, the fourth sub-virtual conductive line D24, the second redundant conductive line R2 and the second conductive line L2), between the third sub-virtual conductive line D23 and the conductive line intersecting therewith (including but not limited to the second sub-virtual conductive line D12, the fourth sub-virtual conductive line D24, the second redundant conductive line R2 and the second conductive line L2), between the first redundant conductive line R1 and the conductive line intersecting therewith (including but not limited to the second sub-virtual conductive line D12, the fourth sub-virtual conductive line D24, the second redundant conductive line R2 and the second conductive line L2), and between the fifth sub-virtual conductive line D15 and the sixth sub-virtual conductive line D26 and the conductive line intersecting therewith (including but not limited to the second sub-virtual conductive line D12 and the fourth sub-virtual conductive line D24, the second redundant conductive line R2 and the second conductive line L2). The storage unit C located in the storage array A and the storage unit C located at the intersection point in other positions can be obtained in the same process step and can have the same structure.

[0118] In the embodiments of the present disclosure, the blank area B is used to divide the plurality of first conductive lines L1 located in the word line layer WL into two areas, and each area contains a plurality of first conductive lines L1. Meanwhile, in the embodiments of the present disclosure, the two second conductive lines L2 located at the blank area B and located at the second bit line layer BL2 are in a disconnected state, while the storage unit C and the word line WL structure located below the second bit line layer BL2 are in a normal existing state.

[0119] In some embodiments, the number of the sixth sub-virtual conductive lines D26 is less than the number of the third sub-virtual conductive lines D23.

[0120] In the embodiments of the present disclosure, the sixth sub-virtual conductive line D26 can be arranged floating relative to the peripheral circuit 20. The sixth sub-virtual conductive line D26 can play a protective role for the first conductive lines L1 located around in the process of disconnecting (which can adopt an etching process) the adjacent second conductive lines L2 located in the blank area B, so as to prevent these first conductive lines L1 from being damaged or damaged.

[0121] In addition, since the adjacent second conductive lines L2 in the second bit line layer BL2 in this area are in a disconnected state at the blank area B, no contact structure is arranged, and at the same time, the storage unit and the word line WL in the blank area B below the second bit line layer BL2 are normally present (without the need to perform etching operation), so that the periphery of the blank area B can also meet the process window of the etching process operation process without the need to arrange a large number of virtual conductive lines.

[0122] In addition, compared with the pad structure for test operation arranged near the blank area B in the conventional process, in the blank area B of the embodiment of the present disclosure, the pad structure for test operation is arranged at other positions, so that the reduction of the number of the fifth dummy conductive lines near the area does not affect the structural integrity and the test operation of the memory.

[0123] In some embodiments, the number of the fifth dummy conductive lines D15 can be equal to the number of the sixth sub-dummy conductive lines D26.

[0124] Optionally, in some embodiments, the number of the fifth sub-dummy conductive lines D15 can range from greater than or equal to 1 and less than 8, for example, 1, 2, 3, 4, 5, 6, 7; and the number of the sixth sub-dummy conductive lines D26 can range from greater than or equal to 1 and less than 8, for example, 1, 2, 3, 4, 5, 6, 7.

[0125] In some specific embodiments, the number of the fifth dummy conductive lines D15 can be equal to the number of the sixth sub-dummy conductive lines D26, both of which can be 2.

[0126] It can be understood that the reduction of the number of dummy conductive lines near the blank area B means that more space can be left for the conductive lines at other positions (such as the conductive lines of the storage array or the redundant conductive lines, etc.) and a larger design window, which is beneficial to the improvement of the memory capacity and the improvement of the design efficiency.

[0127] In some embodiments, as shown in Figure 9a and Figure 9b The memory includes a plurality of storage blocks 10 related to any of the above embodiments, and the plurality of storage blocks 10 are arranged in an array along the direction in which the conductive lines L extend. Specifically, the plurality of storage blocks 10 can include a plurality of rows arranged in a first direction and a plurality of columns arranged in a second direction.

[0128] In the embodiment of the present disclosure, as shown in Figure 9bAs shown, the plurality of memory blocks 10 adopt a full print design. In the full print design, the first conductive lines L1 and the second conductive lines L2 are in a state of covering the entire area where each memory block 10 is located, and no blank area is intentionally left for the first conductive lines L1 and the second conductive lines L2. In contrast, in a discrete design, the first conductive lines and the second conductive lines are not in a state of covering the entire area where each memory block 10 is located, and there is a blank area where no first conductive lines and second conductive lines are arranged along the direction parallel to the thickness of the memory block 10. Due to the protection function of the second dummy conductive lines D2L, the overall yield of the memory is improved. In the full print design, the storage capacity of the memory can be improved while ensuring a good yield. It can be understood that when the memory block 10 includes a plurality of discrete memory array regions, in order to protect the conductive lines in each memory array region from being damaged during preparation, a large number of dummy structures (first dummy structures and second dummy structures, which are usually equal in number, for example, 8 first dummy structures and 8 second dummy structures are arranged on the same side) need to be designed around each memory array region, which occupies a large amount of space. At this time, in order to ensure that the storage capacity of the memory in the memory array region is not affected, the number of other structures, such as redundant structures, will be compressed to some extent, which reduces the repair capability of the redundant structures to the conductive lines, thereby adversely affecting the integrity of the memory array and also adversely affecting the repair and improvement of the storage capacity of the memory.

[0129] Therefore, in the embodiments of the present disclosure, the full print design of each memory block 10 instead of the discrete arrangement of a plurality of memory arrays reduces the area occupation between adjacent memory arrays A, which can help the conductive lines L arranged in the memory array A to span a larger distance and area when extending, thereby improving the array area and helping to improve the design efficiency and the capacity of the obtained memory.

[0130] It should be noted that although the memory is shown to include four memory blocks 10 in Figure 9a , this is only an example and is not the only limitation of the application scenario of the present disclosure. In actual operation, the number of memory blocks 10 can include multiple, such as two, six, eight, ten, a dozen, dozens, hundreds or even more, etc. Specifically, the number can be selected according to the actual situation, and no specific limitation is made here.

[0131] In addition, in Figure 9bIn the specific embodiments, although it is shown that the storage block 10 included in the memory is a schematic diagram of a group of storage block 10 structures with the same structure, which is only exemplary and is not the only limitation of the application scenario of the embodiments of the present disclosure. It should be noted that in actual operation, the storage block 10 included in the memory can also be a plurality of storage block 10 structures with different structures. Specifically, the structure of the storage block 10 included in the memory can be at least one of any of the above embodiments or a combination thereof.

[0132] It should be noted that the memory provided by the embodiments of the present disclosure can be a phase change memory structure or other possible semiconductor structure, which is not limited here. The embodiments of the preparation method of the semiconductor structure provided by the present disclosure belong to the same concept as the embodiments of the semiconductor structure. In the technical solutions recorded in each embodiment, the technical features can be combined arbitrarily without conflict.

[0133] The above is only a preferred embodiment of the present disclosure, and is not intended to limit the protection scope of the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A memory, characterized in that, include: At least one storage block; Each of the storage blocks includes: A storage array; the storage array includes a plurality of conductive lines and a plurality of storage cells located between the conductive lines; A first dummy structure, at least surrounding the memory array, is used to provide a fixed potential for testing; the first dummy structure includes a plurality of first dummy conductive lines; A redundant structure, located between the storage array and the first dummy structure, is used to repair the damaged conductive lines; the redundant structure includes a plurality of redundant conductive lines. The ratio of the number of redundant conductive lines to the sum of the number of the first dummy conductive lines and the number of redundant conductive lines is greater than a preset value.

2. The memory according to claim 1, characterized in that, The preset value is greater than 0.

6.

3. The memory according to claim 1, characterized in that, The memory also includes: A second dummy structure, at least surrounding the first dummy structure, is used to provide protection for the storage array; the second dummy structure includes a plurality of second dummy conductive lines; the number of second dummy conductive lines is greater than the number of first dummy conductive lines.

4. The memory according to claim 3, characterized in that, The conductive lines include a plurality of first conductive lines extending along a first direction and a plurality of second conductive lines extending along a second direction; the first direction and the second direction intersect; the storage unit is located between the first conductive lines and the second conductive lines. The first dummy conductive line includes a plurality of first sub-dummy conductive lines extending along a first direction and a plurality of second sub-dummy conductive lines extending along a second direction; the first sub-dummy conductive lines are located on a first side and a second side of the storage array that are opposite to each other along the second direction, and the second sub-dummy conductive lines are located on a third side and a fourth side of the storage array that are opposite to each other along the first direction. The second dummy conductive line includes a plurality of third sub-dummy conductive lines extending along a first direction and a plurality of fourth sub-dummy conductive lines extending along a second direction; the third sub-dummy conductive lines are located on the first side and the second side of the storage array, and the fourth sub-dummy conductive lines are located on the third side and the fourth side of the storage array. The redundant conductive lines include a plurality of first redundant conductive lines extending along a first direction and a plurality of second redundant conductive lines extending along a second direction; the first redundant conductive lines are located on a first side and / or a second side of the storage array, and the second redundant conductive lines are located on a third side and / or a fourth side of the storage array.

5. The memory according to claim 4, characterized in that, The number of the first sub-dummy conductive lines is equal to the number of the second sub-dummy conductive lines, and the number of the third sub-dummy conductive lines is equal to the number of the fourth sub-dummy conductive lines.

6. The memory according to claim 4, characterized in that, The leakage current of the second conductive line has a greater impact on the performance of the memory than the leakage current of the first conductive line; the number of the second redundant conductive lines is greater than the number of the first redundant conductive lines.

7. The memory according to claim 4, characterized in that, The number of the first redundant conductive lines and the number of the second redundant conductive lines are both even numbers.

8. The memory according to claim 4, characterized in that, The memory also includes peripheral circuitry; The peripheral circuits and the storage array are stacked sequentially along a third direction; the third direction is perpendicular to both the first direction and the second direction. The first dummy conductive line is connected to the peripheral circuit through a first contact structure; the second dummy conductive line is floating relative to the peripheral circuit; the redundant conductive line is connected to the peripheral circuit through a second contact structure; and the conductive line is connected to the peripheral circuit through a third contact structure.

9. The memory according to claim 8, characterized in that, The storage array includes a first bit line layer, a first storage cell layer, a word line layer, a second storage cell layer, and a second bit line layer stacked sequentially along the third direction; Both the first bit line layer and the second bit line layer include a plurality of second conductive lines, both the first memory cell layer and the second memory cell layer include a plurality of memory cells, and the word line layer includes a plurality of first conductive lines. The word line layer contains blank areas among its several first conductive lines.

10. The memory according to claim 9, characterized in that, The first dummy conductive line also includes a plurality of fifth sub-dummy conductive lines extending along the first direction, the fifth sub-dummy conductive lines being disposed on both sides of the blank area along the second direction; The second dummy conductive line also includes a plurality of sixth sub-dummy conductive lines extending along the first direction, wherein the sixth sub-dummy conductive lines are disposed between the blank area and the fifth sub-dummy conductive line.

11. The memory according to claim 10, characterized in that, The number of the sixth sub-dummy conductive lines is less than the number of the third sub-dummy conductive lines.

12. The memory according to any one of claims 1 to 11, characterized in that, The memory includes multiple memory blocks, which are arranged in an array along the direction in which the conductive lines extend.

Images