A multi-level converter topology and control method

Abstract

This application relates to the field of power electronics control technology, and discloses a multilevel converter topology and control method. The topology includes a six-level hybrid clamp converter topology or an eight-level hybrid clamp converter topology. The control method includes a phase-locked synchronization control loop, a power control loop, a total DC voltage balancing control loop between upper / lower arm power submodules, a voltage equalization control loop for each voltage divider capacitor, and a pulse width modulation and pulse signal generation loop. This application achieves voltage balancing between the total voltage of the hybrid clamp power submodule and each voltage divider capacitor. By combining the multilevel hybrid clamp power submodule with the flying capacitor power submodule, the topology is simple to implement, highly scalable, requires fewer power devices, has a simple control method, and achieves voltage self-balancing for the voltage dividers. It enables direct connection at medium and high voltage levels and can be widely promoted and applied in medium and high voltage distribution networks, energy storage converters, transformer interconnection, and flexible DC transmission, with a broad market potential.

Description

Technical Field

[0001] This invention relates to the field of power electronic control technology, and in particular to a multilevel converter topology and control method. Background Technology

[0002] With the rapid development of new energy power generation and high-voltage direct current (HVDC) transmission technologies, the demand for medium- and high-voltage large-capacity power electronic converters is increasing. Traditional two-level converters, due to limitations in device withstand voltage and high harmonic content in the output waveform, cannot directly meet the requirements of medium- and high-voltage applications. Multilevel converters, by cascading multiple power units, significantly reduce the voltage stress on individual devices, while the stepped output waveform greatly reduces harmonic content, thus becoming core equipment in medium- and high-voltage frequency converters, energy storage converters, distribution network interconnection, and flexible HVDC transmission. Among various multilevel topologies, the cascaded H-bridge structure is the most widely used in medium- and high-voltage motor frequency conversion speed control due to its high modularity and strong scalability. It achieves flexible expansion of the number of output voltage levels through the cascading of multiple H-bridge submodules, effectively solving the problem of insufficient device withstand voltage in traditional solutions. However, this topology also faces the challenge of a significant increase in the number of switching devices and control complexity as the number of levels increases exponentially. While traditional diode or capacitor clamped multilevel converters can reduce device voltage stress, they suffer from problems such as high clamping element losses and complex DC-side capacitor voltage balance control. Modular multilevel converters (MMCs), while offering scalability advantages, are difficult to scale up due to their large number of modules, high cost, and large size.

[0003] Therefore, there is an urgent need for a multilevel converter topology and its control method to achieve direct connection of medium and high voltage levels, and to realize efficient, green and energy-saving conversion. Summary of the Invention

[0004] The main objective of this invention is to provide a multilevel converter topology and control method, aiming to solve the problems faced by existing multilevel technologies, such as the number of switching devices increasing exponentially with the number of levels, significantly increased control complexity, high cost, large size, and difficulty in large-scale application.

[0005] To achieve the above objectives, the present invention provides a multilevel converter topology, including a six-level hybrid clamp converter topology or an eight-level hybrid clamp converter topology; both the six-level hybrid clamp converter topology and the eight-level hybrid clamp converter topology include two multilevel hybrid clamp power submodules and one multilevel flying capacitor power submodule, wherein the two multilevel hybrid clamp power submodules are connected in series with a capacitor and then interconnected with the multilevel flying capacitor power submodule to provide medium and high voltage level output on the AC side.

[0006] Preferably, the multilevel converter topology is equipped with a corresponding control method, which includes a phase-locked synchronization control loop, a power control loop, a total DC voltage equalization control loop between the upper / lower bridge arm power submodules, a voltage equalization control loop for each voltage divider capacitor, and a pulse width modulation and pulse signal generation loop. Based on the initial duty cycle output in the power control loop, the zero-sequence component and the voltage equalization control component are superimposed to perform mixed clamping of the total voltage of the power submodule and the equalization of each voltage divider capacitor. The modulation signal output by the controller of each loop is compared with the phase-shifted carrier to complete the control of the power devices.

[0007] Synchronization with the power grid and power command control are achieved through phase-locked synchronization control and power control. The controller output value is used as the initial duty cycle and superimposed with the zero-sequence current component to achieve total voltage balance between the upper and lower bridge arm hybrid clamping power submodules. The command difference signal of each voltage divider capacitor is passed through an independent controller and then the output signal is synchronously superimposed on the control signal to control each voltage divider capacitor.

[0008] The duty cycle obtained by the power control and voltage equalization control loops is compared with multiple sets of phase-shifted carrier signals to control the entire multi-level hybrid clamp converter topology.

[0009] As a preferred embodiment, the six-level hybrid clamp converter topology is specifically composed of two three-level hybrid clamp power sub-modules and one three-level flying capacitor power sub-module;

[0010] The six-level hybrid clamp converter corresponds to phases A, B, and C of a three-phase converter, and phases A, B, and C have the same structure; specifically, phase A includes: an insulated-gate bipolar transistor. to Clamping diode to ,capacitance to and AC filter inductor Among them, capacitors ,capacitance Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series to clamp the diode. Anode and clamping diode After the cathode is connected, a capacitor is connected in parallel. Clamped diode Cathode and clamping diode The anodes are respectively connected to the insulated gate bipolar transistor. Insulated Gate Bipolar Transistor and insulated gate bipolar transistor Insulated Gate Bipolar Transistor Between these components, a three-level hybrid clamping power submodule is formed at the upper end; capacitor ,capacitance Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series to clamp the diode. Anode and clamping diode After the cathode is connected, a capacitor is connected in parallel. Clamped diode Cathode and clamping diode The anodes are respectively connected to the insulated gate bipolar transistor. Insulated Gate Bipolar Transistor and insulated gate bipolar transistor Insulated Gate Bipolar Transistor Between these components, a three-level hybrid clamping power submodule is formed at the lower end; Insulated Gate Bipolar Transistor to Interconnected and insulated gate bipolar transistors to Interconnected in series, insulated gate bipolar transistor Emitter-gate bipolar transistor Parallel capacitor between collectors Insulated Gate Bipolar Transistor Emitter-gate bipolar transistor Parallel capacitor between collectors This forms a three-level flying capacitor power submodule; the corresponding three-level hybrid clamping power submodules located at the upper and lower ends are connected to the capacitor. After series connection, the output terminal is connected to the three-level flying capacitor power submodule, and the output point of the three-level flying capacitor power submodule is connected to the AC filter inductor. The connections form a six-level hybrid clamp converter topology.

[0011] As a preferred embodiment, the eight-level hybrid clamp converter topology is specifically composed of two four-level hybrid clamp power sub-modules and one four-level flying capacitor power sub-module.

[0012] The eight-level hybrid clamp converter corresponds to phases A, B, and C in a three-phase converter, and phases A, B, and C have the same structure; for phase A, it specifically includes: an insulated gate bipolar transistor. to Clamping diode to ,capacitance to and AC filter inductor Among them, capacitors ,capacitance ,capacitance Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series; clamped diode Anode and clamping diode Cathode connection, clamped diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor Collector connection; clamped diode Anode and clamping diode Cathode connection, clamped diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor collector connection; capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor collector connection, capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor The collector connections form the upper four-level hybrid clamp power submodule; capacitors To capacitor Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series; clamped diode Anode and clamping diode Cathode connection, clamped diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor Collector connection; clamped diode Anode and clamping diode Cathode connection, clamped diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor collector connection; capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor collector connection, capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor The collector connections form the lower four-level hybrid clamped power submodule; Insulated Gate Bipolar Transistor to Interconnected and insulated gate bipolar transistors to Interconnected in series, insulated gate bipolar transistor Emitter-gate bipolar transistor Parallel capacitor between collectors Insulated Gate Bipolar Transistor Emitter-gate bipolar transistor Parallel capacitor between collectors Insulated Gate Bipolar Transistor Emitter-gate bipolar transistor Parallel capacitor between collectors This forms a four-level flying capacitor power submodule; the four-level hybrid clamping power submodules located at the upper and lower ends are connected to the capacitor. After series connection, the output terminal is connected to the four-level flying capacitor power submodule, and the output point of the four-level flying capacitor power submodule is connected to the AC filter inductor. The connections form an eight-level hybrid clamp converter topology.

[0013] As a preferred embodiment, the total DC voltage balancing control link between the multi-level hybrid clamping power submodules in the six-level hybrid clamping converter topology is to use its capacitor ,capacitance Total voltage With capacitor ,capacitance Total voltage After subtraction, the capacitance value of the DC capacitor is obtained. and control cycle Estimate the magnitude of the injected zero-sequence current component and then compare it with the initial duty cycle. The updated duty cycle is obtained after calculation. The corresponding calculation formula is:

[0014]

[0015] in: Representing phases A, B, and C, corresponding to , This is the sign function for the initial duty cycle of phase A, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase B, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase C, with a positive value of 1 and a negative value of -1. The initial duty cycle of phase A. This is the initial duty cycle of phase B. This represents the initial duty cycle of phase C.

[0016] As a preferred embodiment, the voltage equalization control stage of each voltage divider capacitor in the six-level hybrid clamp converter topology is to equalize the target voltage. With each voltage divider capacitor ,capacitance ,capacitance and capacitor The voltage difference is then passed through a PI controller and multiplied by the phase current. , , The sign function is obtained , , and Then, with the updated duty cycle The final duty cycle is obtained after addition and subtraction calculations. The corresponding formula is expressed as:

[0017]

[0018] After voltage equalization through each voltage-dividing capacitor, the other capacitors... to It also performs self-equalization.

[0019] As a preferred embodiment, the pulse width modulation and pulse signal generation stages of the six-level hybrid clamp converter topology follow the following operating rules:

[0020] Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor (IGBT) with complementary conduction in pairs and Insulated Gate Bipolar Transistor and Synchronous, Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor to Interleaved conduction, its carrier signal phase shift , The number of devices is determined based on interleaved conduction.

[0021] As a preferred embodiment, the total DC voltage balancing control link between the multi-level hybrid clamping power submodules in the eight-level hybrid clamping converter topology is to use its capacitor to Total voltage With capacitor to Total voltage After subtraction, the capacitance value of the DC capacitor is obtained. and control cycle Estimate the magnitude of the injected zero-sequence current component and then compare it with the initial duty cycle. The updated duty cycle is obtained after calculation. The corresponding calculation formula is:

[0022]

[0023] in: Representing phases A, B, and C, corresponding to , This is the sign function for the initial duty cycle of phase A, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase B, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase C, with a positive value of 1 and a negative value of -1. The initial duty cycle of phase A. This is the initial duty cycle of phase B. This represents the initial duty cycle of phase C.

[0024] Preferably, in the voltage equalization control stage of each voltage divider capacitor in the eight-level hybrid clamp converter topology, the target voltage is... With each voltage divider capacitor ,capacitance to and capacitors The voltage difference is then passed through a PI controller and multiplied by the phase current. , , The sign function is obtained , , , , and Then, with the updated duty cycle The final duty cycle is obtained after addition and subtraction calculations. The corresponding formula is expressed as:

[0025]

[0026] After voltage equalization through each voltage-dividing capacitor, the other capacitors... to and capacitors to It also performs self-equalization.

[0027] As a preferred embodiment, the pulse width modulation and pulse signal generation stages of the eight-level hybrid clamp converter topology follow the following operating rules:

[0028] Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor (IGBT) with complementary conduction in pairs and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Synchronous, Insulated Gate Bipolar Transistor to Insulated Gate Bipolar Transistor to Interleaved conduction, its carrier signal phase shift , The number of devices is determined based on interleaved conduction.

[0029] Beneficial effects: The multilevel converter topology and control method of this application, through the combination of multilevel hybrid clamping power submodule and flying capacitor power submodule, achieves a simple topology, strong scalability, relatively few power devices, simple control method, easy voltage self-balancing of voltage dividers, and direct connection of medium and high voltage levels. It can be widely promoted and applied in medium and high voltage distribution networks, energy storage converters, transformer interconnection and flexible DC transmission, etc., with a broad market and provides theoretical guidance for achieving efficient, green and energy-saving conversion. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a topology diagram of a six-level hybrid clamp converter provided in an embodiment of the present invention;

[0032] Figure 2 An eight-level hybrid clamp converter topology diagram provided for an embodiment of the invention;

[0033] Figure 3 The control block diagram of the six-level hybrid clamp converter provided in the embodiment of the present invention; in the figure: (a) phase-locked synchronization control loop; (b) power control loop; (c) voltage equalization control loop for upper / lower arm power modules; (d) voltage equalization control loop for voltage divider capacitors; (e) pulse width modulation and pulse signal generation loop;

[0034] Figure 4 The control block diagram of the eight-level hybrid clamp converter provided in the embodiment of the present invention; in the figure: (a) phase-locked synchronization control loop; (b) power control loop; (c) voltage equalization control loop for upper / lower arm power modules; (d) voltage equalization control loop for voltage divider capacitors; (e) pulse width modulation and pulse signal generation loop;

[0035] Figure 5The three-phase current waveform diagram of a six-level hybrid clamp converter topology at a voltage level of 10kV is provided for an embodiment of the present invention.

[0036] Figure 6 The waveform diagram provided in this embodiment of the invention shows the three-phase line voltage before filtering using a six-level hybrid clamp converter topology at a voltage level of 10kV; in the figure: (a) unfiltered line voltage V AB (b) Unfiltered phase voltage V A (c) Unfiltered phase voltage V B ;

[0037] Figure 7 The following are voltage waveforms of the voltage divider capacitors in a six-level hybrid clamp converter topology at a voltage level of 10kV, provided for embodiments of the present invention. In the figure: (a) simulated voltage waveform of capacitor C1; (b) simulated voltage waveform of capacitor C2; (c) simulated voltage waveform of capacitor C3; (d) simulated voltage waveform of capacitor C4; (e) simulated voltage waveform of capacitor C5; (f) simulated voltage waveform of capacitor C6; (g) simulated voltage waveform of capacitor C7; (h) simulated voltage waveform of capacitor C8.

[0038] The implementation, functional features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0039] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0040] To address the challenges of existing technologies where the number of switching devices increases exponentially with the number of voltage levels, leading to significantly increased control complexity, high cost, large size, and difficulty in large-scale application, this embodiment discloses a multilevel converter topology and control method. The multilevel converter topology includes either a six-level hybrid clamp converter topology or an eight-level hybrid clamp converter topology, both of which can be composed of two sets of multilevel hybrid clamp power submodules and one set of flying capacitor power submodules. The corresponding control method includes a phase-locked loop synchronization control loop, a power control loop, a total DC voltage balancing control loop between the upper / lower arm power submodules, a voltage equalization control loop for each voltage divider capacitor, and a pulse width modulation and pulse signal generation loop.

[0041] Reference Figure 1 , Figure 1 This is a topology diagram of a six-level hybrid clamp converter provided in this embodiment.

[0042] like Figure 1As shown, the six-level hybrid clamp converter topology consists of two three-level hybrid clamp power submodules and one three-level flying capacitor power submodule. The characteristic of this structure is that five sets of capacitors are connected in series on the DC side. The upper and lower sets of capacitors, together with two diodes, one floating capacitor and four switching power devices, form two sets of three-level hybrid clamp power submodules. After being interconnected with a three-level flying capacitor power submodule, a six-level output is achieved.

[0043] like Figure 1 As shown, the six-level hybrid clamp converter topology includes an insulated-gate bipolar transistor with an anti-parallel diode. to Clamping diode to ,capacitance to and AC filter inductor Among them, capacitors , Transistors connected in series and then in parallel collector and The emitter of the transistor , , , The collector and emitter are connected in series in a diode. anode and diode After the cathode is connected, a capacitor is connected in parallel. , cathode and The anodes are respectively connected , and , Between these components, an upper three-level hybrid clamping power submodule is formed; capacitor , Transistors connected in series and then in parallel collector and The emitter of the transistor , , , The collector and emitter are connected in series in a diode. anode and diode After the cathode is connected, a capacitor is connected in parallel. , cathode and The anodes are respectively connected , and , This forms the lower-end three-level hybrid clamping power submodule; transistor , , Interconnected and transistor , , After being connected in series, they are interconnected. emitter and Parallel capacitor between collectors , emitter and Parallel capacitor between collectors (the capacitor) Designed to increase control freedom (can be omitted), thus forming a three-level flying capacitor power submodule; upper / lower three-level hybrid clamping power submodule and capacitor After series connection, the output terminal is connected to the three-level flying capacitor power submodule, and the output point of the three-level flying capacitor power submodule is connected to the AC filter inductor. The connections form a six-level hybrid clamp converter topology. The above describes phase A of a three-phase converter; phases B and C have the same structure.

[0044] Reference Figure 2 , Figure 2 This is a topology diagram of the eight-level hybrid clamp converter provided in this embodiment.

[0045] like Figure 2 As shown, the hybrid clamp converter topology can be composed of two four-level hybrid clamp power submodules and one four-level flying capacitor power submodule to form an eight-level hybrid clamp converter topology. The feature of this structure is that seven sets of capacitors are connected in series on the DC side. Among them, the three sets of capacitors on the upper and lower sides are respectively connected with four diodes, two floating capacitors and six switching power devices to form two sets of four-level hybrid clamp power submodules. After being interconnected with a four-level flying capacitor power submodule, eight-level output is achieved.

[0046] like Figure 2 As shown, the eight-level hybrid clamp converter topology includes an insulated-gate bipolar transistor with an anti-parallel diode. to Clamping diode to ,capacitance to and AC filter inductor Among them, capacitors , , Transistors connected in series and then in parallel collector and The emitter of the transistor , , , , , The collector and emitter are connected in series; diode anode and diode Cathode connection, diode cathode and collector connection, diode anode and collector connection; diode anode and diode Cathode connection, diode cathode and collector connection, diode anode and collector connection; capacitor The two ends are respectively with , collector connection, capacitor The two ends are respectively with , The collector connections form the upper four-level hybrid clamp power submodule. Capacitor , , Transistors connected in series and then in parallel collector and The emitter of the transistor , , , , , The collector and emitter are connected in series; diode anode and diode Cathode connection, diode cathode and collector connection, diode anode and collector connection; diode anode and diode Cathode connection, diode cathode and collector connection, diode anode and collector connection; capacitor The two ends are respectively with , collector connection, capacitor The two ends are respectively with , The collector connections form the lower-end four-level hybrid clamp power submodule. Transistor , , , Interconnected and transistor , , , After being connected in series, they are interconnected. emitter and Parallel capacitor between collectors , emitter and Parallel capacitor between collectors , emitter and Parallel capacitor between collectors (the capacitor) , This is designed to increase control freedom (and can be omitted), thus forming a four-level flying capacitor power submodule; after the upper / lower four-level hybrid clamping power submodule is connected in series with capacitor C4, the output terminal is connected to the four-level flying capacitor power submodule, and the output point of the four-level flying capacitor power submodule is connected to the AC filter inductor. The connections form an eight-level hybrid clamp converter topology. The above describes phase A of a three-phase converter; phases B and C have the same structure.

[0047] Reference Figure 3 , Figure 3 The control block diagram of the six-level hybrid clamp converter provided in this embodiment is shown in the figure. In the figure: (a) phase-locked synchronization control loop; (b) power control loop; (c) voltage equalization control loop for upper / lower arm power modules; (d) voltage equalization control loop for voltage divider capacitors; (e) pulse width modulation and pulse signal generation loop.

[0048] like Figure 3 As shown, the control method of the six-level hybrid clamp converter achieves synchronization with the power grid and completes power command control through phase-locked loop synchronization control and power control. The controller output value is used as the initial duty cycle, superimposed with the zero-sequence current component to achieve overall voltage balance between the upper and lower bridge arm hybrid clamp power submodules. The command difference signals of each voltage divider capacitor are synchronously superimposed onto the control signal after passing through independent controllers, thus achieving control of each voltage divider capacitor. The duty cycle obtained by the power control and voltage equalization control loops is compared with multiple sets of phase-shifted carrier signals to complete the control of the entire multi-level hybrid clamp converter topology.

[0049] The overall DC voltage balancing control link between the multilevel hybrid clamping power submodules in the six-level hybrid clamping converter topology is to balance the capacitors... , Total voltage With capacitor , Total voltage After subtraction, the capacitance value of the DC capacitor is obtained. and control cycle Estimate the magnitude of the injected zero-sequence current component and then compare it with the initial duty cycle. ( The updated duty cycle is obtained after performing simple calculations on phases A, B, and C. The calculation formula is as follows:

[0050] (1)

[0051] in, a corresponds to phase A, b corresponds to phase B, and c corresponds to phase C. This is the sign function for the initial duty cycle of phase A, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase B, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase C, with a positive value of 1 and a negative value of -1. The initial duty cycle of phase A. This is the initial duty cycle of phase B. This represents the initial duty cycle of phase C.

[0052] The voltage equalization control loop of each voltage divider capacitor in the six-level hybrid clamp converter topology is to equalize the target voltage. With each voltage divider capacitor , , and ( The voltage difference (which can be omitted) is then passed through a PI controller and multiplied by the current of each phase. , , The sign function is obtained , , , Then, with the updated duty cycle The final duty cycle is obtained after performing simple addition and subtraction calculations. Its formula is expressed as:

[0053] (2)

[0054] After voltage equalization is achieved through each voltage-dividing capacitor, the other capacitors... , , , It can also achieve self-equalizing pressure.

[0055] The pulse width modulation and pulse signal generation stages of a six-level hybrid clamp converter topology follow the following modulation rules: power devices and... , and , and , and , and , and , and Two complementary conductions, power devices and , and Synchronization, power devices , , , , Interleaved conduction, its carrier signal phase shift , It is determined by the number of devices that are interleaved in conduction.

[0056] Reference Figure 4 , Figure 4 The control block diagram of the six-level hybrid clamp converter provided in this embodiment is shown in the figure. In the figure: (a) phase-locked synchronization control loop; (b) power control loop; (c) voltage equalization control loop for upper / lower arm power modules; (d) voltage equalization control loop for voltage divider capacitors; (e) pulse width modulation and pulse signal generation loop.

[0057] like Figure 4 As shown, the total DC voltage balancing control loop between the multi-level hybrid clamp power submodules in the eight-level hybrid clamp converter topology is to balance the capacitor... , , Total voltage With capacitor , , Total voltage After subtraction, the capacitance value of the DC capacitor is obtained. and control cycle Estimate the magnitude of the injected zero-sequence current component and then compare it with the initial duty cycle. The updated duty cycle is obtained after performing simple calculations. The calculation formula is as follows:

[0058] (3)

[0059] in, a corresponds to phase A, b corresponds to phase B, and c corresponds to phase C. This is the sign function for the initial duty cycle of phase A, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase B, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase C, with a positive value of 1 and a negative value of -1. The initial duty cycle of phase A. This is the initial duty cycle of phase B. This represents the initial duty cycle of phase C.

[0060] In the voltage equalization control stage of each voltage divider capacitor in the eight-level hybrid clamp converter topology, the target voltage is... With each voltage divider capacitor , , , , , ( , The voltage difference (which can be omitted) is then passed through a PI controller and multiplied by the current of each phase. , , The sign function is obtained , , , , , Then, with the updated duty cycle The final duty cycle is obtained after performing simple addition and subtraction calculations. Its formula is expressed as:

[0061] (4)

[0062] After voltage equalization is achieved through each voltage-dividing capacitor, the other capacitors... , , , , , It can also achieve self-equalizing pressure.

[0063] The pulse width modulation and pulse signal generation stages of an eight-level hybrid clamp converter topology follow the following operating rules: power devices... and , and , and , and , and , and , and , and , and , and Two complementary conductions, power devices and , and , and Synchronization, power devices , , , , , , Interleaved conduction, its carrier signal phase shift , It is determined by the number of devices that are interleaved in conduction.

[0064] Reference Figures 5 to 7 , Figure 5 The three-phase current waveform diagram of a six-level hybrid clamp converter topology at a voltage level of 10kV is provided for an embodiment of the present invention. Figure 6 The waveform diagram before three-phase line voltage filtering is provided for a 10kV voltage level using a six-level hybrid clamp converter topology; Figure 7 The voltage waveforms of each voltage divider capacitor in a six-level hybrid clamp converter topology at a voltage level of 10kV are shown in the embodiments of the present invention.

[0065] It should be noted that the control method in this embodiment corresponds to the aforementioned multi-level hybrid clamp converter topology. Therefore, any content not specifically described in the control method of this embodiment, including but not limited to functional definitions, working principles, and technical effects, can be referred to the description in the aforementioned control method, and will not be repeated here.

[0066] In summary, the multilevel converter topology and control method provided in this specific embodiment, through the combination of multilevel hybrid clamping power submodule and flying capacitor power submodule, achieves a simple topology with strong scalability, relatively few power devices, simple control method, easy voltage self-balancing of voltage dividers, and direct connection of medium and high voltage levels. It is highly likely to be widely promoted and applied in medium and high voltage distribution networks, energy storage converters, transformer interconnection, and flexible DC transmission, with a vast market potential, providing theoretical guidance for achieving efficient, green, and energy-saving conversion.

[0067] It should be understood that the above are merely illustrative examples and do not constitute any limitation on the technical solutions of the present invention. In specific applications, those skilled in the art can make settings as needed, and the present invention does not impose any restrictions on this.

[0068] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of this invention. In practical applications, those skilled in the art can select some or all of the workflow to achieve the purpose of this embodiment according to actual needs, and no restrictions are imposed here.

[0069] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0070] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory / random access memory, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0071] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A control method for a multilevel converter topology, characterized in that, This control method is applicable to multilevel converter topologies, including six-level hybrid clamp converter topologies and eight-level hybrid clamp converter topologies. Both the six-level and eight-level hybrid clamp converter topologies include two multilevel hybrid clamp power submodules and one multilevel flying capacitor power submodule. The two multilevel hybrid clamp power submodules are connected in series with a capacitor and then interconnected with the multilevel flying capacitor power submodule to achieve medium-to-high voltage output on the AC side. This multilevel converter topology is equipped with a corresponding control method, which includes a phase-locked loop (PLL) synchronization control loop, a power control loop, a total DC voltage equalization control loop between the upper and lower bridge arm power submodules, a voltage equalization control loop for each voltage divider capacitor, and a pulse width modulation and pulse signal generation loop. The total voltage of the hybrid clamp power submodule and the voltage divider capacitors are equalized based on the initial duty cycle output from the power control loop, superimposed with a zero-sequence component and a voltage equalization control component. The modulation signal output by the controller of each loop is compared with a phase-shifted carrier wave to complete the control of the power devices. Synchronization with the power grid and power command control are achieved through phase-locked synchronization control and power control. The controller output value is used as the initial duty cycle and superimposed with the zero-sequence current component to achieve total voltage balance between the upper and lower bridge arm hybrid clamping power submodules. The command difference signal of each voltage divider capacitor is passed through an independent controller and then the output signal is synchronously superimposed on the control signal to control each voltage divider capacitor. The duty cycle obtained by the power control and voltage equalization control loops is compared with multiple sets of phase-shifted carrier signals to control the entire multi-level hybrid clamp converter topology.

2. The control method for the multilevel converter topology according to claim 1, characterized in that, The six-level hybrid clamp converter topology is specifically composed of two three-level hybrid clamp power submodules and one three-level flying capacitor power submodule. The six-level hybrid clamp converter corresponds to phases A, B, and C of a three-phase converter, and phases A, B, and C have the same structure; specifically, phase A includes: an insulated-gate bipolar transistor. to Clamping diodes to ,capacitance to and AC filter inductor Among them, capacitors ,capacitance Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series, clamping diode. Anode and clamping diode After the cathode is connected, a capacitor is connected in parallel. Clamping diode Cathode and clamping diode The anodes are respectively connected to the insulated gate bipolar transistor. Insulated Gate Bipolar Transistor and insulated gate bipolar transistor Insulated Gate Bipolar Transistor Between these components, a three-level hybrid clamping power submodule is formed at the upper end; capacitor ,capacitance Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series, clamping diode. Anode and clamping diode After the cathode is connected, a capacitor is connected in parallel. Clamping diode Cathode and clamping diode The anodes are respectively connected to the insulated gate bipolar transistor. Insulated Gate Bipolar Transistor and insulated gate bipolar transistor Insulated Gate Bipolar Transistor Between these components, a three-level hybrid clamping power submodule is formed at the lower end; Insulated Gate Bipolar Transistor to Interconnected and insulated gate bipolar transistors to Interconnected in series, insulated gate bipolar transistor Emitter-gate bipolar transistor Parallel capacitor between collectors Insulated Gate Bipolar Transistor Emitter-gate bipolar transistor Parallel capacitor between collectors This forms a three-level flying capacitor power submodule; the corresponding three-level hybrid clamping power submodules located at the upper and lower ends are connected to the capacitor. After series connection, the output terminal is connected to the three-level flying capacitor power submodule, and the output point of the three-level flying capacitor power submodule is connected to the AC filter inductor. The connections form a six-level hybrid clamp converter topology.

3. The control method for a multilevel converter topology according to claim 1, characterized in that, The eight-level hybrid clamp converter topology is specifically composed of two four-level hybrid clamp power submodules and one four-level flying capacitor power submodule. The eight-level hybrid clamp converter corresponds to phases A, B, and C in a three-phase converter, and phases A, B, and C have the same structure; for phase A, it specifically includes: an insulated gate bipolar transistor. to Clamping diodes to ,capacitance to and AC filter inductor Among them, capacitors ,capacitance ,capacitance Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series; clamping diode Anode and clamping diode Cathode connection, clamping diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor collector connection; clamping diode Anode and clamping diode Cathode connection, clamping diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor collector connection; capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor collector connection, capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor The collector connections form the upper four-level hybrid clamp power submodule; capacitors To capacitor Insulated gate bipolar transistors connected in series and then in parallel Collector and insulated gate bipolar transistor Emitter, Insulated Gate Bipolar Transistor to The collector and emitter are connected in series; clamping diode Anode and clamping diode Cathode connection, clamping diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor collector connection; clamping diode Anode and clamping diode Cathode connection, clamping diode Cathode and Insulated Gate Bipolar Transistor collector connection, clamping diode Anode and Insulated Gate Bipolar Transistor collector connection; capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor collector connection, capacitor The two ends are respectively connected to an insulated gate bipolar transistor. Insulated Gate Bipolar Transistor The collector connections form the lower four-level hybrid clamped power submodule; Insulated Gate Bipolar Transistor to Interconnected and insulated gate bipolar transistors to Interconnected in series, insulated gate bipolar transistor Emitter-gate bipolar transistor Parallel capacitor between collectors Insulated Gate Bipolar Transistor Emitter-gate bipolar transistor Parallel capacitor between collectors Insulated Gate Bipolar Transistor Emitter-gate bipolar transistor Parallel capacitor between collectors This forms a four-level flying capacitor power submodule; the four-level hybrid clamping power submodules located at the upper and lower ends are connected to the capacitor. After series connection, the output terminal is connected to the four-level flying capacitor power submodule, and the output point of the four-level flying capacitor power submodule is connected to the AC filter inductor. The connections form an eight-level hybrid clamp converter topology.

4. The control method for a multilevel converter topology according to claim 2, characterized in that, The overall DC voltage balancing control link between the multilevel hybrid clamping power submodules in the six-level hybrid clamping converter topology is to balance the capacitors... ,capacitance Total voltage With capacitor ,capacitance Total voltage After subtraction, the capacitance value of the DC capacitor is obtained. and control cycle Estimate the magnitude of the injected zero-sequence current component and then compare it with the initial duty cycle. The updated duty cycle is obtained after calculation. The corresponding calculation formula is: in: Representing phases A, B, and C, corresponding to , This is the sign function for the initial duty cycle of phase A, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase B, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase C, with a positive value of 1 and a negative value of -1. The initial duty cycle of phase A. This is the initial duty cycle of phase B. This represents the initial duty cycle of phase C.

5. The control method for a multilevel converter topology according to claim 4, characterized in that, The voltage equalization control loop of each voltage divider capacitor in the six-level hybrid clamp converter topology is to equalize the target voltage. With each voltage divider capacitor ,capacitance ,capacitance and capacitor The voltage difference is then passed through a PI controller and multiplied by the phase current. , , The sign function is obtained , , and Then, with the updated duty cycle The final duty cycle is obtained after performing addition and subtraction calculations. The corresponding formula is expressed as: After voltage equalization through each voltage-dividing capacitor, the other capacitors... to It also performs self-equalization.

6. The control method for a multilevel converter topology according to claim 5, characterized in that, The pulse width modulation and pulse signal generation stages of a six-level hybrid clamp converter topology follow the following operating rules: Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Two complementary conductions, insulated gate bipolar transistor and Insulated Gate Bipolar Transistor and Synchronous, Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor Insulated Gate Bipolar Transistor to Interleaved conduction, its carrier signal phase shift , The number of devices is determined based on interleaved conduction.

7. The control method for a multilevel converter topology according to claim 3, characterized in that, The overall DC voltage balancing control link between the multilevel hybrid clamp power submodules in the eight-level hybrid clamp converter topology is to balance the capacitors... to Total voltage With capacitor to Total voltage After subtraction, the capacitance value of the DC capacitor is obtained. and control cycle Estimate the magnitude of the injected zero-sequence current component and then compare it with the initial duty cycle. The updated duty cycle is obtained after calculation. The corresponding calculation formula is: in: Representing phases A, B, and C, corresponding to , This is the sign function for the initial duty cycle of phase A, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase B, with a positive value of 1 and a negative value of -1. This is the sign function for the initial duty cycle of phase C, with a positive value of 1 and a negative value of -1. The initial duty cycle of phase A. This is the initial duty cycle of phase B. This represents the initial duty cycle of phase C.

8. The control method for a multilevel converter topology according to claim 7, characterized in that, In the voltage equalization control stage of each voltage divider capacitor in the eight-level hybrid clamp converter topology, the target voltage is... With each voltage divider capacitor ,capacitance to and capacitors The voltage difference is then passed through a PI controller and multiplied by the phase current. , , The sign function is obtained , , , , and Then, with the updated duty cycle The final duty cycle is obtained after performing addition and subtraction calculations. The corresponding formula is expressed as: After voltage equalization through each voltage-dividing capacitor, the other capacitors... to and capacitors to It also performs self-equalization.

9. The control method for a multilevel converter topology according to claim 8, characterized in that, The pulse width modulation and pulse signal generation stages of an eight-level hybrid clamp converter topology follow the following operating rules: Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Two complementary conductions, insulated gate bipolar transistor and Insulated Gate Bipolar Transistor and Insulated Gate Bipolar Transistor and Synchronous, Insulated Gate Bipolar Transistor to Insulated Gate Bipolar Transistor to Interleaved conduction, its carrier signal phase shift , The number of devices is determined based on interleaved conduction.

Images