Amplification circuit
By combining common source and common gate connection with an auxiliary amplifier, and using an LC parallel resonant circuit to adjust the resonant frequency, the problem of existing amplifier circuits being unable to achieve high gain under low power consumption is solved, achieving a balance between high gain and low power consumption.
Patent Information
- Application Number
- CN202511009748.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-06
- Filing Date
- 2025-07-22
- Publication Date
- 2026-02-06
AI Technical Summary
Existing amplifier circuits struggle to achieve high gain while maintaining low power consumption. In particular, increasing current consumption or using multi-stage structures leads to increased power supply voltage and current, which fails to effectively improve gain.
By employing a common-source, common-gate amplification element and combining an auxiliary amplifier with an LC parallel resonant circuit, the resonant frequency is adjusted to increase the output resistance and reduce the impact of drain current amplitude on the gate-source voltage, thereby achieving high gain.
The gain of the amplifier circuit is significantly improved under low power consumption conditions, and the frequency characteristics are optimized by the frequency variability of the resonant circuit, achieving a balance between high gain and low power consumption.
Smart Images
Figure CN121485604A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to amplifier circuits. Background Technology
[0002] Patent document 1 discloses a low-noise amplifier circuit having two amplifying elements connected by a common source and a common gate.
[0003] Patent Document 1: Japanese Patent Publication No. 2008-512926
[0004] In the amplifier circuit disclosed in Patent Document 1, methods for further increasing gain include increasing the transconductance by increasing the current consumption (drain current or collector current) and increasing the output resistance by making the amplifying element a multi-stage structure with three or more stages. However, in the above methods, the current consumption or power supply voltage increases, making it impossible to achieve high gain while maintaining low power consumption. Summary of the Invention
[0005] Therefore, the present invention was made to solve the above-mentioned problems, and the object is to provide an amplifier circuit that can achieve high gain while maintaining power consumption.
[0006] To achieve the above objectives, one technical solution of the present invention includes an amplifier circuit comprising: a first input terminal and a first output terminal; a first amplifying element having a first control terminal, a first terminal, and a second terminal; a second amplifying element having a second control terminal, a third terminal, and a fourth terminal; a third amplifying element having a third control terminal, a fifth terminal, and a sixth terminal; and a first LC parallel resonant circuit and a second LC parallel resonant circuit, wherein the first control terminal is connected to the first input terminal, the first terminal is connected to the fourth terminal, the second terminal is grounded, the second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit, the third terminal is connected to the first output terminal and the first LC parallel resonant circuit, the third control terminal is connected to the fourth terminal, and the sixth terminal is grounded.
[0007] According to the present invention, an amplifier circuit can be provided that achieves high gain while maintaining low power consumption. Attached Figure Description
[0008] Figure 1 This is a circuit structure diagram of the amplifier circuit involved in the implementation method.
[0009] Figure 2A This is the circuit diagram of the amplifier circuit involved in the comparative example.
[0010] Figure 2B This is a graph showing the current / voltage characteristics of the amplification element involved in the implementation and comparative examples.
[0011] Figure 3 This is a circuit diagram of the amplifier circuit involved in the modified example 1 of the implementation method.
[0012] Figure 4A This is a circuit state diagram of the amplifier circuit at high gain according to the modified example 1 of the implementation method.
[0013] Figure 4B This is a circuit state diagram of the amplifier circuit at low gain according to the modified example 1 of the implementation method.
[0014] Figure 5 This is a circuit diagram of the amplifier circuit involved in the modified example 2 of the implementation method.
[0015] Figure 6 This is a circuit diagram of the amplifier circuit involved in variation 3 of the implementation method.
[0016] Figure 7 This is a circuit diagram of the amplifier circuit involved in variation 4 of the implementation method.
[0017] Figure 8A This is a circuit state diagram of the amplifier circuit involved in the modified example 4 of the implementation method when the first amplifier is in operation.
[0018] Figure 8B This is a circuit state diagram of the second amplifier of the amplifier circuit involved in the modified example 4 of the implementation method when it is in operation.
[0019] Explanation of reference numerals in the attached figures
[0020] 1, 2, 3, 4, 5, 500… amplifier circuits; 10, 10A, 10B, 10C… amplifiers; 11, 11B, 11C, 12, 12B, 12C, 31, 31B, 32… FETs; 20, 20B, 20C, 40, 520… LC parallel resonant circuits; 21, 21B, 21C, 41… variable inductors; 22, 22B, 22C, 42… variable... Containers; 23, 23B, 23C, 24, 24B, 24C, 27, 27C… Capacitors; 25, 25B, 25C… Inductors; 26, 26C… Resistor elements; 30, 30A… Auxiliary amplifiers; 51, 52, 53, 54, 55, 56, 57… Switches; 101, 103… Input terminals; 102, 104… Output terminals; 105, 106… Bias terminals. Detailed Implementation
[0021] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments described below are either general or specific examples. The numerical values, shapes, materials, constituent elements, arrangements of constituent elements, and connection methods shown in the following embodiments are examples and are not intended to limit the scope of the invention.
[0022] Furthermore, the figures are schematic diagrams that have been appropriately emphasized, omitted, or proportionally adjusted for the purpose of illustrating the invention, and are not necessarily strictly illustrative, sometimes differing from the actual shapes, positional relationships, and proportions. In the figures, substantially identical structures are labeled with the same reference numerals, and sometimes repeated descriptions are omitted or simplified.
[0023] In the circuit structure disclosed herein, "connection" includes not only direct connection via connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Connection between A and B" means connection between A and B and between A and B.
[0024] In addition, in this disclosure, "path" means a transmission line consisting of wiring for high-frequency signal transmission, electrodes directly connected to the wiring, and terminals directly connected to the wiring or the electrodes.
[0025] Furthermore, in this disclosure, "component A is connected in series in path B" means that both the signal input terminal and the signal output terminal of component A are connected to the wiring, electrodes, or terminals constituting path B.
[0026] In this invention, "terminal," "input terminal," and "output terminal" mean the point where the conductor within an element ends. Furthermore, when the impedance of the conductors between elements is sufficiently low, a terminal is interpreted not only as a single point but also as any point on the conductors between elements or the entire conductor.
[0027] (Implementation Method)
[0028] [Circuit structure of amplifier circuit 1]
[0029] While referring to Figure 1 The circuit structure of the amplifier circuit 1 involved in this embodiment will be described. Figure 1 This is a circuit diagram of the amplifier circuit 1 according to the embodiment. As shown in the figure, the amplifier circuit 1 includes an amplifier 10 and an auxiliary amplifier 30. The amplifier 10 includes an input terminal 101, an output terminal 102, FETs 11 and 12, an LC parallel resonant circuit 20, capacitors 23 and 24, and an inductor 25. The auxiliary amplifier 30 includes a FET 31 and an LC parallel resonant circuit 40.
[0030] Input terminal 101 is an example of a first input terminal, used for inputting high-frequency signals. Output terminal 102 is an example of a first output terminal, used for outputting high-frequency signals.
[0031] FET11 is an example of a first amplifying element; it is an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a gate terminal g1 (first control terminal), a drain terminal d1 (first terminal), and a source terminal s1 (second terminal). FET12 is an example of a second amplifying element; it is an n-channel MOSFET with a gate terminal g2 (second control terminal), a drain terminal d2 (third terminal), and a source terminal s2 (fourth terminal). FET31 is an example of a third amplifying element; it is an n-channel MOSFET with a gate terminal g3 (third control terminal), a drain terminal d3 (fifth terminal), and a source terminal s3 (sixth terminal).
[0032] Furthermore, FETs 11, 12, and 31 can each be a p-channel MOSFET or other types of FETs. When FETs 11, 12, and 31 are p-channel MOSFETs, the drain and source terminals are configured in opposite directions. Alternatively, FETs 11, 12, and 31 can each be a bipolar transistor. When FETs 11, 12, and 31 are bipolar transistors, the gate terminal of the FET is the base terminal, the drain terminal is the collector terminal, and the source terminal is the emitter terminal.
[0033] LC parallel resonant circuit 20 is an example of a first LC parallel resonant circuit, having a structure in which a variable inductor 21 and a variable capacitor 22 are connected in parallel. The resonant frequency of LC parallel resonant circuit 20 is variable according to the frequency of the high-frequency signal input to input terminal 101. LC parallel resonant circuit 40 is an example of a second LC parallel resonant circuit, having a structure in which a variable inductor 41 and a variable capacitor 42 are connected in parallel. The resonant frequency of LC parallel resonant circuit 40 is variable according to the frequency of the high-frequency signal input to input terminal 101. Furthermore, LC parallel resonant circuits 20 and 40 may also not have the function of changing the resonant frequency.
[0034] Gate terminal g1 is connected to input terminal 101 via capacitor 23. Drain terminal d1 is connected to source terminal s2. Source terminal s1 is grounded via inductor 25. Gate terminal g2 is connected to drain terminal d3 and LC parallel resonant circuit 40. Drain terminal d2 is connected to output terminal 102 via capacitor 24, and also to LC parallel resonant circuit 20. Gate terminal g3 is connected to source terminal s2. Source terminal s3 is grounded.
[0035] According to the above connection structure, FET11 and FET12 are connected in a common source and common gate configuration, so amplifier circuit 1 can function as an amplifier circuit with high gain.
[0036] Here, for comparison, a conventional common-source cascode amplifier circuit is illustrated. Figure 2A This is a circuit diagram of the amplifier circuit 500 involved in the comparative example. As shown in the figure, the amplifier circuit 500 involved in the comparative example is a conventional common-source common-gate type amplifier circuit, including an input terminal 101, an output terminal 102, a bias terminal 105, FETs 11 and 12, an LC parallel resonant circuit 520, capacitors 23, 24 and 27, an inductor 25, and a resistor element 26. The amplifier circuit 500 involved in the comparative example differs structurally from the amplifier circuit 1 involved in the embodiment in that it does not include an auxiliary amplifier 30.
[0037] FETs 11 and 12 are interconnected via a common source and common gate configuration. Generally, in low-noise amplifier circuits, a common source and common gate configuration is used to achieve high gain. In amplifier circuit 500, the gain A is defined by Equation 1.
[0038] A = gm1 × Rout (Equation 1)
[0039] gm1 is the transconductance of FET11, and Rout is the output resistance, as expressed by Equation 2.
[0040] Rout=r_up / / r_down=r_up×r_down / (r_up+r_down)(Formula 2)
[0041] r_up is the impedance observed from the drain terminal of FET12 on the power supply side, and r_down is the impedance observed from the drain terminal of FET12 on the ground side. That is, the output resistance Rout is the parallel impedance of r_up and r_down.
[0042] According to Equation 1, in order to increase the gain A, the following are listed:
[0043] (1) Increase the drain current (drain current Id) and thus increase gm1
[0044] (2) Make the FET a multi-stage structure with more than 3 stages and increase the output resistance Rout, etc.
[0045] However, in the method described in (1) above, the current consumption increases. Furthermore, if gm1 is saturated, the gain will not increase even if the current is further increased. Additionally, in the method described in (2) above, low power supply voltage circuits cannot be used if it is a multi-stage structure. That is, it is difficult to achieve gain while consuming less power using the methods described in (1) and (2) above.
[0046] In contrast, in the amplifier circuit 1 of this embodiment, the output resistance Rout can be increased without increasing power consumption. Regarding r_up, the resonant frequency of the LC parallel resonant circuit 20 is adjusted to achieve high impedance at the frequency of a high-frequency signal. On the other hand, regarding r_down, by configuring the auxiliary amplifier 30, the potential amplitude at point X (the connection point of the drain terminal d1 of FET11 and the source terminal s2 of FET12) is reduced, thereby achieving high impedance.
[0047] In the amplifier circuit 500 of the comparative example, the potential Vg2 of the gate terminal of FET12 is fixed by the supply of a bias potential from the bias terminal 105. Therefore, in order to allow the drain current Id to flow at a high frequency, the gate-source voltage Vgs2 of FET12 varies. If the potential at point X is set to Vx, then the gate-source voltage Vgs2 is (Vg2 - Vx), and therefore Vx also varies correspondingly to the amplitude of the drain current Id.
[0048] In contrast, in the amplifier circuit 1 of this embodiment, the potential Vg2 of the gate terminal g2 of FET12 is connected to the drain terminal d3 of the auxiliary amplifier 30, and therefore varies in response to the amplitude of the drain current Id. Therefore, the gate-source voltage Vgs2 is (Vg2-Vx), and thus Vx is fixed in response to the amplitude of the drain current Id.
[0049] Figure 2B This is a graph showing the current / voltage characteristics of the FET12 according to the embodiments and comparative examples. In the amplifier circuit 500 according to the comparative example, Vx varies greatly, so the drain current Id increases or decreases in amplitude according to the change in the drain-source voltage Vds of the FET12. In contrast, in the amplifier circuit 1 according to the embodiment, Vx varies little, so the drain-source voltage Vds of the FET12 does not change, and the drain current Id increases or decreases in amplitude depending on the gate-source voltage Vgs. In this case, the drain current Id does not change due to the change in the drain-source voltage Vds. This is equivalent to the case where the drain-source resistance of the FET12 is very large. As a result, r_down can be increased. That is, in the amplifier circuit 1 according to the embodiment, by allowing a small current to flow through the auxiliary amplifier 30, the output resistance Rout can be increased significantly, and the gain A can be increased. As a result, an amplifier circuit 1 can be provided that achieves high gain while maintaining low power consumption.
[0050] [Circuit structure of amplifier circuit 2 involved in variation 1]
[0051] Figure 3This is a circuit diagram of the amplifier circuit 2 according to Modification 1 of the embodiment. As shown in the diagram, the amplifier circuit 2 according to this modification includes an amplifier 10A, an auxiliary amplifier 30, and switches 51 and 52. The amplifier circuit 2 according to this modification differs from the amplifier circuit 1 according to the embodiment in the structure of the auxiliary amplifier 10A and the switches 51 and 52. Therefore, in the following description of the amplifier circuit 2 according to this modification, the description of the same structure as the amplifier circuit 1 according to the embodiment will be omitted, and the description will focus on the different structures.
[0052] Amplifier 10A includes input terminal 101, output terminal 102, FETs 11 and 12, LC parallel resonant circuit 20, capacitors 23, 24 and 27, inductor 25, resistive element 26, and switch 53.
[0053] Switch 53 is connected between gate terminal g2, capacitor 27, and resistor 26. Capacitor 27 is connected between switch 53 and ground, functioning as the gate ground capacitance of FET 12. Resistor 26 is connected between switch 53 and bias terminal 105.
[0054] Switch 52 is an example of the first switch, connected between the source terminal s2 and the gate terminal g3, switching the connection and disconnection of the source terminal s2 and the gate terminal g3. Switch 51 is an example of the second switch, connected between the gate terminal g2 and the drain terminal d3, switching the connection and disconnection of the gate terminal g2 and the drain terminal d3.
[0055] Figure 4A This is a circuit state diagram of the amplifier circuit 2 in high gain mode according to Modification 1 of the embodiment. When the amplifier circuit 2 requires a gain higher than a specified value, switches 51 and 52 are turned on. In addition, switch 53 is turned off. Thus, with the auxiliary amplifier 30 connected to the amplifier 10A, the amplifier circuit 2 can amplify the high-frequency signal input to the input terminal 101 with high gain while maintaining low power consumption.
[0056] Figure 4B This is a circuit diagram of the amplifier circuit 2 in low-gain mode according to Variation 1 of the embodiment. When the amplifier circuit 2 requires a gain below a specified value, switches 51 and 52 are in a non-conducting state. Additionally, switch 53 is in a conducting state. Therefore, the auxiliary amplifier 30 is not connected to the amplifier 10A, the gate terminal g2 is grounded at high frequency, a bias voltage is supplied to the gate terminal g2 from the bias terminal 105, and the amplifier circuit 2 can amplify the high-frequency signal input to the input terminal 101 at low gain.
[0057] Therefore, the amplifier circuit 2 can appropriately select between a low-gain mode and a high-gain mode with low power consumption by controlling switches 51 to 53.
[0058] [Circuit structure of amplifier circuit 3 involved in variation 2]
[0059] Figure 5 This is a circuit diagram of the amplifier circuit 3 according to Modification 2 of the embodiment. As shown in the figure, the amplifier circuit 3 according to this modification includes an amplifier 10A, an auxiliary amplifier 30A, and switches 51, 52, and 54. The amplifier circuit 3 according to this modification differs from the amplifier circuit 2 according to Modification 1 in the structure of the auxiliary amplifier 30A and the addition of the switch 54. Therefore, in the following description of the amplifier circuit 3 according to this modification, the description of the same structure as the amplifier circuit 2 according to Modification 1 will be omitted, and the description will focus on the different structures.
[0060] The auxiliary amplifier 30A includes FETs 31 and 32, and an LC parallel resonant circuit 40.
[0061] FET32 is an example of the fourth amplification element. It is an n-channel MOSFET with a gate terminal g4 (fourth control terminal), a drain terminal d4 (seventh terminal), and a source terminal s4 (eighth terminal).
[0062] In addition, FET32 can also be a p-channel MOSFET or other types of FETs. When FET32 is a p-channel MOSFET, the drain terminal is configured opposite to the source terminal. Alternatively, FET32 can also be a bipolar transistor. When FET32 is a bipolar transistor, the gate terminal of FET32 is the base terminal, the drain terminal of FET32 is the collector terminal, and the source terminal of FET32 is the emitter terminal.
[0063] FET32 is connected between drain terminal d3 and LC parallel resonant circuit 40. Gate terminal g4 is connected to bias terminal 105 via switch 54. Drain terminal d4 is connected to LC parallel resonant circuit 40. Source terminal s4 is connected to drain terminal d3. Gate terminal g2 is connected to drain terminal d3 via drain terminal d4 and source terminal s4. Gate terminal g3 is connected to source terminal s2 via switch 52. Source terminal s3 is grounded.
[0064] Based on the above connection structure, FET31 and FET32 are connected via a common source and common gate configuration, providing an amplifier circuit 3 with lower current consumption and higher gain. Furthermore, by suppressing the Miller effect in the auxiliary amplifier 30A, the reverse isolation can be improved, thus enhancing the K value.
[0065] [4. Circuit structure of amplifier circuit 4 involved in variation 3]
[0066] Figure 6 This is a circuit diagram of the amplifier circuit 4 according to Embodiment 3. As shown in the diagram, the amplifier circuit 4 according to this embodiment includes amplifiers 10 and 10B, and FETs 31 and 31B. The amplifier circuit 4 according to this embodiment differs from the amplifier circuit 1 according to Embodiment 1 in that it includes two amplifiers 10 and 10B, uses part of amplifier 10B as an auxiliary amplifier of amplifier 10, and uses part of amplifier 10 as an auxiliary amplifier of amplifier 10B. Therefore, in the following description of the amplifier circuit 4 according to this embodiment, the same structure as the amplifier circuit 1 according to Embodiment 1 will be omitted, and the description will focus on the different structures.
[0067] Amplifier 10 includes input terminal 101, output terminal 102, FETs 11 and 12, LC parallel resonant circuit 20, capacitors 23 and 24, and inductor 25. Amplifier 10 has the same structure as amplifier 10 of amplifier circuit 1 according to the embodiment.
[0068] Amplifier 10B includes input terminal 103, output terminal 104, FETs 11B and 12B, LC parallel resonant circuit 20B, capacitors 23B and 24B, and inductor 25B.
[0069] Input terminal 103 is an example of a second input terminal, used for inputting high-frequency signals. Output terminal 104 is an example of a second output terminal, used for outputting high-frequency signals.
[0070] FET11B is an example of a fifth amplifying element; it is an n-channel MOSFET with a gate terminal g5 (fifth control terminal), a drain terminal d5 (ninth terminal), and a source terminal s5 (tenth terminal). FET12B is an example of a sixth amplifying element; it is an n-channel MOSFET with a gate terminal g6 (sixth control terminal), a drain terminal d6 (eleventh terminal), and a source terminal s6 (twelfth terminal).
[0071] Furthermore, FET11B and 12B can each be a p-channel MOSFET or other types of FETs. When FET11B and 12B are p-channel MOSFETs, the drain and source terminals are configured in opposite directions. Alternatively, FET11B and 12B can each be a bipolar transistor. When FET11B and 12B are bipolar transistors, the gate terminal of the FET is the base terminal, the drain terminal is the collector terminal, and the source terminal is the emitter terminal.
[0072] The LC parallel resonant circuit 20B is an example of a second LC parallel resonant circuit, having a structure in which a variable inductor 21B and a variable capacitor 22B are connected in parallel. The resonant frequency of the LC parallel resonant circuit 20B varies according to the frequency of the high-frequency signal input to the input terminal 103. Alternatively, the LC parallel resonant circuit 20B may not have the function of changing the resonant frequency.
[0073] Gate terminal g1 is connected to input terminal 101 via capacitor 23. Drain terminal d1 is connected to source terminal s2. Source terminal s1 is grounded via inductor 25. Gate terminal g2 is connected to drain terminal d6 and LC parallel resonant circuit 20B. Drain terminal d2 is connected to output terminal 102 via capacitor 24, and also to LC parallel resonant circuit 20.
[0074] Gate terminal g5 is connected to input terminal 103 via capacitor 23B. Drain terminal d5 is connected to source terminal s6. Source terminal s5 is grounded via inductor 25B. Gate terminal g6 is connected to drain terminal d2 and LC parallel resonant circuit 20. Drain terminal d6 is connected to output terminal 104 via capacitor 24B, and also to LC parallel resonant circuit 20B.
[0075] FET31 is an example of a third amplifying element; it is an n-channel MOSFET with a gate terminal g3 (third control terminal), a drain terminal d3 (fifth terminal), and a source terminal s3 (sixth terminal). FET31B is an example of a seventh amplifying element; it is an n-channel MOSFET with a gate terminal g7 (seventh control terminal), a drain terminal d7 (thirteenth terminal), and a source terminal s7 (fourteenth terminal).
[0076] Gate terminal g3 is connected to source terminal s2. Drain terminal d3 is connected to gate terminal g2 and LC parallel resonant circuit 20B. Source terminal s3 is grounded. Gate terminal g7 is connected to source terminal s6. Drain terminal d7 is connected to gate terminal g6 and LC parallel resonant circuit 20. Source terminal s7 is grounded.
[0077] According to the above connection structure, FET11 and FET12 are connected in a common source and common gate configuration, and FET11B and FET12B are connected in a common source and common gate configuration.
[0078] In the above circuit structure, for example, when a high-frequency signal is input from input terminal 101, amplified by amplifier 10, and output from output terminal 102, FETs 11B, 12B, and 31B are in the off state, and FET 31 and the LC parallel resonant circuit 20B function as auxiliary amplifiers for amplifier 10. Alternatively, for example, when a high-frequency signal is input from input terminal 103, amplified by amplifier 10B, and output from output terminal 104, FETs 11, 12, and 31 are in the off state, and FET 31B and the LC parallel resonant circuit 20 function as auxiliary amplifiers for amplifier 10B.
[0079] Therefore, it is possible to use it as an auxiliary amplifier as part of an amplifier in the off-state (LC parallel resonant circuit). Thus, an amplifier circuit 4 can be provided that achieves high gain and area saving while maintaining low power consumption.
[0080] [Circuit structure of amplifier circuit 5 involved in variation 4]
[0081] Figure 7 This is a circuit diagram of the amplifier circuit 5 according to Embodiment 4. As shown in the diagram, the amplifier circuit 5 according to this embodiment includes amplifiers 10A and 10C, FETs 31 and 31B, and switches 51, 52, 55, and 56. The amplifier circuit 5 according to this embodiment differs from the amplifier circuit 3 according to Embodiment 2 in that it includes two amplifiers 10A and 10C, uses amplifier 10C as an auxiliary amplifier for amplifier 10A, and uses amplifier 10A as an auxiliary amplifier for amplifier 10C. Therefore, in the following description of the amplifier circuit 5 according to this embodiment, the description of the same structure as the amplifier circuit 3 according to Embodiment 2 will be omitted, and the description will focus on the different structures.
[0082] Amplifier 10A includes input terminal 101, output terminal 102, FETs 11 and 12, LC parallel resonant circuit 20, capacitors 23, 24 and 27, inductor 25, resistive element 26, and switch 53. Amplifier 10A has the same structure as amplifier 10A in amplifier circuit 2 according to Modified Example 1 and amplifier 10A in amplifier circuit 3 according to Modified Example 2.
[0083] Amplifier 10C includes input terminal 103, output terminal 104, FETs 11C and 12C, LC parallel resonant circuit 20C, capacitors 23C, 24C and 27C, inductor 25C, resistor element 26C, and switch 57.
[0084] Input terminal 103 is an example of a second input terminal, used for inputting high-frequency signals. Output terminal 104 is an example of a second output terminal, used for outputting high-frequency signals.
[0085] FET11C is an example of a fifth amplifying element; it is an n-channel MOSFET with a gate terminal g5 (fifth control terminal), a drain terminal d5 (ninth terminal), and a source terminal s5 (tenth terminal). FET12C is an example of a sixth amplifying element; it is an n-channel MOSFET with a gate terminal g6 (sixth control terminal), a drain terminal d6 (eleventh terminal), and a source terminal s6 (twelfth terminal).
[0086] Furthermore, FET11C and FET12C can each be a p-channel MOSFET or other types of FETs. When FET11C and FET12C are p-channel MOSFETs, the drain and source terminals are configured in opposite directions. Alternatively, FET11C and FET12C can each be a bipolar transistor. When FET11C and FET12C are bipolar transistors, the gate terminal of the FET is the base terminal, the drain terminal of the FET is the collector terminal, and the source terminal of the FET is the emitter terminal.
[0087] The LC parallel resonant circuit 20C is an example of a second LC parallel resonant circuit, having a structure in which a variable inductor 21C and a variable capacitor 22C are connected in parallel. The resonant frequency of the LC parallel resonant circuit 20C varies according to the frequency of the high-frequency signal input to the input terminal 103. Alternatively, the LC parallel resonant circuit 20C may not have the function of changing the resonant frequency.
[0088] Switch 53 is connected between gate terminal g2, capacitor 27, and resistor 26. Capacitor 27 is connected between switch 53 and ground, functioning as the gate ground capacitance of FET 12. Resistor 26 is connected between switch 53 and bias terminal 105.
[0089] Switch 57 is connected between gate terminal g6, capacitor 27C, and resistor 26C. Capacitor 27C is connected between switch 57 and ground, functioning as the gate ground capacitance of FET 12C. Resistor 26C is connected between switch 57 and bias terminal 106.
[0090] Switch 52 is an example of the third switch, connected between the source terminal s2 and the gate terminal g3, switching the connection and disconnection of the source terminal s2 and the gate terminal g3. Switch 51 is an example of the fourth switch, connected between the gate terminal g2 and the drain terminal d3, switching the connection and disconnection of the gate terminal g2 and the drain terminal d3. Switch 56 is an example of the fifth switch, connected between the source terminal s6 and the gate terminal g7, switching the connection and disconnection of the source terminal s6 and the gate terminal g7. Switch 55 is an example of the sixth switch, connected between the gate terminal g6 and the drain terminal d2, switching the connection and disconnection of the gate terminal g6 and the drain terminal d2.
[0091] Gate terminal g1 is connected to input terminal 101 via capacitor 23. Drain terminal d1 is connected to source terminal s2. Source terminal s1 is grounded via inductor 25. Gate terminal g2 is connected to drain terminal d6 and LC parallel resonant circuit 20C via switch 51. Drain terminal d2 is connected to output terminal 102 via capacitor 24, and also to LC parallel resonant circuit 20.
[0092] Gate terminal g5 is connected to input terminal 103 via capacitor 23C. Drain terminal d5 is connected to source terminal s6. Source terminal s5 is grounded via inductor 25C. Gate terminal g6 is connected to drain terminal d2 and LC parallel resonant circuit 20 via switch 55. Drain terminal d6 is connected to output terminal 104 via capacitor 24C, and also to LC parallel resonant circuit 20C.
[0093] FET31 is an example of a third amplifying element; it is an n-channel MOSFET with a gate terminal g3 (third control terminal), a drain terminal d3 (fifth terminal), and a source terminal s3 (sixth terminal). FET31B is an example of a seventh amplifying element; it is an n-channel MOSFET with a gate terminal g7 (seventh control terminal), a drain terminal d7 (thirteenth terminal), and a source terminal s7 (fourteenth terminal).
[0094] Gate terminal g3 is connected to source terminal s2 via switch 52. Drain terminal d3 is connected to gate terminal g2 via switch 51, and also connected to the LC parallel resonant circuit 20C. Source terminal s3 is grounded. Gate terminal g7 is connected to source terminal s6 via switch 56. Drain terminal d7 is connected to gate terminal g6 via switch 55, and also connected to the LC parallel resonant circuit 20. Source terminal s7 is grounded.
[0095] According to the above connection structure, FET11 and FET12 are connected in a common source and common gate configuration, and FET11C and FET12C are connected in a common source and common gate configuration.
[0096] Figure 8A This is a circuit state diagram showing the amplifier 10A of the amplifier circuit 5 according to Modification 4 of the embodiment when it is operating. When the amplifier 10A amplifies at a gain higher than a predetermined value, switches 51 and 52 are turned on. Switch 53 is turned off. Switches 55 and 56 are also turned off. Therefore, FET 31 and the LC parallel resonant circuit 20C are connected to the amplifier 10A. That is, when the amplifier 10A amplifies at high gain, FET 31 and the LC parallel resonant circuit 20C function as an auxiliary amplifier for the amplifier 10A. Thus, the amplifier circuit 5 can amplify the high-frequency signal input to the input terminal 101 at high gain while maintaining low power consumption.
[0097] Furthermore, although not shown, when amplifier 10A operates with a gain below a specified value, switches 51 and 52 are in a non-conducting state. Switch 53 is in a conducting state. Therefore, the auxiliary amplifier is not connected to amplifier 10A, gate terminal g2 is grounded at high frequency, and a bias voltage is supplied to gate terminal g2 from bias terminal 105. Amplifier circuit 5 can then amplify the high-frequency signal input to input terminal 101 at low gain.
[0098] Figure 8B This is a circuit state diagram showing the amplifier 10C of the amplifier circuit 5 according to Variation Example 4 of the embodiment when it is operating. When the amplifier 10C amplifies at a gain higher than a predetermined value, switches 55 and 56 are turned on. Switch 57 is turned off. Switches 51 and 52 are also turned off. Thus, FET 31B and the LC parallel resonant circuit 20 are connected to the amplifier 10C. That is, when the amplifier 10C amplifies at high gain, FET 31B and the LC parallel resonant circuit 20 function as an auxiliary amplifier for the amplifier 10C. Therefore, the amplifier circuit 5 can amplify the high-frequency signal input to the input terminal 103 at high gain while maintaining low power consumption.
[0099] Additionally, although not shown, when amplifier 10C operates with a gain below a specified value, switches 55 and 56 are in a non-conducting state. Switch 57 is in a conducting state. Therefore, the auxiliary amplifier is not connected to amplifier 10C, gate terminal g6 is grounded at high frequency, and a bias voltage is supplied to gate terminal g6 from bias terminal 106. Amplifier circuit 5 can then amplify the high-frequency signal input to input terminal 103 at low gain.
[0100] Therefore, by controlling switches 51, 52, 53, 55, 56, and 57, amplifier circuit 5 can appropriately select between a low-gain mode and a high-gain mode with low power consumption. Furthermore, it can be used as an auxiliary amplifier as part of the amplifier in the off-state (LC parallel resonant circuit). Thus, an amplifier circuit 5 can be provided that achieves high gain and area savings while maintaining low power consumption.
[0101] [6 Effects, etc.]
[0102] As described above, the amplifier circuit 1 according to this embodiment includes: an input terminal 101 and an output terminal 102; a FET 11 having a gate terminal g1, a drain terminal d1, and a source terminal s1; a FET 12 having a gate terminal g2, a drain terminal d2, and a source terminal s2; a FET 31 having a gate terminal g3, a drain terminal d3, and a source terminal s3; and LC parallel resonant circuits 20 and 40. The gate terminal g1 is connected to the input terminal 101, the drain terminal d1 is connected to the source terminal s2, the source terminal s1 is grounded, the gate terminal g2 is connected to the drain terminal d3 and the LC parallel resonant circuit 40, the drain terminal d2 is connected to the output terminal 102 and the LC parallel resonant circuit 20, the gate terminal g3 is connected to the source terminal s2, and the source terminal s3 is grounded.
[0103] Therefore, the variation at point X (the connection point between drain terminal d1 and source terminal s2) is small, so the drain-source voltage Vds of FET12 remains constant, and the drain current Id fluctuates depending on the gate-source voltage Vgs. In this case, the drain current Id does not change due to variations in the drain-source voltage Vds, resulting in a very large drain-source resistance of FET12. That is, by allowing a small current to flow through the auxiliary amplifier 30, the output resistance Rout can be significantly increased, thereby improving the gain A. Thus, an amplifier circuit 1 can be provided that achieves high gain while maintaining low power consumption.
[0104] Additionally, for example in amplifier circuit 1, the LC parallel resonant circuits 20 and 40 have variable resonant frequencies depending on the frequency of the high-frequency signal input to input terminal 101.
[0105] This allows for increased gain at the desired frequency, and also allows for the release of unwanted frequency components to the power supply terminal side.
[0106] Additionally, for example, the amplifier circuit 2 involved in Modification 1 also includes: a switch 52 for switching the connection and disconnection of the source terminal s2 and the gate terminal g3; and a switch 51 for switching the connection and disconnection of the gate terminal g2 and the drain terminal d3.
[0107] Furthermore, for example, in amplifier circuit 2, when the gain of amplifier circuit 2 is higher than a specified value, switches 51 and 52 are turned on, and when the gain of amplifier circuit 2 is lower than the specified value, switches 51 and 52 are turned off.
[0108] Therefore, by switching switches 51 and 52 on and off, amplifier circuit 2 can appropriately select between low-gain mode and high-gain mode with low power consumption.
[0109] Additionally, for example, the amplifier circuit 2 also includes: a resistive element 26 connected between the gate terminal g2 and the bias terminal 105; and a capacitor 27 connected between the gate terminal g2 and ground.
[0110] Therefore, it is possible to select a high-gain mode where the gate terminal g2 is connected to the auxiliary amplifier 30, and a low-gain mode where the gate terminal g2 is connected to the bias terminal 105.
[0111] Additionally, for example in amplifier circuits 1 and 2, FETs 11 and 12 are connected in a common-source, common-gate configuration.
[0112] Therefore, amplifier circuits 1 and 2 capable of high-gain operation can be provided.
[0113] Additionally, for example, the amplifier circuit 3 involved in Modification 2 also includes a FET 32 having a gate terminal g4, a drain terminal d4, and a source terminal s4. The FET 32 is connected between the drain terminal d3 and the LC parallel resonant circuit 40. The gate terminal g4 is connected to the bias terminal 105, the drain terminal d4 is connected to the LC parallel resonant circuit 40, the source terminal s4 is connected to the drain terminal d3, and the gate terminal g2 is connected to the drain terminal d3 via the drain terminal d4 and the source terminal s4.
[0114] Therefore, by suppressing the Miller effect, the reverse isolation can be improved, which can improve the K value.
[0115] Additionally, for example, in amplifier circuit 3, FETs 31 and 32 are connected in a common-source, common-gate configuration.
[0116] Therefore, an amplifier circuit 3 with lower current consumption and higher gain can be provided.
[0117] Additionally, for example, the amplifier circuit 4 involved in Modification 3 further includes: an input terminal 103 and an output terminal 104; a FET 11B having a gate terminal g5, a drain terminal d5, and a source terminal s5; a FET 12B having a gate terminal g6, a drain terminal d6, and a source terminal s6; and a FET 31B having a gate terminal g7, a drain terminal d7, and a source terminal s7, wherein the gate terminal g1 is connected to the input terminal 101, the gate terminal g5 is connected to the input terminal 103, the drain terminal d1 is connected to the source terminal s2, and the drain terminal g5 is connected to the source terminal s6. Terminal d5 is connected to source terminal s6, source terminals s1 and s5 are grounded, gate g2 is connected to drain terminal d3 and LC parallel resonant circuit 20B, gate terminal g6 is connected to drain terminal d7 and LC parallel resonant circuit 20, drain terminal d2 is connected to output terminal 102 and LC parallel resonant circuit 20, drain terminal d6 is connected to output terminal 104 and LC parallel resonant circuit 20B, gate terminal g3 is connected to source terminal s2, gate terminal g7 is connected to source terminal s6, and source terminals s3 and s7 are grounded.
[0118] Therefore, it is possible to use it as an auxiliary amplifier as part of an amplifier in the off-state (LC parallel resonant circuit). Thus, an amplifier circuit 4 can be provided that achieves high gain and area saving while maintaining low power consumption.
[0119] Additionally, for example, the amplifier circuit 5 involved in Modification 4 further includes: a switch 52 for switching the connection and disconnection of the source terminal s2 and the gate terminal g3; a switch 51 for switching the connection and disconnection of the gate terminal g2 and the drain terminal d3; a switch 56 for switching the connection and disconnection of the source terminal s6 and the gate terminal g7; and a switch 55 for switching the connection and disconnection of the gate terminal g6 and the drain terminal d7.
[0120] Additionally, for example, in amplifier circuit 5, when FETs 11 and 12 are amplified with a gain higher than a specified value, switches 51 and 52 are turned on, and switches 55 and 56 are turned off. When FETs 11C and 12C are amplified with a gain higher than a specified value, switches 51 and 52 are turned off, and switches 55 and 56 are turned on.
[0121] Therefore, by controlling switches 51, 52, 55, and 56, amplifier circuit 5 can appropriately select between a low-gain mode and a high-gain mode with low power consumption. Furthermore, it can be used as an auxiliary amplifier (LC parallel resonant circuit) as part of the amplifier in the off-state. Thus, an amplifier circuit 5 can be provided that achieves high gain and area saving while maintaining low power consumption.
[0122] Additionally, for example, in amplifier circuit 4, FETs 11B and 12B are connected in a common-source, common-gate configuration. Also, for example, in amplifier circuit 5, FETs 11C and 12C are connected in a common-source, common-gate configuration.
[0123] Therefore, amplifier circuits 4 and 5 are provided that can perform high-gain operation.
[0124] (Other implementation methods)
[0125] The above description is based on the amplifier circuit, embodiments, and modifications related to the present invention. However, the amplifier circuit related to the present invention is not limited to the above embodiments and modifications. Other embodiments implemented by combining any of the constituent elements in the above embodiments and modifications, modifications obtained by implementing the above embodiments and modifications in accordance with the spirit of the present invention, and various machines that incorporate the above amplifier circuit are also included in the present invention.
[0126] For example, in the circuit structure of the amplifier circuit involved in the above embodiments and variations, other circuit elements and wiring are inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings.
[0127] The following describes the features of the amplifier circuit based on the above embodiments and variations.
[0128] <1>
[0129] An amplifier circuit, wherein:
[0130] First input terminal and first output terminal;
[0131] The first amplifying element has a first control terminal, a first terminal, and a second terminal;
[0132] The second amplifying element has a second control terminal, a third terminal, and a fourth terminal;
[0133] The third amplifying element has a third control terminal, a fifth terminal, and a sixth terminal; and
[0134] The first LC parallel resonant circuit and the second LC parallel resonant circuit
[0135] The aforementioned first control terminal is connected to the aforementioned first input terminal.
[0136] The first terminal is connected to the fourth terminal.
[0137] The aforementioned second terminal is grounded.
[0138] The second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit.
[0139] The third terminal is connected to the first output terminal and the first LC parallel resonant circuit.
[0140] The third control terminal is connected to the fourth terminal.
[0141] The sixth terminal mentioned above is grounded.
[0142] <2>
[0143] According to the amplifier circuit described in <1>, where,
[0144] The resonant frequencies of the first LC parallel resonant circuit and the second LC parallel resonant circuit can be varied according to the frequency of the high-frequency signal input to the first input terminal.
[0145] <3>
[0146] According to the amplifier circuit described in <1> or <2>, it also includes:
[0147] The first switch switches the connection and disconnection of the aforementioned fourth terminal and the aforementioned third control terminal; and
[0148] The second switch switches the connection between the second control terminal and the fifth terminal and the connection from non-connection.
[0149] <4>
[0150] According to the amplifier circuit described in <3>, where,
[0151] When the gain of the aforementioned amplifier circuit is higher than the specified value, both the first switch and the second switch become in the ON state.
[0152] When the gain of the aforementioned amplifier circuit is below a specified value, the first switch and the second switch become non-conducting.
[0153] <5>
[0154] According to any one of <1> to <4>, the amplifier circuit also includes:
[0155] A resistive element is connected between the second control terminal and the bias terminal; and
[0156] A capacitor is connected between the second control terminal and the ground wire.
[0157] <6>
[0158] According to the amplifier circuit described in any one of <1> to <4>, where,
[0159] The first amplifying element and the second amplifying element are connected in a common source, common gate configuration.
[0160] <7>
[0161] According to the amplifier circuit described in any one of <1> to <6>, where,
[0162] It also includes a fourth amplifying element, which has a fourth control terminal, a seventh terminal, and an eighth terminal.
[0163] The fourth amplifying element is connected between the fifth terminal and the second LC parallel resonant circuit.
[0164] The aforementioned fourth control terminal is connected to the bias terminal.
[0165] The seventh terminal is connected to the second LC parallel resonant circuit.
[0166] The eighth terminal is connected to the fifth terminal.
[0167] The second control terminal is connected to the fifth terminal via the seventh terminal and the eighth terminal.
[0168] <8>
[0169] According to the amplifier circuit described in <7>, in which,
[0170] The third and fourth amplifying elements are connected in a common source, common gate configuration.
[0171] <9>
[0172] According to the amplifier circuit described in <1> or <2>, it also includes:
[0173] The second input terminal and the second output terminal;
[0174] The fifth amplifying element has a fifth control terminal, a ninth terminal, and a tenth terminal;
[0175] The sixth amplifying element has a sixth control terminal, an eleventh terminal, and a twelfth terminal; and
[0176] The seventh amplifying element has a seventh control terminal, a thirteenth terminal, and a fourteenth terminal.
[0177] The aforementioned first control terminal is connected to the aforementioned first input terminal.
[0178] The fifth control terminal is connected to the second input terminal.
[0179] The first terminal is connected to the fourth terminal.
[0180] The ninth terminal is connected to the twelfth terminal.
[0181] The aforementioned second terminal is grounded.
[0182] The aforementioned tenth terminal is grounded.
[0183] The second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit.
[0184] The aforementioned sixth control terminal is connected to the aforementioned thirteenth terminal and the aforementioned first LC parallel resonant circuit.
[0185] The third terminal is connected to the first output terminal and the first LC parallel resonant circuit.
[0186] The aforementioned eleventh terminal is connected to the aforementioned second output terminal and the aforementioned second LC parallel resonant circuit.
[0187] The third control terminal is connected to the fourth terminal.
[0188] The seventh control terminal is connected to the twelfth terminal.
[0189] The aforementioned sixth terminal is grounded.
[0190] The fourteenth terminal mentioned above is grounded.
[0191] <10>
[0192] According to the amplifier circuit described in <9>, it also includes:
[0193] The third switch switches the connection and disconnection of the aforementioned fourth terminal and the aforementioned third control terminal;
[0194] The fourth switch switches the connection between the second control terminal and the fifth terminal and the connection from non-connection.
[0195] The fifth switch switches the connection and disconnection of the aforementioned twelfth terminal and the aforementioned seventh control terminal; and
[0196] The sixth switch switches the connection and disconnection of the sixth control terminal and the thirteenth terminal.
[0197] <11>
[0198] According to the amplifier circuit described in <10>, in which,
[0199] When the first and second amplifying elements are operated with a gain higher than a specified value, the third and fourth switches become conductive, and the fifth and sixth switches become deconductive.
[0200] When the fifth and sixth amplifying elements are amplified with a gain higher than the specified value, the third and fourth switches are de-conducting, and the fifth and sixth switches are conducting.
[0201] <12>
[0202] According to any one of <9> to <11>, the amplifier circuit described therein,
[0203] The fifth and sixth amplifying elements are connected in a common source, common gate configuration.
[0204] Industrial availability
[0205] This invention, as a power amplifier circuit configured in the front end for handling multiple frequency bands, can be widely used in communication devices such as mobile phones.
Claims
1. An amplification circuit, wherein, Possessing: a first input terminal and a first output terminal; a first amplification element having a first control terminal, a first terminal, and a second terminal; a second amplification element having a second control terminal, a third terminal, and a fourth terminal; a third amplification element having a third control terminal, a fifth terminal, and a sixth terminal; and a first LC parallel resonant circuit and a second LC parallel resonant circuit, the first control terminal is connected to the first input terminal, the first terminal is connected to the fourth terminal, the second terminal is grounded, the second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit, the third terminal is connected to the first output terminal and the first LC parallel resonant circuit, the third control terminal is connected to the fourth terminal, the sixth terminal is grounded.
2. The amplification circuit according to claim 1, wherein the first LC parallel resonant circuit and the second LC parallel resonant circuit are variable in resonant frequency according to a frequency of a high frequency signal input to the first input terminal. Further possessing:
3. The amplification circuit according to claim 1 or 2, wherein a first switch that switches connection and non-connection of the fourth terminal and the third control terminal; and a second switch that switches connection and non-connection of the second control terminal and the fifth terminal.
4. The amplification circuit according to claim 3, wherein in a case where a gain of the amplification circuit is higher than a prescribed value, the first switch and the second switch are in an on state, in a case where the gain of the amplification circuit is equal to or lower than the prescribed value, the first switch and the second switch are in an off state. Further possessing:
5. The amplification circuit according to any one of claims 1 to 4, wherein, a resistance element connected between the second control terminal and a bias terminal; and a capacitor connected between the second control terminal and a ground line.
6. The amplification circuit according to any one of claims 1 to 4, wherein the first amplification element and the second amplification element are connected in common source and common gate.
7. The amplification circuit according to any one of claims 1 to 6, wherein further possessing a fourth amplification element having a fourth control terminal, a seventh terminal, and an eighth terminal, the fourth amplification element is connected between the fifth terminal and the second LC parallel resonant circuit, the fourth control terminal is connected to a bias terminal, the seventh terminal is connected to the second LC parallel resonant circuit, the eighth terminal is connected to the fifth terminal, the second control terminal is connected to the fifth terminal via the seventh terminal and the eighth terminal.
8. The amplification circuit according to claim 7, wherein the third amplification element and the fourth amplification element are connected in common source and common gate. Further possessing:
9. The amplification circuit of claim 1 or 2, wherein, a second input terminal and a second output terminal; a fifth amplification element having a fifth control terminal, a ninth terminal, and a tenth terminal; a sixth amplification element having a sixth control terminal, an eleventh terminal, and a twelfth terminal; and a seventh amplification element having a seventh control terminal, a thirteenth terminal, and a fourteenth terminal, the first control terminal is connected to the first input terminal, the fifth control terminal is connected to the second input terminal, the seventh control terminal is connected to the second output terminal. The first terminal is connected to the fourth terminal, The ninth terminal is connected to the twelfth terminal, The second terminal is grounded, The tenth terminal is grounded, The second control terminal is connected to the fifth terminal and the second LC parallel resonant circuit, The sixth control terminal is connected to the thirteenth terminal and the first LC parallel resonant circuit, The third terminal is connected to the first output terminal and the first LC parallel resonant circuit, The eleventh terminal is connected to the second output terminal and the second LC parallel resonant circuit, The third control terminal is connected to the fourth terminal, The seventh control terminal is connected to the twelfth terminal, The sixth terminal is grounded, The fourteenth terminal is grounded.
10. The amplification circuit of claim 9, wherein, Further provided are: a third switch that switches connection and non-connection of the fourth terminal and the third control terminal; a fourth switch that switches connection and non-connection of the second control terminal and the fifth terminal; a fifth switch that switches connection and non-connection of the twelfth terminal and the seventh control terminal; and a sixth switch that switches connection and non-connection of the sixth control terminal and the thirteenth terminal.
11. The amplification circuit according to claim 10, wherein in a case where the first amplification element and the second amplification element are caused to perform amplification operation with a gain higher than a prescribed value, the third switch and the fourth switch are brought into an on state, and the fifth switch and the sixth switch are brought into a non-on state, in a case where the fifth amplification element and the sixth amplification element are caused to perform amplification operation with a gain higher than the prescribed value, the third switch and the fourth switch are brought into a non-on state, and the fifth switch and the sixth switch are brought into an on state.
12. The amplification circuit according to any one of claims 9 to 11, wherein the fifth amplification element and the sixth amplification element are connected in common source and common gate.
Citation Information
Patent Citations
Adjustable cascode lna with flat gain response over wide frequency band
JP2008512926A