PWM signal generator circuit and related integrated circuit

Abstract

The embodiment of the invention relates to a PWM signal generator circuit and a related integrated circuit. A PWM signal generator circuit includes a multi-phase clock generator that generates a plurality of n phase shifted clock phases that have the same clock cycle and are phase shifted by a time corresponding to a fraction 1 / n of the clock cycle. The PWM signal generator circuit determines, for each on duration, a first number of integers and a second number of integers, and determines, for each off duration, a third number of integers and a fourth number of integers. The first integer number indicates an integer number of clock cycles of the on-duration, and the second integer number indicates an integer number of an additional fraction 1 / n of the clock cycles of the on-duration. The third integer indicates an integer number of clock cycles of the turn-off duration, and the fourth integer number indicates an integer number of an additional fraction 1 / n of the clock cycles of the turn-off duration.

Description

[0001] This application is a continuation of the invention patent application with the application date of October 28, 2020 (the priority date of October 29, 2019), the Chinese national application number of 202011170294.4, and the name of “PWM signal generator circuit and related integrated circuit”. TECHNICAL FIELD

[0002] Embodiments of the present specification relate to solutions for generating a pulse width modulation (PWM) signal. BACKGROUND

[0003] Generally, as shown in Figure 1 , a PWM signal is a periodic signal with a given switching period T SW , wherein the PWM signal is set to high for a given on duration T ON , and to low for a given off duration T OFF , wherein: T SW = T ON + T OFF . (1)

[0004] Moreover, a duty cycle D of the PWM signal is generally defined, wherein D=T ON / T SW .

[0005] Such a PWM signal can be generated in various modes. For example, as shown in Figure 1 , one of the simplest solutions is based on an oscillator circuit generating a clock signal CLK, and a counter configured to increase a count value in response to the clock signal CLK. Thus, by using a comparator circuit, the PWM signal can be generated, for example, in dependence of the count value provided by the counter (e.g. by comparing the count value with a given threshold value, which for example indicates the on duration T ON and the switching period T SW ).

[0006] However, in such a (digital) implementation, the accuracy and resolution of the PWM signal is limited by the clock period T CLK of the clock signal CLK (the sampling frequency). Moreover, with increasing clock frequency f CLK =1 / T CLK , the switching losses will also increase.

[0007] However, in many applications, high resolution PWM signals are necessary or highly preferred. For example, as mentioned before, PWM signals can be used in many applications to control the average value of a voltage or current, such as for wireless battery chargers, switched mode power converters, motor control and lighting. For example, in such applications, a half-bridge or full-bridge can be used to drive a resonant tank typically comprising one or more inductors and capacitors, wherein the electronic switches of the half-bridge or full-bridge are driven by means of a PWM signal.

[0008] In order to miniaturize the device, smaller inductors can be used, resulting in higher operating frequencies. Therefore, typically, high frequency modulation waveforms PWM signals with high precision resolution should be provided in order to keep the power consumption at an acceptable value. For example, in switched mode power supplies, the output voltage is typically proportional to the PWM duty cycle. The smaller the adjustment of the duty cycle, the smaller the final change to the output, i.e. a more precise control of the output voltage permits to achieve better accuracy levels and system stability. Moreover, minimizing the output voltage ripple means reducing the noise level.

[0009] Alternative solutions for generating PWM signals, in particular high resolution (HR) PWM signals, are based on the use of multiple clock phases, i.e. phase-shifted clock signals with the same frequency.

[0010] For example, Figure 2 A possible circuit for generating multiple clock phases φ0..φ n via a delay locked loop (DLL) is shown.

[0011] In particular, in the considered example, the clock signal CLK generated by an oscillator OSC is fed to a cascade of multiple (identical) delay stages DU1..DU n . In particular, in the considered example, the first phase φ0 corresponds to the clock signal CLK, while the other phases φ1..φ n correspond to the output signals of the delay stages DU1..DU n .

[0012] In the considered example, each of the delay stages DU1..DU n has a programmable / settable delay T DU according to a (voltage or current) control signal CTRL. For example, such delay stages DU with variable delay can be implemented using an even number of inverters, wherein one or more of the inverters charge a respective capacitance, such as a parasitic capacitance, connected to the output of the inverter. In this case, the control signal CTRL can indicate the current provided by the inverter for charging the respective capacitance, thereby varying the time until the subsequent inverter switches.

[0013] In the example considered, the last phase φ n (with a given delay T relative to the clock signal CLK) D =n·T DU A clock signal CLK is provided to a phase detector PD. The output of the phase detector PD is fed to a regulator CP (such as a charge pump) having at least an I (integral) component, wherein the regulator CP provides a control signal CTRL at its output. Optionally, the control signal CTRL can be transmitted through a loop filter LF.

[0014] Therefore, essentially, the negative feedback loop implemented by the block PD / CP / LF makes the last phase φ in time... n Synchronized with clock signal CLK. If the delay unit DU is the same, then all clock phases φ1...φ n Those with the same frequency f CLK However, it has a phase shift delay T compared to the previous phase. DU =T CLK / n.

[0015] Multiple clock phases can also be provided via a phase-locked loop (PLL) comprising a voltage-controlled oscillator (VCO) having multiple delay stages, wherein the PLL is locked to the frequency of the clock signal CLK. Furthermore, in this case, the PLL locking can be achieved by varying the delay introduced by the delay stages, for example, by varying the current supplied to the inverter stage implementing such delay stages via a bias circuit, until the oscillator signal at the VCO output corresponds to the clock signal CLK. Thus, each delay stage of the VCO can provide a corresponding clock phase, which is phase-shifted by a given fraction of the period of the clock signal CLK.

[0016] For example, Figure 3 This shows the phase φ1..φ when n=17. 16 An exemplary waveform, where the last phase φ is not shown in the figure. 17 =φ0=CLK.

[0017] Therefore, such as Figure 4 As shown, although the counter and corresponding comparator circuitry can provide a coarse PWM signal (multiple k clock cycles with clock signal CLK), additional clock phases φ1..φ can be used. n To add fine-tuning to the coarse PWM signal, this essentially allows for the fractional T of the clock signal CLK to be adjusted. DU Add to the coarse PWM signal. For example, this solution is described in US 7,206,343B2, the contents of which are incorporated herein by reference.

[0018] For example, a fraction can be added to the coarse PWM signal in the following manner:

[0019] For example, by using one or more logic (e.g., OR) gates to directly combine the coarse PWM signal with a given selected clock phase φ, or

[0020] As described in document US 7,206,343 B2, the coarse PWM signal is indirectly transmitted through an additional delay stage and, for example, the coarse PWM signal is combined with the delayed PWM signal via a logic (e.g., OR) gate, where the additional delay stage introduces a delay T identical to that of delay stages DU1..DU n identical to the delay T DU , for example, by biasing the additional delay stage with the same control signal CTRL as that of delay stages DU1..DU n identical to that of delay stages DU1..DU

[0021] Therefore, assuming that the counter (and the corresponding comparator circuit) provides a coarse PWM signal with a switching period T SW =i·T CLK and an on-duration T ON =k·T CLK (0≤k≤i), then the final PWM signal can have a switching period T SW =i·T CLK and an on-duration T ON =k·T CLK +l·T CLK / n (0≤l<n). Therefore, the on-duration T of the PWM signal can be selected by setting the integer values of parameters k and l ON . Therefore, essentially, using an additional DLL or PLL allows the on-duration T ON to change with higher precision (or generally, the duty cycle D to change), while the switching period T SW remains constant. SUMMARY OF THE INVENTION

[0022] In view of the foregoing, various embodiments of the present disclosure provide solutions for generating PWM signals.

[0023] According to one or more embodiments, a PWM signal generator circuit is provided, which has unique elements described in the following description. The embodiments also relate to a corresponding integrated circuit.

[0024] Various embodiments of the present disclosure relate to a PWM signal generator circuit configured to generate a pulse width modulation signal with a given switching duration, the given switching duration including an on-duration and an off-duration.

[0025] In various embodiments, the PWM signal generator circuit includes a multi-phase clock generator configured to generate a given number n of phase-shifted clock phases having a same clock period and being phase-shifted by a time corresponding to 1 / n of the clock period.

[0026] In various embodiments, the PWM signal generator circuit is configured to:

[0027] determine, for each on-duration, a first integer number indicating an integer number of clock periods of the on-duration and a second integer indicating an integer number of a fraction 1 / n of a clock period of the on-duration additional to the integer number of clock periods of the on-duration, and

[0028] determine, for each off-duration, a third integer number indicating an integer number of clock periods of the off-duration or an integer number of clock periods of the on-duration and a fourth integer number indicating an integer number of a fraction 1 / n of a clock period of the off-duration additional to the integer number of clock periods of the off-duration.

[0029] For example, in various embodiments, the PWM signal generator circuit can receive, at an input, the first integer number, the second integer number, the third integer number, and the fourth integer number.

[0030] In various embodiments, the PWM signal generator circuit includes a clock switching circuit, a timer circuit, a phase accumulator circuit, and a trigger circuit.

[0031] In various embodiments, the clock switching circuit is configured to generate the timer clock signal by selecting one of the phase-shifted clock phases as the timer clock signal in accordance with a selection signal.

[0032] For example, in various embodiments, the clock switching circuit includes:

[0033] a respective transmission gate for each of the phase-shifted clock phases, and wherein each transmission gate is configured to generate a respective gated clock phase in accordance with the selection signal; and

[0034] combinational logic circuitry configured to generate the timer clock signal by combining the gated clock phases.

[0035] In various embodiments, the timer circuit includes one or more counters and one or more comparators, wherein the timer circuit is configured to:

[0036] during the on duration, the first count value is changed in response to the timer clock signal, and the first trigger is generated when the first count value reaches a first integer number; and

[0037] during the off duration, the second count value is changed in response to the timer clock signal, and the second trigger is generated when the second count value reaches a second integer number.

[0038] For example, the timer circuit can comprise a single counter configured to generate the first count value and the second count value. In this case, the third integer number can indicate an integer number of clock periods of the off duration, and the single counter can be reset at the start of each on duration and each off duration. Alternatively, the third integer number can indicate an integer number of clock periods of the switch duration, and the single counter can be reset only at the start of each on duration.

[0039] In various embodiments, the phase accumulator circuit is configured to generate the selection signal by:

[0040] during the on duration, the selection signal is increased by the second integer number; and

[0041] during the off duration, the selection signal is increased by a fourth integer number.

[0042] In general, the change of the selection signal can occur at any instant during the respective on duration or off duration. However, preferably, the phase accumulator circuit is configured to generate the selection signal by:

[0043] in response to the first trigger, the selection signal is increased by the second integer number; and

[0044] in response to the second trigger, the selection signal is increased by the fourth integer number.

[0045] In various embodiments, the trigger circuit is configured to:

[0046] in response to the first trigger, the PWM signal is set to low; and

[0047] in response to the second trigger, the PWM signal is set to high.

[0048] In such embodiments, the timer circuit thus operates with an adaptive clock signal generated by the switching / combining of the shifted clock phases.

[0049] The inventors have observed that the switching of the clock phase can occur while the previous clock phase is high, resulting in a loss of edges for increasing the timer circuit.

[0050] Accordingly, to compensate for the missed edges, in various embodiments, the PWM signal generator circuit is configured to:

[0051] during the on duration, determine whether the second integer number is less than n / 2; and if the second integer number is less than n / 2, increase the first count value for a single clock cycle of the timer clock signal by two; and

[0052] during the off duration, determine whether the fourth integer number is less than n / 2; and if the fourth integer number is less than n / 2, increase the second count value for a single clock cycle of the timer clock signal by two.

[0053] Alternatively, the PWM signal generator circuit can be configured to:

[0054] during the on duration, determine whether the second integer number is less than n / 2; and if the second integer is less than n / 2, decrease the first integer number by 1 ; and

[0055] during the off duration, determine whether the fourth integer number is less than n / 2; and if the fourth integer number is less than n / 2, decrease the third integer number by 1. BRIEF DESCRIPTION OF DRAWINGS

[0056] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, which are purely illustrative and non-limiting in nature, in which:

[0057] Figure 1 An example of a PWM signal is shown;

[0058] Figure 2 An example of a circuit generating a multi-phase clock signal is shown.

[0059] Figure 3 An example of a waveform of a clock phase provided by the circuit of Figure 2 An example of a waveform of a clock phase provided by the circuit of

[0060] Figure 4 An example of fine-tuning an on duration of a PWM signal by means of a multi-phase clock signal is shown;

[0061] Figure 5 An embodiment of fine-tuning both an on duration and an off duration of a PWM signal by means of a multi-phase clock signal is shown;

[0062] Figure 6A An embodiment of fine-tuning both an on duration and an off duration of a PWM signal by means of a multi-phase clock signal is shown; Figure 6B An embodiment of a timer circuit according to the present disclosure is shown;

[0063] Figure 7 An embodiment of a timer circuit according to the present disclosure is shown; Figure 6A An embodiment of a timer circuit according to the present disclosure is shown; Figure 6Bexemplary waveforms generated by the timer circuit;

[0064] Figure 8 Embodiments of a PWM generator circuit are shown; and

[0065] Figure 9A Figure 9B Figure 10A Figure 10B Figure 10C Figure 11A Figure 11B Figure 12A Figure 12B Figure 12C Figure 12D various details of the circuits of Figure 6A Figure 6B and Figure 8 are shown. DETAILED DESCRIPTION

[0066] In the following description, various specific details are set forth in order to provide a thorough understanding of the embodiments. One or more of the embodiments can be implemented without one or more of the specific details, or through other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments.

[0067] Reference to "an embodiment" or "one embodiment" in the framework of this specification means that a particular configuration, structure, or characteristic described in relation to that embodiment is included in at least one embodiment. Thus, appearances of the phrase "in one embodiment" or "in an embodiment" in various aspects of this specification are not necessarily all referring to one and the same embodiment. Furthermore, the particular configurations, structures, or characteristics can be combined in any suitable way in one or more embodiments.

[0068] The references used herein are provided merely for convenience and thus do not limit the scope of the protection or range of the embodiments.

[0069] In the following description of Figure 5 to Figure 1 2, reference is made to the parts, elements or components described in Figure 1 to Figure 4 the previous description of these figures by the same reference numerals. These elements have been described and are not repeated in the following in order not to make this detailed description cumbersome.

[0070] As previously mentioned, various embodiments of the present specification relate to a PWM signal generator circuit configured to generate a high resolution PWM signal. In particular, in various embodiments, the PWM signal generator circuit is configured to receive a plurality of clock phases φ0..φ n and to generate a PWM signal based on these clock phases φ0..φ​​​​​​​​​​​n This generates the rising and falling edges of the PWM signal, thereby controlling the PWM duty cycle and PWM frequency with higher resolution.

[0071] Figure 5 The general operation of the first embodiment is shown.

[0072] In the considered embodiment, the PWM signal generator circuit receives a first clock phase φ0 (and / or a last clock phase φ0). n =φ0) and intermediate clock phase φ1.φ n-1 In some embodiments, the PWM signal generator circuit includes a multiphase clock generator that generates various clock phases. This multiphase clock generator can include any multiphase clock generator configured to generate the clock phases described herein. Possible solutions for generating such clock phases have been described in the description of this disclosure, and the related descriptions apply in their entirety (see in particular...). Figure 2 (Description). That is, in some embodiments, the multiphase clock generator circuit of various embodiments of this disclosure can, for example, be relative to... Figure 2 Describe it.

[0073] Furthermore, in the considered embodiment, the PWM signal generator circuit is configured to generate a PWM signal, wherein:

[0074] Switch duration T SW It can be set to T SW =i·T CLK +j·T CLK / n; and

[0075] Connection time T ON It can be set to T ON =k·T CLK +l·T CLK / n.

[0076] In various embodiments, the parameters i, j, k, and l are integer values, and the parameters i, j, k, and l can be programmable.

[0077] Specifically, in Figure 5 In the example shown, assuming n=17, for example, the PWM signal generator circuit receives clock phases φ0..φ 16 Furthermore, the PWM signal generator circuit is configured to generate a PWM signal, wherein:

[0078] T SW =i·T CLK +10·T CLK / 17=T i +10·T CLK / 17,

[0079] a duty cycle of 50% (i.e., T ON = T OFF = T SW / 2), i.e., T ON = T OFF = T i / 2 + 5 · T CLK / 17.

[0080] In the considered example, for simplicity, it is assumed that i is even and that k = p = i / 2.

[0081] In particular, in the considered embodiment, the PWM signal generator circuit is configured to use the phase φ0 as a clock signal for a digital counter counting the time period T i / 2 = k · T CLK during the first on-period T1 and (as described in more detail below) the PWM signal generator circuit adds a fraction 5 / 17 of the period T CLK at the end by using the phase φ5.

[0082] However, as an alternative to subsequently tracking the accumulation of various fractions, the PWM signal generator circuit uses the phase φ5 (i.e., the phase for adding the fraction) as a clock signal for a timer circuit (i.e., a digital counter counting the time period p · T CLK during the subsequent off-period T2. Moreover, the PWM signal generator circuit again adds a respective fraction 5 / 17 of the period T 10 at the end by using the phase φ CLK until the phase φ 10 is shifted by a delay 5 · T CLK / 17 with respect to the phase φ5.

[0083] Next, the PWM signal generator circuit uses the phase φ 10 as a clock signal for a digital counter counting the time period k · T CLK during the second on-period T3 and the PWM signal generator circuit this time adds a fraction 5 / 17 of the period T 15 at the end by using the phase φ CLK until the phase φ 15 is shifted by a delay 5 · T 10 / 17 with respect to the phase φ CLK .

[0084] Likewise, the PWM signal generator circuit uses the phase φ 15as a clock signal for a digital counter that counts the time period p-T CLK and the PWM signal generator circuit this time adds a fraction 5 / 17 of the period T CLK at the end by means of the phase φ3 until the phase φ3 is offset by the delay 5-T 15 / 17 with respect to the phase φ CLK .

[0085] The operation continues for subsequent on- and off-periods as well.

[0086] In various embodiments, the PWM generator circuit is thus configured to generate a PWM signal in which:

[0087] the on-duration corresponds to T ON =k-T CLK +l-T CLK / n; and

[0088] the off-duration corresponds to T OFF =p-T CLK +q-T CLK / n.

[0089] In various embodiments, the parameter n (number of delay stages / phases) is fixed at hardware level. However, the number n can also be programmable, for example, by using a given fixed number of delay stages (e.g. 32) in Figure 2 and selecting the nth phase (not necessarily the last one) as the feedback signal provided to the phase detector PD. In fact, in this way, the control loop is still locked to the nth phase φ n , where T DU =T CLK / n.

[0090] Thus, in various embodiments, the timer circuit (including the counter circuit and the comparator circuit) of the PWM signal generator circuit is configured to:

[0091] during the on-period T ON , increase the count value from a reset value until the count value reaches the integer value k; and

[0092] during the off-period T OFF , increase the count value from a reset value until the count value reaches the integer value p.

[0093] However, in general, the timer circuit can also monitor the on-duration T SW , i.e. the timer circuit (including the counter circuit and the comparator circuit) of the PWM signal generator circuit can be configured to:

[0094] during the on-period, until the count value reaches the integer value k; and

[0095] during the off-period, the count value used during the on-period is increased until the count value reaches the integer value i.

[0096] Thus, in various embodiments, the PWM signal generator circuit is configured to determine the parameters k / l and at least one of p / q and i / j, wherein:

[0097] in case of an on-period T ON , k corresponds to an integer number of clock cycles of the clock signal CLK and l corresponds to an integer number of fractions 1 / n of a clock cycle of the clock signal CLK;

[0098] in case of an off-period T OFF , p corresponds to an integer number of clock cycles of the clock signal CLK and q corresponds to an integer number of fractions 1 / n of a clock cycle of the clock signal CLK; and

[0099] in case of a switching period T SW , i corresponds to an integer number of clock cycles of the clock signal CLK and j corresponds to an integer number of fractions 1 / n of a clock cycle of the clock signal CLK.

[0100] In particular, in view of the above definitions: T ON = k · T CLK + l · T CLK / n (2) T OFF = p · T CLK + q · T CLK / n (3) T SW = T ON + T OFF = i · T CLK + j · T CLK / n (4)

[0101] The integer values i and j are related to the integer values k, l, p and q according to the following equations:

[0102] if (l+q) < n (no overflow), then: i = k + p; j = l + q, (5)

[0103] if (l+q) > n (with overflow), then: i = k + p + 1; j = l + q - n. (6)

[0104] Accordingly, in various embodiments, the PWM generator circuit is configured to receive at least two of the parameters i, k, and p, and at least two of the parameters j, l, and q. For example, the PWM signal generator circuit can receive parameters k / l and / or p / q and / or i / j directly, such as:

[0105] data identifying (e.g., corresponding to) the parameters k / l; and

[0106] data identifying (e.g., corresponding to) the parameters p / q.

[0107] Alternatively, the PWM signal generator circuit can receive other data, permitting the calculation of these parameters according to equations (5) and (6), such as:

[0108] data identifying the switch duration T SW , such as the parameters i and j mentioned above, and one of:

[0109] data identifying (e.g., corresponding to) the parameters k / l;

[0110] data identifying (e.g., corresponding to) the parameters p / q; or

[0111] data identifying the duty cycle.

[0112] As shown in Figure 6A , in various embodiments, the PWM signal generator circuit includes a timer circuit 102 including a digital counter circuit 104 configured to cause an integer count value CNT to change (i.e., increase or decrease) in response to a clock signal CLK TMR, and a comparator circuit 106 configured to compare the count value CNT to a respective integer comparison threshold.

[0113] As shown in Figure 6A , by selecting parameter k or p as the comparison threshold, for example, via a multiplexer 108, the same counter 104 and comparator 106 can be used for both the on period and the off period. Thus, by resetting the counter 104 via the signal at the output of the comparator 106, the same counter 104 can be used to monitor both the on period and the off period. However, the counter 104 can also be used to monitor the on period and the duration T SW . For example, in this case, the multiplexer 108 can receive parameters k and i, and the counter 104 can be reset only when the count value CNT reaches the value i.

[0114] Alternatively, as shown in Figure 6BAs shown, the respective counters 104a and 104b and comparators 106a and 106b can be used for the on-period and the off-period, wherein the comparator 106a compares the count value CNTa provided by the comparison counter 104a with the parameter k, and the comparator 106b compares the count value CNTb provided by the comparison counter 104b with the parameter p.

[0115] In various embodiments, the timer circuit 102 is configured to generate one or more trigger signals when the output of the comparator indicates that the count value has reached the comparison threshold value (e.g. by using the signal EOC_TMR at the output of the comparator 106 or the signals EOC_TMRa and EOC_TMRb at the outputs of the comparators 106a and 106b).

[0116] In the considered embodiments, the signal EOC_TMR ( Figure 6A ) or the signals EOC_TMRa and EOC_TMRb ( Figure 6B ) are provided to a control circuit 110, which selects the clock signal CLK_TMR for the timer circuit 102 (in particular the counter 104 (104a / 104b)) depending on:

[0117] During the on-period, the parameter l; and

[0118] During the off-period, the parameter q.

[0119] In particular, even at the end of the monitoring of the switch duration T SW , it is preferred to obtain (e.g. calculate) the parameter q, e.g. according to equations (5) and (6), since this parameter indicates the additional fraction that has to be added with respect to the previous on-time.

[0120] For example, the control circuit 110 can select the clock signal CLK_TMR by driving the multiplexer 100 at the input receiving the clock phases φ0..φ n-1 Likewise, the control signal can drive the multiplexer 112 via the selection signal SEL2 in order to select the parameter l or the parameter q, i.e. the selection signal indicates whether the current period is an on-period or an off-period and can thus also be used to drive the multiplexer 108.

[0121] In particular, in various embodiments, in response to a trigger in the signal EOC_TMR ( Figure 6A ) or the signals EOC_TMRa and EOC_TMRb ( Figure 6B ), the control circuit 110 is configured to change the logic value of the selection signal SEL1:

[0122] During the on-period, according to the parameter l; and

[0123] During the off period, according to the parameter q.

[0124] In particular, in various embodiments, the control circuit also performs a modulo operation in order to maintain the selection signal SEL1 between 0 and n-1. Thus, in response to a trigger in the signal EOC_TMR ( Figure 6A ) or in the signals EOC_TMRa and EOC_TMRb ( Figure 6B ), the control circuit 110 causes the selection signal SEL1 to change:

[0125] During the on period, SEL1 = (SEL1 + 1) mod n; and

[0126] During the off period, SEL1 = (SEL1 + q) mod n.

[0127] Thus, in essence, the control circuit 110 implements a phase accumulator circuit that adds either 1 or q to the currently selected phase, where the parameter q can be computed according to the parameters j and n (e.g., as shown in equations (5) and (6)).

[0128] Finally, in various embodiments, the respective period (on period or off period) is terminated, and the subsequent period starts with the next clock pulse from the selected clock phase (i.e., the next rising edge or falling edge based on which type of edge the timer circuit 102 uses).

[0129] Thus, in essence, during the on period T ON , the trigger signal EOC_TMR (or EOC_TMRa) is generated after the time k · T CLK , and the on period is terminated by changing the clock signal CLK_TMR, such that the next off period starts after the additional time l / n · T CLK . Likewise, during the off period T OFF , the trigger signal EOC_TMR (or EOC_TMRb) is generated after the time p · T CLK (e.g., which can be obtained by resetting the counter 104 and waiting for p cycles or by waiting until the count value reaches i), and the off period is terminated by changing the clock signal CLK_TMR, such that the next on period starts after the additional time q / n · T CLK .

[0130] For example, this is shown in Figure 7 , where during the on period, the timer circuit uses the clock phase CLK_TMR = φ x , and, for example, in the phase φx EOC_TMR is set. In response to the trigger signal EOC_TMR (EOC_TMRa), the control circuit selects the new phase CLK_TMR = φ y (where y = (x+ l) mod n). Moreover, in response to a (e.g. rising) edge immediately following in the signal φ y the PWM signal generator circuit terminates the on-period and starts the subsequent off-period, thereby introducing an additional time corresponding to the fraction l / n of a clock period.

[0131] In the considered embodiment, during the subsequent off-period, the timer circuit uses the clock phase CLK_TMR = φ y and, for example, after p = 8 periods of the phase φ y EOC_TMR is set. In response to the trigger signal EOC_TMR (EOC_TMRb), the control circuit selects the new phase CLK_TMR = φ z (where z = (y+ q) mod n). In response to a (e.g. rising) edge immediately following in the signal φ z the PWM signal generator circuit terminates the off-period and starts the subsequent on-period, thereby introducing an additional time corresponding to the fraction q / n of a clock period.

[0132] In the previous embodiments, the control circuit 110 is configured to drive the selection circuit 100 so as to change the phase φ assigned to the clock signal CLK_TMR from the current phase φ(t) (e.g. φ0) to the next phase φ(t+1) (e.g. φ5) in response to the signal EOC_TMR, thereby adding the fraction (l or q) at the end of the respective on or off period.

[0133] However, in various embodiments, the switching from the current phase φ(t) to the next phase φ(t+1) can occur at any instant during the respective period. In this case, the control unit 110 can also be configured to sequentially increase / decrease the selection signal SEL1 from the old phase φ(t) to the new phase φ(t+1) (e.g. φ0, φ1, φ2, φ3, φ4, φ5) or directly increase / decrease to the new phase φ(t+1) by switching, e.g. in response to the clock signal CLK_TMR.

[0134] In general, although reference has been made to periods of the clock signal CLK, in practice the phases φ0... φ n-1 may also have different clock periods T PLL , e.g. a frequency f PLL = 1 / T PLLIt can be the clock frequency f CLK A multiple of, for example, through phase φ n-1 A frequency divider is used in the feedback loop. Therefore, generally speaking:

[0135] Connection duration and T ON =k·T PLL +l·T PLL / n corresponds to; and

[0136] Off duration and T OFF =p·T PLL +q·T PLL / n corresponds to.

[0137] Figure 8 A second embodiment of the PWM signal generator circuit is shown.

[0138] Specifically, in the considered embodiment, the PWM signal generator circuit again includes a timer circuit 102, a clock switching circuit 100ʹ, and a control circuit / phase accumulator 110ʹ.

[0139] Specifically, for Figure 6A and Figure 6B The clock switching circuit 100ʹ is not implemented using only a multiplexer, but rather a circuit that directly generates a clock signal CLK_TMR for the timer circuit in response to the trigger signal EOC_TMR provided by the timer circuit 102, based on the selection signal SEL1 provided by the control circuit 110ʹ. Typically, as mentioned earlier, any other trigger signal can also be used to assign a new clock phase to the clock signal CLK_TMR based on the selection signal SEL1.

[0140] For example, in Figure 9A and Figure 9B A possible embodiment of the clock switching circuit 100ʹ is shown.

[0141] In the considered embodiment, a selection signal SEL1 (indicating the next clock phase) is provided to a series of selectable latches 1000, which are configured to store the value of signal SEL1 in response to a trigger signal EOC_TMR. Essentially, these latches 1000 ensure that the circuit samples the value of signal SEL1 only when a trigger occurs in the signal EOC_TMR.

[0142] In the considered embodiment, each clock phase φ0…φ n-1 Provided to the corresponding transmission gate (gated clock unit) 10020...1002 n It is enabled based on the selection signal SEL1 or the optional latch selection signal SEL1, thereby generating the corresponding (gated) signal φ.0_gtd …φ n-1_gtd For example, in various embodiments, the selection signal comprises (n) bits SEL0...SEL n-1 and uses one-hot encoding, where a given bit is associated with a given clock phase φ0...φ n-1 uniquely (i.e., only one bit of SEL0...SEL n-1 is set), and indicates the respective clock phase φ0...φ n-1 may pass through the respective transmission gate 10020...1002 n-1 , while the other clock phases φ0...φ n-1 cannot pass through the respective transmission gate 10020...1002 n-1 . Generally, other encoding schemes can also be used for the selection signal (such as binary encoding), and the transmission gates can be driven via a decoder circuit configured to generate one-hot encoded drive signals for the transmission gates 10020...1002 n-1 from the selection signal SEL1.

[0143] As shown in Figure 9B , the signals φ 0_gtd ...φ n-1_gtd are then provided to a combinational logic circuit 1004, which is configured to generate, at an output, a clock signal CLK TMR for the timer circuit 102 by combining the signals φ 0_gtd ...φ n-1_gtd . For example, in various embodiments, the signals φ 0_gtd ...φ n-1_gtd are combined via a logical OR operation, e.g., using a cascaded structure of multiple OR gates OR1, OR2, OR3, etc.

[0144] Figure 10A shows operation of the clock switching circuit 100ʹ at an example of the selection signal SEL1 having values k, x, and y in sequence, thereby (in response to the trigger signal EOC TMR) activating the clock phases φ k_gtd , φ x_gtd , and φ y_gtd , in sequence.

[0145] Thus, if the selection signal SEL1 changes, the clock signal CLK TMR switches from the first clock phase to the second clock phase in response to the selection signal.

[0146] In particular, as shown in Figure 10B , when the second clock phase (φ x_gtd ) becomes high (rising edge), and the first clock phase (φ k_gtdWhen φ is still high, the generated clock signal CLK_TMR will have a duration higher than the clock phase φ0...φ n-1 clock cycle T PLL A single clock pulse is lost, thus essentially a clock cycle is lost.

[0147] This usually happens when the corresponding fraction l or q is less than n / 2.

[0148] On the contrary, such as Figure 10C As shown, when the second clock phase (φ) y_gtd ) becomes high (rising edge), and the first clock phase (φ) x_gtd When φ is low, the generated clock signal CLK_TMR has a duration less than the clock phase φ0...φ n-1 clock cycle T PLL A single clock pulse. This typically occurs when the corresponding fraction l or q is greater than n / 2.

[0149] Therefore, in order to correctly determine the duration of the corresponding time interval, the lost clock edges should be taken into account. Figure 10B Specifically, in various embodiments, if a clock cycle is lost (i.e., the corresponding fraction l or q is less than n / 2), the PWM signal generator circuit is configured to add an additional clock cycle to the timer circuit 102, that is, within a single clock cycle, the timer 102 increments by 2 instead of just 1.

[0150] Figure 11A A possible embodiment of the timer circuit 102 is shown.

[0151] Specifically, in the considered embodiment, counter 104 is implemented using an accumulator, which includes:

[0152] Register 1040, which provides the count value CNT at its output, is configured to store the signal REG_IN at the corresponding input in response to the clock signal CLK_TMR; and

[0153] Digital adder 1042 is configured to generate signal REG_IN at input of register 1040 by adding increment value INC to count value CNT.

[0154] In the considered embodiment, the incremental value INC can be set to "1" or "2" for example via multiplexer 1044. Specifically, the selection is driven via the selection signal SEL3 provided by control circuit 110 (or also via control circuit 110').

[0155] Specifically, in the considered embodiment, the control circuit 110 includes:

[0156] a digital comparator 1100 configured to determine whether the fractional value I or q of the current on-period or the current off-period is greater than n / 2; and

[0157] a circuit 1102 configured to generate the selection signal SEL3 from the comparison signal generated by the comparator 1100 and a trigger signal (such as the signal EOC TMR) indicating the start of a new on-period or a new off-period; or, in general, from the comparison signal generated by the comparator 1100 and a general trigger signal generated at any appropriate moment during an on-period or an off-period and having a length of one CLK TMR cycle.

[0158] In particular, in the considered embodiment, the multiplexer 112 has provided the fractional value for the current period, with the selection signal SEL2 indicating whether the current period is an on-period or an off-period. Thus, the comparator 1100 can receive at the input the signal provided by the multiplexer 112 and thus generate a comparison signal indicating whether the fractional value I or q is greater than n / 2. In particular, the circuits 110 and 112 are configured to:

[0159] when the signal at the output of the comparator indicates that the fraction I or q (based on the current period) is greater than n / 2 or that the trigger signal (e.g. EOC TMR) is not set, the multiplexer 1044 is driven via the signal SEL3 so as to select the value "1", whereby the accumulator 1040 / 1042 is increased by "1" in response to the clock signal CLK TMR; and

[0160] when the signal at the output of the comparator indicates that the fraction I or q (based on the current period) is less than n / 2 and that the trigger signal (e.g. EOC TMR) is set, the multiplexer 1044 is driven via the signal SEL3 so as to select the value "2", whereby the accumulator 1040 / 1042 is increased by "2" in response to the clock signal CLK TMR.

[0161] Thus, in essence, the timer circuit 104 is configured to increase the count value by two ("2") for one clock cycle of the signal CLK TMR (i.e. a single cycle of each on-period or off-period) when the fraction I or q (based on the current period) is less than n / 2.

[0162] Conversely, Figure 11B It is shown that similar results can be obtained by directly adjusting the threshold value used by the comparator 106.

[0163] In particular, in the considered embodiment, the increment value INC is always set to "1" and an additional digital subtractor is provided, which is configured, for example, via the multiplexer 1048, to:

[0164] Subtracting the value "1" from the current threshold (k or p) selected by the multiplexer 108; or

[0165] Maintaining the threshold, e.g. by subtracting the value "0" from the current threshold (k or p) selected by the multiplexer 108.

[0166] In general, embodiments can also be combined, i.e. during the on duration, the PWM signal can be toggled by the "add two" mechanism ( Figure 11A ) or the adjustment of the threshold k ( Figure 11B ), and during the off duration, the PWM signal can be toggled by the "add two" mechanism or the adjustment of the threshold p.

[0167] Thus, in the embodiments considered, the circuit 1100 / 1102 informs the timer circuit 102 that it has missed or is about to miss a counting edge due to Figure 9B the clock combination shown. This missed edge information (i.e. the signal SEL3) can be computed by the control circuit / phase accumulator machine 110 / 110ʹ which controls the fine delay selection and generates the phase selection change SEL1 (indicating the next clock phase to be used for fine tuning the PWM signal). In fact, if the new phase selection selects a clock having a rising edge occurring during the on time of the running clock, it then combines CLK_TMR will have a longer on time and the clock phase selected for Figure 9B the next clock phase of the clock combination circuitry for

[0168] Using this clock change property, the timer can be incremented by "1" or "2", or the threshold of the comparator 106 can be adjusted with respect to this internal flag generated as shown in Figure 11A or Figure 11B .

[0169] In various embodiments, the PWM signal is toggled in response to the next rising edge of the new clock phase (i.e. the selected clock phase φ 0_gtd ...φ n-1_gtd ) of the subsequent on period or off period. However, in case the SEL1 signal is generated at any appropriate instant during a given slot / period, the PWM signal can also be changed in response to the rising edge of the trigger signal EOC_TMR.

[0170] For example, as shown in Figure 8As shown, the PWM signal generator circuit can comprise a flip-flop circuit 114 configured to generate a PWM signal φ 0_gtd ...φ n-1_gtd and the flip-flop signal EOC_TMR.

[0171] Generally, in response to the signal EOC_TMR (or EOC_TMRa and EOC_TMRb) and the new clock phase, any suitable circuit can be used to switch the level of the PWM signal.

[0172] For example, Figure 12A An embodiment of the flip-flop circuit 114 is shown. In particular, the flip-flop circuit 114 comprises a rising edge detector circuit. In particular, in the considered embodiment, the flip-flop circuit comprises a respective rising edge detector 11400..1140 0_gtd ...φ n-1_gtd for each of the signals φ n-1 which is enabled in dependence of the signal EOC_TMR.

[0173] In particular, as shown in Figure 12B , Figure 12C and Figure 12D in response to a rising edge of the current clock phase (e.g. φ Figure 12C in k_gtd ), the signal EOC_TMR will be set after a short delay. In response to the flip in the signal EOC_TMR, the circuit 100ʹ will switch to the new clock phase (e.g. φ Figure 12C in x_gtd ). Thus, no additional rising edge of the old clock signal (e.g. φ Figure 12C in k_gtd ) will occur. Thus, in response to a subsequent rising edge in the new clock phase (e.g. φ Figure 12C in x_gtd ), the respective edge detector 1140 sets its output (e.g. to high) also because the signal EOC_TMR is still set.

[0174] Thus, in the considered embodiment, for this purpose, the outputs of the various rising edge detectors 11400..1140 n-1 may be connected to a combinatorial logic circuit (e.g. implementing a logical OR function) Figure 12AA logic OR gate OR4 is schematically shown, which can correspond to the last OR gate in a chain of OR gates, e.g. including 6 OR gates with 3 inputs, 2 OR gates with 2 inputs, and the OR gate OR4 in a cascade, but in general, different numbers and topologies of gates can be used to implement the various rising edge detectors 11400..1140 n-1 The output of the OR gate OR4, which can correspond to the last OR gate in a chain of OR gates, e.g. including 6 OR gates with 3 inputs, 2 OR gates with 2 inputs, and the OR gate OR4 in a cascade, but in general, different numbers and topologies of gates can be used to implement the various rising edge detectors 11400..1140

[0175] Thus, in the considered embodiment, the signal TRIG can be used to drive a flip-flop FF1 in order to invert the output of the flip-flop FF1, wherein the PWM signal is generated (and preferably corresponds to) the signal at the output of the flip-flop FF1.

[0176] For example, in the considered embodiment, the flip-flop FF1 is implemented using a D-type flip-flop, which receives the inverted output signal of the flip-flop FF1 at the data terminal D via an inverter INV1, so that the output of the flip-flop FF1 is inverted in response to the trigger signal TRIG.

[0177] Of course, the details of construction and embodiments can vary widely with respect to what is described and illustrated herein by way of example only, without thereby departing from the scope of the present disclosure, as defined by the claims hereafter, without impairing the principles of the present disclosure.

[0178] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above- described description. In general, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, in conjunction with other features, structures, or characteristics not expressly described above. It will be appreciated that those skilled in the art will be able to devise many embodiments which, although not explicitly described herein, embody the principles of the disclosure and are within the scope of the disclosure as defined by the following claims. Thus, the disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. A method comprising: During the connection duration: In a timer circuit that includes a counter and a comparator, a first count value is changed in response to a timer clock signal, and the timer circuit is part of a pulse width modulation signal generator. as well as A first trigger is generated when the first count value reaches a first integer, wherein the first integer indicates the number of clock cycles for the on-time duration; During the shutdown duration: The second count value is changed in response to the timer clock signal; as well as A second trigger is generated when the second count value reaches a second integer, the second integer indicating the number of clock cycles for the shutdown duration; as well as During the connection duration: Determine whether a third integer is less than n / 2, where n is equal to the number of phase-shifted clock phases of the timer clock signal, and in response to determining that the third integer is less than n / 2, increment the first count value of a single clock cycle of the timer clock signal by 2.

2. The method of claim 1, wherein during the off-duration period, the signal generator is used to determine whether the fourth integer is less than n / 2.

3. The method of claim 2, wherein in response to determining that the fourth integer is less than n / 2, the second count value of a single clock cycle of the timer clock signal is incremented by 2.

4. The method of claim 3, wherein during the on-time, the signal generator determines whether the third integer is less than n / 2, where n is equal to the number of phase-shifted clock phases.

5. The method of claim 4, wherein in response to determining that the third integer is less than n / 2, the first integer is decreased by one.

6. The method of claim 5, wherein during the off-duration period, the signal generator is used to determine whether the fourth integer is less than n / 2.

7. The method of claim 6, wherein in response to determining that the fourth integer is less than n / 2, the second integer is decreased by one.

8. A circuit comprising: The timer circuit includes: A register, configured to output a count value, and configured to store a signal at a corresponding input in response to a clock signal; and An adder, configured to generate the signal at the input of the register, and configured to add an increment value to the count value; and A multiplexer is coupled to the adder and configured to set the increment value.

9. The circuit of claim 8, wherein the timer circuit includes a control circuit configured to provide a selection signal to the multiplexer.

10. The circuit of claim 9, wherein the timer circuit includes a digital comparator configured to determine whether the fraction of the current on-cycle or off-cycle is greater than n / 2.

11. The circuit of claim 10, wherein the control circuit is configured to generate a selection signal based on a comparison signal generated by the comparator and a trigger signal indicating the start of a new on-cycle or off-cycle.

12. The circuit of claim 11, wherein the control circuit is configured to: When the signal at the output of the comparator indicates that the fraction l or q based on the current period is greater than n / 2, or when the trigger signal is not set, the multiplexer is driven via the selection signal and the accumulator is incremented by a first value in response to the clock signal.

13. The circuit of claim 12, wherein the control circuit is configured to drive the multiplexer via the selection signal when the signal at the output of the comparator indicates that the fraction l or q based on the current period is less than n / 2 and the trigger signal is set, the accumulator increasing by a second value greater than the first value in response to the clock signal.

14. The circuit of claim 13, wherein the first value is 1 and the second value is 2.

15. A method comprising: Set the incremental value in the multiplexer; In a digital adder, a signal is generated by adding the increment value to the count value; The signal is stored in the first input of the register in response to a clock signal; as well as The count value is output at the output of the register.

16. The method of claim 8, wherein the multiplexer is coupled to a control circuit.

17. The method of claim 16, wherein setting the incremental value in the multiplexer is driven by a selection signal provided to the control circuitry.

18. The method of claim 17, wherein the control circuitry includes a digital comparator that generates a comparison signal.

19. The method of claim 18, wherein the control circuit includes a selection signal generation circuit that generates the selection signal based on the comparison signal.

20. The method of claim 19, wherein the selection signal generation circuit generates the selection signal based on the comparison signal and the trigger signal, the trigger signal having the length of a cycle of the clock signal.

21. The method of claim 20, wherein the trigger signal is generated at any time during the on-cycle or off-cycle.

22. The method of claim 20, wherein the trigger signal indicates the start of a new on-cycle or off-cycle.

23. A method comprising: In response to a trigger signal, the selection signal is stored in multiple latches; Each clock phase is provided to the corresponding transmission gate according to the selection signal; A clock signal is generated using combinational logic circuitry in response to the selection signal; In response to the trigger signal, each of the clock phases is activated sequentially by a clock switching circuit; as well as In response to the change of the selection signal, the clock signal is switched from a first clock phase to a second clock phase.

24. The method of claim 23, wherein the selection signal represents the next clock phase.

25. The method of claim 23, wherein the plurality of latches are configured to allow sampling of the value of the selection signal only in response to the trigger signal.

26. The method of claim 23, wherein the selection signal comprises n bits, and wherein the positioning is associated with only one given clock phase, only the given clock phase being configured to pass through the corresponding transmission gate.

27. The method of claim 23, wherein the second clock phase becomes high when the first clock phase is high, causing the clock signal to have a single clock pulse with a duration greater than the clock period of the clock phase.

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