Method for improving alignment of contact hole and groove in insulated gate bipolar transistor

Abstract

The invention provides a method for improving overlay alignment of a contact hole and a groove in an insulated gate bipolar transistor. The method comprises the following steps: carrying out thermal oxidation treatment on a wafer, and synchronously forming a back oxidation film on the back of the wafer; before the groove photoetching step is carried out, part of the back oxidation film is removed so as to control the warping degree of the wafer to be in a preset state; performing groove photoetching and etching to form a groove; after at least one heat treatment, a contact hole lithography step is performed to form a contact hole. According to the method, the warping states of the wafer in the two key steps of groove photoetching and contact hole photoetching are actively regulated and controlled, so that the warping states are basically kept consistent, and overlay alignment deviation caused by inconsistent warping is systematically eliminated. According to the method, the overlay alignment precision can be remarkably improved, the uniformity of the electrical performance of the device and the process stability are improved, and the product yield is further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the alignment of contact holes and trenches in an insulated gate bipolar transistor. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs), as a key power semiconductor device, are typically manufactured using silicon substrates and require multiple high-temperature thermal processing steps. While these process steps are crucial for device performance, they also introduce and accumulate stress within the wafer, leading to significant wafer warping.

[0003] Wafer warpage has a direct negative impact on the precision of photolithography processes. In the IGBT manufacturing process, the formation of trench structures and contact vias are two critical photolithography steps. Due to wafer warpage, especially in the wafer edge region, focal plane deviation occurs during alignment and exposure of the photolithography machine, resulting in severe overlay misalignment between the trench layer and the contact via layer. This overlay misalignment directly affects the electrical performance and reliability of the device. For example, it may lead to deterioration of key parameters such as on-state voltage drop, or even device failure during the circuit probing stage, thus significantly reducing product yield. As the size of semiconductor devices continues to shrink, the pitch of feature structures becomes smaller, and the trench density increases accordingly, making the overlay misalignment problem caused by wafer warpage increasingly severe.

[0004] In existing technologies, efforts are typically made to minimize wafer warpage before each critical lithography step to ensure alignment accuracy. However, in the complex manufacturing process of IGBTs, multiple thermal processing steps are involved between trench formation and contact hole formation. These subsequent thermal processes alter the wafer's stress state again, causing warpage to occur again. Therefore, even if the wafer is relatively flat during trench lithography, it may have become severely warped by the time contact hole lithography is performed, and vice versa. This inconsistency in wafer warpage between different critical lithography steps is the root cause of alignment deviations.

[0005] Therefore, how to effectively control and coordinate the wafer warpage state during different key lithography steps in the IGBT manufacturing process in order to improve the alignment accuracy between trenches and contact holes has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The purpose of this application is to provide a method for improving the alignment of contact holes and trenches in insulated gate bipolar transistors, so as to solve the problems of poor alignment accuracy and low device yield caused by the inconsistency of wafer warping state between trench lithography and contact hole lithography steps in the prior art.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] A method for improving the alignment of contact holes and trenches in an insulated gate bipolar transistor includes the following steps:

[0009] Step 1: Perform one or more thermal oxidation processes on the wafer to form the device structure on the front side of the wafer while simultaneously forming a back oxide film on the back side of the wafer.

[0010] Step 2: Before performing trench lithography, remove part of the back oxide film on the back side of the wafer to control the wafer warpage to a preset state.

[0011] Step 3: After removing part of the back oxide film, perform trench photolithography and trench etching on the wafer to form trenches;

[0012] Step 4: After the trenches are formed, the wafer is subjected to one or more heat treatments, and a contact hole photolithography step is performed to form contact holes.

[0013] Preferably, by controlling the amount of back oxide film removed in step two, the first warpage state of the wafer during the trench lithography step in step three is substantially consistent with the second warpage state during the contact hole lithography step in step four.

[0014] Preferably, the one or more thermal oxidation treatments in step one are thermal oxidation steps in a localized oxidation process.

[0015] Preferably, prior to the thermal oxidation step, the process further includes: defining a field region and an active region on the front side of the wafer through patterning, such that the field region exposes the silicon substrate.

[0016] Preferably, in the thermal oxidation step of step one, a field oxide layer is formed on the silicon substrate exposed in the field area, and a back oxide film is simultaneously formed on the back side of the wafer.

[0017] Preferably, the thickness of the formed back oxide film is 13,000 to 16,000 angstroms.

[0018] Preferably, the patterning process includes: sequentially forming a hard mask structure on the front side of the wafer; and patterning the hard mask structure through photolithography and etching processes.

[0019] Preferably, the hard mask structure includes: a pad oxide layer; a silicon nitride layer; and a top oxide layer.

[0020] Preferably, the thickness of the pad oxide layer is 200 to 600 angstroms.

[0021] Preferredly, the thickness of the silicon nitride layer is 1100 angstroms to 1800 angstroms.

[0022] Preferably, the thickness of the top oxide layer is 1000 angstroms to 3000 angstroms.

[0023] Preferably, after the thermal oxidation step in step one, the process further includes: removing the hard mask structure by a wet etching process.

[0024] Preferably, the wet etching process includes: removing the top oxide layer and pad oxide layer using a hydrofluoric acid solution; and removing the silicon nitride layer using hot phosphoric acid.

[0025] Preferably, in step two, the thickness of the removed back oxide film is 3,000 to 13,000 angstroms.

[0026] Preferably, before the trench lithography step in step three, the method further includes: depositing a trench hard mask layer on the front side of the wafer.

[0027] Preferably, the trench hard mask layer is a silicon oxide layer.

[0028] Preferably, the thickness of the trench hard mask layer is 3000 angstroms to 5000 angstroms.

[0029] Preferably, one or more heat treatments include annealing or oxide growth processes.

[0030] As described above, the method for improving the alignment of contact holes and trenches in an insulated gate bipolar transistor according to the present invention has the following beneficial effects:

[0031] 1. This application achieves a basic consistency in wafer warpage during the two critical steps of trench lithography and contact hole lithography by actively managing and controlling the warpage state of the wafer at different process stages, thereby fundamentally solving the problem of overlay alignment deviation caused by warpage mismatch.

[0032] 2. This application can significantly improve the overlay alignment accuracy. Experimental data shows that after adopting this method, the maximum overlay alignment error can be reduced from 0.16 micrometers to 0.04 micrometers, with a significant improvement effect.

[0033] 3. This application can improve the uniformity of electrical performance and process stability of devices. Experimental data show that after adopting this method, the distribution of the key electrical parameters (Delta VDSON) of the device is more convergent and the dispersion is smaller, thereby improving the overall yield and reliability of the product.

[0034] 4. The method of this application cleverly utilizes the inherent results of standard processes (such as LOCOS) and controls them through back-side thinning without the need for additional complex equipment or process steps, thus having good process compatibility and cost-effectiveness. Attached Figure Description

[0035] Figure 1 The diagram shows a flow chart of a process for improving overlay alignment provided in an embodiment of this application.

[0036] Figure 2 This is a schematic diagram illustrating the effect of back oxide film etching on wafer warpage in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram illustrating the effect of subsequent thermal processing on wafer warpage in an embodiment of this application.

[0038] Figure 4 This diagram illustrates the photolithographic alignment of the trench and the contact hole under ideal flat conditions.

[0039] Figure 5 This diagram illustrates the misalignment caused by the flatness of the groove photolithography and the warping of the contact hole photolithography in the traditional process.

[0040] Figure 6 This diagram illustrates the misalignment caused by warping in groove lithography and smooth lithography in contact hole lithography in traditional processes.

[0041] Figure 7 The diagram shows a schematic of how the method of this application achieves precise alignment by ensuring that both the trench and the contact hole are in a slightly warped state during photolithography.

[0042] Figure 8 The diagram shows a comparison of experimental data on overlay alignment errors before and after using the method described in this application.

[0043] Figure 9 The figure shows a comparison of experimental data on the electrical parameters (Delta VDSON) of the device before and after using the method of this application. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please refer to Figure 1 , Figure 1A schematic flowchart of a process for improving overlay alignment provided in an embodiment of this application includes the following steps:

[0046] Step 1: Perform one or more thermal oxidation processes on the wafer to form the device structure on the front side of the wafer while simultaneously forming a back oxide film on the back side of the wafer.

[0047] In some embodiments, the thermal oxidation process in step one is the thermal oxidation step in the Localized Oxidation System (LOCOS) process. This is a mature and widely used semiconductor device isolation technology, and this application utilizes the inherent characteristics of this process to serve the purpose of global warp management.

[0048] In some embodiments, prior to the thermal oxidation step in step one, the method further includes: defining a field region and an active region on the front side of the wafer by patterning, such that the field region exposes the silicon substrate.

[0049] In some embodiments, during the thermal oxidation step of step one, a field oxide layer is formed on the silicon substrate exposed in the field region, and a back oxide film is simultaneously formed on the back side of the wafer. This simultaneous formation process is a key feature of this application because it generates the core structure for subsequent stress modulation and warpage management—the thick back oxide film—in a single standard process step without adding any additional process steps, offering good cost-effectiveness and process compatibility.

[0050] In some embodiments, the thickness of the back oxide film formed in step one is 13,000 to 16,000 angstroms. Such a thick back oxide film introduces significant compressive stress within the wafer, causing the wafer to exhibit a predictable, initial warpage, providing a basis for subsequent precise control through back-side thinning.

[0051] In some embodiments, the patterning process in step one includes: sequentially forming a hard mask structure on the front side of the wafer; and patterning the hard mask structure using photolithography and etching processes. This is to selectively protect the active regions while exposing the field regions for subsequent thick oxide layer growth.

[0052] In some embodiments, in step one, the hard mask structure includes: a pad oxide layer; a silicon nitride layer; and a top oxide layer. This is a typical three-layer hard mask stack structure, where the materials and formation methods of each layer can have multiple choices and alternatives to adapt to different process integration needs and performance requirements.

[0053] Pad oxide layer: Besides growing silicon dioxide (SiO2) through thermal oxidation, pad oxide layers can also be formed using chemical vapor deposition (CVD) methods, such as CVD processes using tetraethoxysilane (TEOS) as a precursor. In some applications, to better control stress or achieve specific interface properties, the pad oxide layer can also be silicon oxynitride (SiON), or a stacked structure consisting of alternating extremely thin oxide and nitride layers. Its core function is to act as a stress buffer layer and protect the silicon surface from damage during subsequent silicon nitride removal.

[0054] Silicon nitride layer: This layer is the core barrier layer for achieving localized oxidation. It is typically formed using low-pressure chemical vapor deposition (LPCVD) to create stoichiometric silicon nitride (Si3N4). Depending on the requirements for film stress and oxygen barrier properties, plasma-enhanced chemical vapor deposition (PECVD) can also be used to form silicon-rich or low-hydrogen-content silicon nitride. In more advanced process nodes, atomic layer deposition (ALD) technology may be used to grow silicon nitride films with excellent thickness uniformity and density.

[0055] Top oxide layer: This layer typically serves as an anti-reflective coating (ARC) and a hard mask for etching the silicon nitride layer. Besides CVD-grown silicon dioxide, this layer can also be silicon oxynitride (SiON). Its optical constants (refractive index n and extinction coefficient k) can be precisely controlled by adjusting its composition to achieve optimal anti-reflection performance at specific lithography wavelengths. Other optional materials include doped oxides, such as phosphosilicate glass (PSG) or boron-doped phosphosilicate glass (BPSG), but these are less commonly used. In some simplified processes, if the lithography window is large enough, this top oxide layer can be omitted, and lithography can be performed directly on the silicon nitride layer.

[0056] In some embodiments, in step one, the thickness of the pad oxide layer is 200 to 600 angstroms. This thickness of pad oxide layer can provide effective stress buffering between the silicon nitride layer and the silicon substrate, preventing the introduction of lattice defects in the silicon substrate due to stress mismatch during high-temperature oxidation.

[0057] In some embodiments, in step one, the thickness of the silicon nitride layer is 1100 angstroms to 1800 angstroms. This thickness of silicon nitride layer can effectively act as an oxygen barrier layer, protecting the underlying active silicon surface from oxidation during high-temperature thermal oxidation.

[0058] In some embodiments, in step one, the thickness of the top oxide layer is 1000 to 3000 angstroms. This thickness of top oxide layer can be used as a hard mask during subsequent etching of the silicon nitride layer and can improve the adhesion of the photoresist and the pattern fidelity.

[0059] In some embodiments, after the thermal oxidation step in step one, the process further includes removing the hard mask structure using a wet etching process. Removing the hard mask is to expose the silicon surface of the active region for subsequent device fabrication steps, such as ion implantation and gate formation.

[0060] In some embodiments, step one, the wet etching process includes: removing the top oxide layer and pad oxide layer using a hydrofluoric acid solution; and removing the silicon nitride layer using hot phosphoric acid. This is a standard wet removal scheme with high selectivity. Besides hydrofluoric acid and hot phosphoric acid, other selective wet etchants can be used, or a combination of dry and wet etching can be employed for removal. For example, buffered oxide etchant (BOE) can be used for more controlled oxide layer removal, or reactive ion etching (RIE) can be used to remove the silicon nitride layer; the choice of method depends on the selectivity of the underlying material and the required surface cleanliness.

[0061] Step 2: Before performing trench lithography, remove part of the back oxide film on the back side of the wafer to control the wafer warpage to a preset state.

[0062] Please refer to Figure 2 , Figure 2 The illustration schematically demonstrates the effect of step two on controlling wafer warpage. For example... Figure 2 As shown on the left, after the thermal oxidation in step one, the presence of a thick back oxide film (light blue layer in the image) can cause significant warping of the wafer (green layer in the image). Step two, which involves etching the back oxide film to remove part or all of it, effectively releases stress, allowing the wafer to return to a relatively flat state. Figure 2 As shown on the right, or adjust to a preset slight warp state.

[0063] In some embodiments, by controlling the amount of back oxide film removed in step two, the first warpage state of the wafer during the trench lithography step in step three is substantially consistent with the second warpage state during the contact hole lithography step in step four. For a better understanding of the technical effects of this application, please refer to... Figures 4 to 9 .

[0064] Please refer to Figure 4 , Figure 4 This demonstrates the ideal photolithography alignment. In this ideal state, the wafer (green layer) is perfectly flat, and the trenches (blue layer) and contact holes (yellow layer) are precisely aligned with the ideal exposure area (dark green area).

[0065] However, wafer warpage is unavoidable in actual production. Please refer to... Figure 5 and Figure 6 These two figures illustrate potential problems encountered in existing technologies. For example... Figure 5 As shown, if the wafer is flat during trench lithography, but warps during contact hole lithography due to the intermediate heat treatment, this will cause an overlay misalignment between the contact holes and the trenches. Conversely, if... Figure 6 As shown, if the wafer is warped during trench lithography and is made flat again during contact hole lithography, the inconsistency in the warping state between the two steps will still lead to overlay alignment deviation.

[0066] The core idea of ​​this application is precisely to solve the above-mentioned problems. Please refer to... Figure 7 , Figure 7 The diagram illustrates the alignment after applying the method of this application. Through precise control in step two, the wafer is placed in a preset "micro-warpage" state during trench lithography; subsequently, after a series of heat treatments in step four, the wafer is placed in a similarly consistent "micro-warpage" state during contact hole lithography. Because the warpage states (or relative deformations) of the two key lithography steps are matched, the alignment accuracy between the trenches and contact holes is significantly improved, systematically eliminating alignment deviations introduced by warpage mismatch.

[0067] Please refer to Figure 8 and Figure 9 These two figures demonstrate the beneficial effects of the method of the present invention from two dimensions: physical measurement and electrical performance.

[0068] Figure 8 This figure shows a comparison of experimental data on overlay alignment errors. Each square in the figure represents a region on the wafer, and the arrows indicate the overlay alignment error vector measured within that region. Figure 8 As shown on the left, the wafer (#21) using conventional processes exhibits significant, directionally divergent overlay alignment errors, particularly in the edge regions, with a maximum error (Max) reaching 0.16 micrometers. Figure 8 As shown on the right, the wafer (#5) optimized using the method of this invention has significantly reduced overlay alignment error across the entire wafer range, with the length of the error vector generally shortened and the directionality improved, and the maximum error value (Max) reduced to 0.04 micrometers.

[0069] Improvements in overlay alignment accuracy directly impact the electrical performance of the device. Please refer to... Figure 9This figure is a box plot of Delta VDSON parameters obtained through circuit probing (CP) testing. Delta VDSON is a key indicator characterizing the uniformity of on-state voltage drop in a device. A smaller value and a more concentrated distribution indicate better uniformity of device performance, indirectly reflecting the alignment of vias and trenches. In the figure, blue data points represent the conventional baseline process (BL), and red data points represent the process using the method of this invention. It is clearly seen from the figure that for multiple batches (LOT) of wafers, the average Delta VDSON value using the method of this invention (red data points) is lower, the data distribution is more convergent, the dispersion (e.g., + / -3 sigma range) is smaller, and there are almost no outliers exceeding the specification limits. This demonstrates that the method of this application can effectively improve overlay alignment, thereby significantly improving the uniformity of device electrical performance and process stability, ultimately increasing the overall product yield.

[0070] In some embodiments, in step two, the thickness of the removed back oxide film is between 3,000 angstroms and 13,000 angstroms. By precisely controlling the thickness of the removed oxide film, the stress balance inside the wafer can be finely adjusted, thereby adjusting the wafer warpage to a preset, slightly warped state. This state is an ideal warpage reference for subsequent trench lithography steps.

[0071] Step 3: After removing part of the back oxide film, perform trench photolithography and trench etching on the wafer to form trenches;

[0072] In some embodiments, prior to the trench lithography step in step three, a trench hard mask layer is deposited on the front side of the wafer.

[0073] In some embodiments, in step three, the trench hard mask layer is a silicon oxide layer. Besides silicon oxide, the trench hard mask layer can also be silicon nitride, silicon oxynitride, or a multilayer stacked structure composed of different dielectric materials, such as an oxide / nitride / oxide (ONO) structure, to meet the requirements of different trench depths and etching selectivity. The method for forming this layer can be various chemical vapor deposition (CVD) techniques, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or high-density plasma-enhanced chemical vapor deposition (HDP-CVD), or atomic layer deposition (ALD) techniques can be used to obtain better uniformity and conformal properties.

[0074] In some embodiments, in step three, the thickness of the trench hard mask layer is 3,000 to 5,000 angstroms.

[0075] Step 4: After the trenches are formed, the wafer is subjected to one or more heat treatments, and a contact hole photolithography step is performed to form contact holes.

[0076] Please refer to Figure 3 , Figure 3 This schematically illustrates the impact of subsequent thermal processing on wafer warpage. For example... Figure 3 As shown on the left, the wafer may be in a relatively flat or slightly warped state after trench formation. However, after undergoing one or more heat treatments in step four (e.g., gate oxidation, annealing, etc.), the wafer will warp again due to the introduction of new thin film stress on the front side, such as... Figure 3 As shown on the right. The key to this application is that this recurring warpage is predictable and incorporated into the process design, aiming to match its warpage state with that of the third-step photolithography step.

[0077] In some embodiments, one or more thermal treatments in step four include annealing or oxide growth processes. After trench formation and before contact hole lithography, the wafer typically undergoes a series of complex thermal treatment steps necessary for device performance. These thermal treatments are the primary driving force causing the wafer warpage state to evolve from "ditch lithography" to "contact hole lithography". These thermal treatments may include, but are not limited to:

[0078] Sacrificial oxidation and removal: After trench etching, a sacrificial oxidation process is typically performed to repair lattice damage to the trench sidewalls caused during etching and to passivate the surface. This sacrificial oxide layer is then removed by wet etching. This oxidation-removal cycle itself involves a high-temperature process.

[0079] Gate oxide growth: Growing a high-quality gate oxide layer on the inner wall of the trench is a key step in forming the IGBT trench gate structure. It is usually carried out in a high-temperature (e.g., 900°C to 1100°C) dry or humid oxygen environment, which is a significant source of heat budget.

[0080] Polysilicon deposition and doping activation annealing: Polysilicon is deposited on the gate oxide layer to form the gate electrode. After that, ion implantation is usually performed to dope the polysilicon, followed by high-temperature annealing (e.g., rapid thermal processing, RTP) to activate the dopant and reduce the resistivity of the polysilicon.

[0081] Interlayer dielectric (ILD) deposition and densification annealing: After the gate structure is formed, one or more interlayer dielectric layers (such as BPSG, PSG, or TEOS oxides) are deposited to achieve electrical isolation. These dielectric layers typically undergo a high-temperature annealing process (e.g., furnace tube annealing in a nitrogen atmosphere) after deposition to make the structure more compact and stable, and to expel moisture.

[0082] Each of the aforementioned heat treatment steps introduces new thin-film stress on the front side of the wafer or alters the stress state of the existing thin film, inevitably changing the overall warpage of the wafer. However, in the method of this application, these warpage changes caused by heat treatment are designed and anticipated. Since the wafer has been adjusted to a specific initial warpage state in step two, after this series of predictable heat treatment evolutions, when contact hole photolithography is finally performed, the wafer will reach a warpage state that is essentially consistent with that during trench photolithography, thereby achieving a systematic improvement in overlay alignment.

[0083] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of improving contact hole and trench overlay alignment in an insulated gate bipolar transistor, characterized by, At least comprising: Step one, performing at least one thermal oxidation process on the wafer to form a device structure on the front side of the wafer and simultaneously form a backside oxide film on the back side of the wafer; Step two, before performing a trench photolithography step, removing part of the backside oxide film on the back side of the wafer to control the wafer warpage to a preset state; Step three, after removing part of the backside oxide film, performing the trench photolithography step and trench etching step on the wafer to form a trench; Step four, after forming the trench, performing at least one thermal treatment on the wafer and performing a contact hole photolithography step to form a contact hole.

2. The method of claim 1, wherein: By controlling the amount of the backside oxide film removed in step two, the first wafer warpage state in the trench photolithography step of step three is consistent with the second wafer warpage state in the contact hole photolithography step of step four.

3. The method of claim 1, wherein: In step one, the at least one thermal oxidation process is a thermal oxidation step in a local oxidation process.

4. The method of claim 3, wherein: Before the thermal oxidation step, further comprising: defining a field region and an active region on the front side of the wafer by a patterning process, so that the field region exposes a silicon substrate.

5. The method of claim 4, wherein: In the thermal oxidation step of step one, a field oxide layer is formed on the exposed silicon substrate in the field region, and the backside oxide film is simultaneously formed on the back side of the wafer.

6. The method of claim 5, wherein: The thickness of the formed backside oxide film is 13000 angstroms to 16000 angstroms.

7. The method of claim 4, wherein: The patterning process comprises: sequentially forming a hard mask structure on the front side of the wafer; and patterning the hard mask structure by a photolithography and etching process.

8. The method of claim 7, wherein: The hard mask structure comprises a pad oxide layer, a silicon nitride layer, and a top oxide layer.

9. The method of claim 8, wherein: The thickness of the pad oxide layer is 200 angstroms to 600 angstroms.

10. The method of claim 8, wherein: The thickness of the silicon nitride layer is 1100 angstroms to 1800 angstroms.

11. The method of claim 8, wherein: The thickness of the top oxide layer is 1000 angstroms to 3000 angstroms.

12. The method of claim 7, wherein: After the thermal oxidation step of step one, further comprising: removing the hard mask structure by a wet etching process.

13. The method of claim 12, wherein: The wet etching process comprises: removing the top oxide layer and the pad oxide layer using a hydrofluoric acid solution; and removing the silicon nitride layer using hot phosphoric acid.

14. The method of claim 1, wherein: In step two, the thickness of the removed backside oxide film is 3000 angstroms to 13000 angstroms.

15. The method of claim 1, wherein: Before the trench photolithography step of step three, further comprising: depositing a trench hard mask layer on the front side of the wafer.

16. The method of claim 15, wherein: The trench hard mask layer is a silicon oxide layer.

17. The method of claim 16, wherein: The thickness of the trench hard mask layer is 3000 angstroms to 5000 angstroms.

18. The method for improving contact hole and trench overlay alignment in an insulated gate bipolar transistor of claim 1, wherein: The at least one thermal treatment comprises an annealing process or an oxide growth process.

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