Device with clock signal generator and method of sampling an input signal

Abstract

The embodiment of the invention discloses a device with a clock signal generator and a method for sampling an input signal. The device comprises a first clock signal generator, a second clock signal generator, an input signal generation circuit and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock delayed relative to the first clock signal. The input signal generation circuit includes a voltage signal generator and a functional circuit. The voltage signal generator generates a voltage signal. The functional circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples a value of the voltage signal at a rising edge or a falling edge of the second clock signal and provides the sampled value as an output signal to analyze one or more characteristics of the voltage signal based on the output signal.

Description

Technical Field

[0001] Embodiments of this application relate to devices having a clock signal generator and methods for sampling input signals. Background Technology

[0002] A sampling circuit captures (or samples) the value of an input signal at specific points in time, stores (or holds) the sampled value, and provides it along with the output signal. The sampled value corresponds to the instantaneous level of the input signal at these points in time. In one example, the sampling circuit receives an input signal and a clock signal, where the input signal is in analog form and is periodic. Simultaneously, the clock signal transitions between high and low states and has rising and falling edges. The sampling circuit samples the input signal at the rising (and / or falling) edge of the clock signal, holds these values, and produces an output signal that includes the sampled values. The output signal can be used for further processing, analysis, or transmission. Summary of the Invention

[0003] According to one aspect of this application, a device with a clock signal generator is provided, comprising a first clock signal generator, a second clock signal generator, an input signal generation circuit, and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock signal delayed relative to the first clock signal. Each of the first and second clocks transitions between a high state and a low state and has a rising edge and a falling edge. The input signal generation circuit includes a voltage signal generator and functional circuitry. The voltage signal generator generates a voltage signal having a period defined by the rising and falling edges of the first clock signal. The functional circuitry receives the voltage signal and performs one or more circuit functions. The input signal sampling circuitry samples the value of the voltage signal at the rising or falling edge of the second clock signal and provides the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0004] According to another aspect of this application, a device with a clock signal generator is provided, comprising a first clock signal generator, a second clock signal generator, and an input signal sampling circuit. The first clock signal generator includes a first clock signal selector and a first frequency divider. The first clock signal selector receives a first clock signal and a delayed version of the first clock signal, and selects the first clock signal as the output, while not selecting the first delayed version of the first clock. The second clock signal generator is configured to generate a third clock signal. The input signal sampling circuit samples the value of a voltage signal using the second and third clock signals, and provides the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0005] According to another aspect of the embodiments of this application, a method for sampling an input signal is provided, comprising: generating a first clock signal; dividing the frequency of the first clock signal to generate a second clock signal; generating a third clock signal; introducing a delay to the third clock signal; alternately selecting the third clock signal and a delayed version of the third clock signal to generate an output; reducing the frequency of the output to generate a fourth clock signal; receiving a voltage signal; obtaining a value of the voltage signal using the second clock signal and the fourth clock signal; and providing the value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal. Attached Figure Description

[0006] Various aspects of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings:

[0007] Figure 1 This is a schematic block diagram illustrating exemplary devices according to various embodiments of the present disclosure;

[0008] Figure 2 This is a schematic timing diagram illustrating exemplary relationships between signals of devices according to various embodiments of the present disclosure;

[0009] Figure 3 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0010] Figure 4 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure;

[0011] Figure 5 This is a schematic circuit / block diagram illustrating an exemplary clock signal generator of a device according to various embodiments of the present disclosure;

[0012] Figure 6 This is a schematic circuit / block diagram illustrating another exemplary clock signal generator of a device according to various embodiments of the present disclosure;

[0013] Figure 7 This is a schematic circuit diagram illustrating another exemplary clock signal generator according to various embodiments of the present disclosure; and

[0014] Figure 8 This is a flowchart illustrating an exemplary method for sampling an input signal according to an embodiment of the present disclosure. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] By sampling an input signal at specific points in time, discrete levels of the input signal (such as a periodic analog signal) can be obtained, for example, to assess its quality. The sampled values ​​of the input signal are then stored and provided along with the output signal. This output signal can then be fed to a signal analyzer (such as an oscilloscope) to identify one or more characteristics of the input signal, such as amplitude, frequency, and waveform shape. For example, the sampling circuit receives first and second clock signals, each transitioning between high and low states and having rising and falling edges. The rising edge (and / or falling edge) of the first clock signal triggers or initiates sampling of the input signal. The sampling circuit obtains the value of the input signal at the rising edge (and / or falling edge) of the second clock signal. The second clock signal is delayed relative to the first clock signal by at least a predetermined delay (Δt). However, the clock signal generator may not produce a sufficiently small delay (Δt). If the delay (Δt) is too large, the value obtained by the sampling circuit may not be an accurate representation of the input signal.

[0017] In some examples described herein, the systems and methods include devices with a clock signal generator that generates a second clock signal by alternating between an original clock signal and its delayed version. This approach can produce a sufficiently small delay (Δt) such that the ratio of the period of the second clock signal (e.g., 2.13 ns) to the delay (Δt) (e.g., 23 ps) exceeds 50 (e.g., reaching 92.61). Therefore, the frequency of the output signal is reduced to a lower value (e.g., 5.1 MHz) compared to the higher frequency of the input signal (e.g., 469 MHz). This reduction allows the output signal to accurately represent the input signal, thereby facilitating precise analysis of the input signal.

[0018] Figure 1 This is a schematic block diagram illustrating an exemplary device 100 according to various embodiments of the present disclosure. The example device 100 uses one or more clock signals of its own, such as a clock signal (CLK). TRIG CLK SAMP), to acquire the value of the input signal at a specific point in time, such as a voltage signal (V). SENSE ).like Figure 1 As shown, device 100 includes a clock signal generation circuit 110 and an input signal sampler 120. The clock signal generation circuit 110 includes a circuit for generating a first (or trigger) clock signal (CLK). TRIG A first clock signal generator 130 and a second clock signal generator 140 that generate a second (or sampled) clock signal, wherein the second (or sampled) clock signal has a frequency response greater than that of the trigger clock signal (CLK). TRIG Longer cycles. Each clock signal (CLK) TRIG CLK SAMP It transitions between high and low states and has rising and falling edges.

[0019] Input signal sampler 120 obtains the clock signal (CLK) TRIG CLK SAMP The determined voltage signal (V) SENSE The value of ). For example, the input signal sampler 120 includes an input signal generation circuit 150 and an input signal sampling circuit 160. The input signal generation circuit 150 generates an input signal (V) in analog form. SENSE The input signal has a trigger clock signal (CLK) TRIG The period is defined by the rising and falling edges of the input signal (V). For example, the input signal (V) SENSE The period of ) is respectively in the trigger clock signal (CLK) TRIG The input signal generation circuit 160 begins and ends at the rising (or falling) edge and falling (or rising) edge. In this exemplary embodiment, the input signal generation circuit 160 performs one or more circuit functions.

[0020] The input signal sampling circuit 160 samples the clock signal (CLK). SAMP The rising edge (and / or falling edge) of the input signal (V) is captured (or sampled) SENSE The values ​​of ) are stored (or retained), and they are collectively provided as the output signal (V). SUB The sampled value corresponds to the input signal (V). SENSE The instantaneous level at these points in time. The output signal (V) can be analyzed using a signal analyzer (such as an oscilloscope, spectrum analyzer, voltmeter, any other device capable of measuring voltage signals, or a combination thereof). SUB One or more characteristics of the input signal (V) are used to evaluate the input signal (V). SENSE (quality)

[0021] In this exemplary embodiment, the sampling clock signal (CLK) SAMP ) relative to the trigger clock signal (CLK) TRIGIt is delayed by at least one delay (Δt). For example, Figure 2 This illustrates the clock signal (CLK) of a device (e.g., device 100) according to various embodiments of the present disclosure. TRIG CLK SAMP ) and input signal (V SENSE V SUB A schematic sequence diagram illustrating the exemplary relationship between ).

[0022] like Figure 2 As shown, each clock signal (CLK) TRIG CLK SAMP The input signal (V) transitions between high and low states and has both rising and falling edges. SENSE It is in analog form, and its period is determined by the trigger clock signal (CLK). TRIG The rising and falling edges of an input signal are defined. For example, the input signal (V) SENSE The period of ) is respectively in the trigger clock signal (CLK) TRIG The rising (or falling) edge and falling (or rising) edge of the input signal (V) mark its start and end. In other words, the input signal (V) begins and ends at its rising edge (or falling edge). SENSE The period of the trigger clock signal (CLK) is the period of the trigger clock signal. TRIG Twice the cycle. In some embodiments, the trigger clock signal (CLK) TRIG The rising edge of the input signal (V) triggers or starts the input signal. SENSE Sampling of the clock signal (CLK). In some such embodiments, sampling of the clock signal (CLK) is performed. SAMP The rising edge of the input signal (V) SENSE Sampling is performed. In other embodiments, a trigger clock signal (CLK) is used. TRIG The rising and / or falling edges of the input signal (V) trigger or start the input signal. SENSE The sampling of the input signal (V) and the sampling of the input signal (V) SENSE ) at the sampling clock signal (CLK) SAMP Samples are taken at the rising and / or falling edges of the sample.

[0023] In this exemplary embodiment, the sampling clock signal (CLK) SAMP ) relative to the trigger clock signal (CLK) TRIG The delay is achieved by altering the delay, which gradually increases over multiple cycles. For example, the clock signal (CLK) TRIG CLK SAMP The rising edge of the sampling clock signal (CLK) is separated by a multiple of the delay (Δt), such as Δt, 2Δt, 3Δt, etc. Similarly, the sampling clock signal (CLK) SAMP The falling edge of the trigger clock signal (CLK) relative to the trigger clock signal TRIG The falling edge of the input signal (V) is also delayed by a different delay. This progressive delay allows the sampling process to proceed along the input signal (V).SENSE The capture of values ​​is distributed to ensure that no two sampling points are redundant or too close together. As a result, the voltage signal (V...) is captured... SENSE Compared to higher frequencies, the output signal (V) SUB The frequency is reduced to a lower frequency without sacrificing the input signal (V). SENSE The accuracy of the information captured.

[0024] Figure 3 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure. Figure 3 As shown, example device 300, such as device 100, includes a clock signal generation circuit 310 and an input signal sampler 320. The clock signal generation circuit 310 includes a generator for generating a trigger clock signal (CLK). TRIG The first clock signal generator 330 and the generator that generates the sampling clock signal (CLK) SAMP The second clock signal generator 340 samples the clock signal with a frequency greater than that of the trigger clock signal (CLK). TRIG Longer cycles. Each clock signal (CLK) TRIG CLK SAMP It transitions between high and low states and has rising and falling edges.

[0025] In this exemplary embodiment, the trigger clock signal generator 330 includes a first clock signal source 330a and a first frequency divider 330b. The clock signal source 330a receives an enable signal (START) at its first input (RST) and a first control signal (SEL1) at its second input. The enable signal (START) enables (e.g., when it is high) the generation of a first high-frequency clock signal (CLK1) at the output of the clock signal source 330a, or disables it when it is low. The frequency divider 330b receives the high-frequency clock signal (CLK1) from the clock signal source 330a, divides the high-frequency clock signal by a divisor (N) received at its input, and generates a trigger clock signal (CLK1) at its output. TRIG ).

[0026] In some embodiments, the control signal (SEL) is set to a first logic (e.g., low) state and never to a second logic (e.g., high) state, which is the inverted version of the first logic state. In this particular embodiment, the trigger clock signal (CLK) TRIG It has a period that remains essentially constant over time, in a manner that will be described in further detail below.

[0027] The sampling clock signal generator 340 has a similar structure to the trigger clock signal generator 330. For example, the sampling clock signal generator 340 includes a second clock signal source 340a and a second frequency divider 340b. The clock signal source 340a receives an enable signal (START) at its first input (RST) and a second control signal (SEL2) at its second input. The enable signal (START) enables (e.g., when it is high) the generation of a second high-frequency clock signal (CLK2) at the output of the clock signal source 340a, or disables it when it is low. The frequency divider 340b receives the high-frequency clock signal (CLK2) from the clock signal source 340a, divides the high-frequency clock signal by the divisor (N) received at its input, and generates the sampling clock signal (CLK2) at its output. SAMP ).

[0028] In some embodiments, the sampling clock signal (CLK) SAMP ) is used as a control signal (SEL2). In this particular embodiment, the sampling clock signal (CLK) SAMP ) relative to the trigger clock signal (CLK) TRIG The delay is a multiple of the delay (Δt), and the manner in which it is delayed will be described in further detail below.

[0029] Input signal sampler 320 pairs of clock signals (CLK) TRIG CLK SAMP The determined voltage signal (V) SENSE The input signal sampler 320 includes an input signal generation circuit 350 and an input signal sampling circuit 360. The input signal generation circuit 350 includes a voltage signal generator 350a and a functional circuit 350b. The voltage signal generator 350a generates an input signal (V...). SENSE For example, a voltage signal in analog form, which has a trigger clock signal (CLK) TRIG The voltage signal generator 350a is defined by the rising and falling edges of the voltage source and is applied across the functional circuit 350b. In some embodiments, the voltage signal generator 350a includes a bandgap reference voltage generator, a voltage regulator, a power supply, a digital-to-analog converter (DAC), a voltage-controlled oscillator (VCO), a charge pump, any other circuitry for generating a voltage signal, or a combination thereof. In an alternative embodiment, the voltage signal generator 350a is external to the device 300.

[0030] Functional circuit 350b receives voltage signal (V) SENSEIt performs one or more circuit functions. In some embodiments, functional circuit 350b is a central processing unit (CPU), a memory device, a signal amplifier, an analog-to-digital converter (ADC) circuit, a logic circuit, other circuits performing predetermined circuit functions, or a combination thereof. In an alternative embodiment, functional circuit 350b is external to device 300.

[0031] The input signal sampling circuit 360 samples the clock signal (CLK). SAMP The voltage signal (V) is captured (or sampled) at the rising edge (and / or falling edge) of the signal. SENSE The values ​​of ) are stored (or retained), and they are collectively provided as the output signal (V). SUB The sampled value corresponds to the voltage signal (V). SENSE The instantaneous voltage levels at these points in time. The output signal (V) can be analyzed using a signal analyzer (such as an oscilloscope, spectrum analyzer, voltmeter, any other device capable of measuring voltage signals, or a combination thereof). SUB One or more characteristics of a voltage signal (V) are used to evaluate the voltage signal (V). SENSE (quality)

[0032] Based on the above description, the sampling clock signal generator 340 has a structure that is substantially the same as that of the trigger clock signal generator 330. This similarity simplifies the design and manufacture of the device 300.

[0033] Figure 4 This is a schematic block diagram illustrating another exemplary device according to various embodiments of the present disclosure. Figure 4 As shown, example device 400, such as device 300, includes a clock signal generation circuit 410 and an input signal sampler 420. The clock signal generation circuit 410 includes a generator for a trigger clock signal (CLK). TRIG The first clock signal generator 430 and the generator that generates the sampling clock signal (CLK) SAMP The second clock signal generator 440 samples the clock signal (CLK). SAMP The period of the trigger clock signal (CLK) is greater than that of the trigger clock signal (CLK). TRIG ) length. Each clock signal (CLK) TRIG CLK SAMP It transitions between high and low states and has rising and falling edges.

[0034] In this exemplary embodiment, the trigger clock signal generator 430 includes an oscillator 430a, a first delay circuit 430b, a clock signal selector 430c, a frequency divider 430d, a second delay circuit 430e, and a selection signal generator 430f. The oscillator 430a receives an enable signal (START) at its input (RST), which (e.g., when it is high) enables the generation of an oscillator signal (CLK) at its output (OUT). TRIG '), or disable it when it is in a low state. The delay circuit 430b receives the oscillator signal (CLK) from the oscillator 430a. TRIG '), for the oscillator signal (CLK) received therefrom TRIG A first delay is introduced, and an oscillator signal (CLK) is generated at its output terminal. TRIG The first delayed version of ').

[0035] Clock signal selector 430d receives oscillator signal (CLK) from oscillator 430a. TRIG '), receives oscillator signal (CLK) from delay circuit 430b. TRIG The first delayed version of ') selects the oscillator signal (CLK) in response to the first selection signal (S1) received at its input. TRIG ') and oscillator signal (CLK) TRIG One of the first delayed versions of ') and provides a high-frequency clock signal (CLK1) at its output, which corresponds to the selected oscillator signal (CLK). TRIG ') and oscillator signal (CLK) TRIG One of the first delayed versions of ').

[0036] Frequency divider 430d receives a high-frequency clock signal (CLK1) from clock signal selector 430c and divides it by the divisor (N) received at its input, thereby triggering clock signal generator 430 to generate a trigger clock signal (CLK). TRIG The frequency divider 430d provides a trigger clock signal (CLK) at its output. TRIG ).

[0037] Delay circuit 430e receives oscillator signal (CLK) from oscillator 430a. TRIG '), for the oscillator signal (CLK) received therefrom TRIG A second delay is introduced, and an oscillator signal (CLK) is generated. TRIG The second delayed version of '). Select signal generator 430f receives oscillator signal (CLK) from delay circuit 430e. TRIGThe second delayed version of ') generates a selection signal (S1) in response to the control signal (SEL1) at its input, independent of the received oscillator signal (CLK). TRIG The second delayed version of '). In some embodiments, the control signal (SEL1) is set to a first logic (e.g., low) state and never set to a second logic (e.g., high) state, which is the inverted version of the first logic state. In this particular embodiment, the control signal (SEL1) controls the clock signal selector 430c to always select the oscillator signal (CLK). TRIG Instead of selecting its delayed version, the clock signal (CLK) is triggered. TRIG It has a period that remains basically constant over time.

[0038] The sampling clock signal generator 440 has a similar structure to the trigger clock signal generator 430. For example, the sampling clock signal generator 440 includes an oscillator 440a, a first delay circuit 440b, a clock signal selector 440c, a frequency divider 440d, a second delay circuit 440e, and a selection signal generator 440f. The oscillator 440a receives an enable signal (START) at its input (RST), which (e.g., when it is high) enables the generation of an oscillator signal (CLK) at its output (OUT). SAMP '), or disable it when it is in a low state. Delay circuit 430b receives oscillator signal (CLK) from oscillator 440a. SAMP '), for the oscillator signal (CLK) received therefrom SAMP A first delay is introduced, and an oscillator signal (CLK) is generated at its output. SAMP The first delayed version of ').

[0039] Clock signal selector 440d receives oscillator signal (CLK) from oscillator 440a. SAMP '), receives oscillator signal (CLK) from delay circuit 440b. SAMP The first delayed version of ') selects the oscillator signal (CLK) in response to the second selection signal (S2) received at its input. SAMP ') and oscillator signal (CLK) SAMP One of the second delayed versions of ') and provides a high-frequency clock signal (CLK2) at its output, which corresponds to the selected oscillator signal (CLK). SAMP ') and oscillator signal (CLK) SAMP One of the first delayed versions of ').

[0040] Frequency divider 440d receives a high-frequency clock signal (CLK2) from clock signal selector 440c and divides it by the divisor (N) received at its input, thereby generating a sampled clock signal (CLK2) from sampled clock signal generator 440. SAMP The frequency divider 440d provides a sampling clock signal (CLK) at its output. SAMP ).

[0041] Delay circuit 440e receives oscillator signal (CLK) from oscillator 440a. SAMP '), for the oscillator signal (CLK) received therefrom SAMP A second time delay is introduced, and an oscillator signal (CLK) is generated. SAMP The second delayed version of '). The selection signal (S2) generator 440f receives the oscillator signal (CLK) from the delay circuit 440e. SAMP The second delayed version of ') generates a selection signal (S2) in response to the control signal (SEL2) at its input, depending on the received oscillator signal (CLK). SAMP The second delayed version of '). For example, the sampling clock signal (CLK) SAMP ') is used as the control signal (SEL2). When the oscillator signal (CLK) SAMP When the second delayed version of the oscillator signal is high, and when the control signal (SEL2) transitions from low to high and returns to low, the clock signal selector 440d selects the first delayed version of the oscillator signal as the high-frequency clock signal (CLK2). Otherwise, for example, when the oscillator signal (CLK) is high, the clock signal selector 440d selects the first delayed version of the oscillator signal as the high-frequency clock signal (CLK2). SAMP When the second delayed version of the clock signal (CLK) and the control signal (SEL2) are both low, the clock signal selector 440d selects the oscillator signal (CLK). SAMP ') is used as a high-frequency clock signal (CLK2).

[0042] Because the clock signal selector 440c alternately selects the oscillator signal (CLK) SAMP ') and its delayed version serve as its high-frequency clock signal (CLK2), so the sampling clock signal (CLK) SAMP ) relative to the trigger clock signal (CLK) TRIG The delay is a multiple of the delay (Δt), as previously stated.

[0043] Input signal sampler 420 pairs of clock signals (CLK) TRIG CLK SAMP The determined voltage signal (V) SENSESampling is performed. For example, the input signal sampler 420 includes an input signal generation circuit 450 and an input signal sampling circuit 460. The input signal generation circuit 420a includes an input signal generator 450a and a function signal 450b. The input signal generator generates an input signal (V... SENSE For example, a voltage signal, which is in analog form and has a trigger clock signal (CLK). TRIG The period is defined by the rising and falling edges of the voltage signal (V). SENSE When applied across functional circuit 450b, functional circuit 450a performs one or more circuit functions. In an alternative embodiment, at least one of voltage signal generator 450a and functional circuit 450b is external to device 400.

[0044] The input signal sampling circuit 420b samples the clock signal (CLK). SAMP The voltage signal (V) is captured (or sampled) at the rising edge (and / or falling edge) of the signal. SENSE The values ​​of ) are stored (or retained), and they are collectively provided as the output signal (V). SUB The sampled value corresponds to the voltage signal (V). SENSE The instantaneous voltage levels at these points in time can be analyzed. The output signal (V) can be analyzed. SUB To evaluate the voltage signal (V) SENSE (quality)

[0045] Based on the above description, the sampling clock signal generator 440 has a structure that is substantially the same as that of the trigger clock signal generator 430. This similarity simplifies the design and manufacture of the device 400.

[0046] Figure 5 This is a schematic block diagram / circuit diagram illustrating another exemplary clock signal generator according to various embodiments of the present disclosure. Figure 5 As shown, the example clock signal generator 500 (e.g., trigger clock signal generators 130, 330, 430) includes an oscillator 510, a first delay circuit 520, a clock signal selector 530, a frequency divider 540, a second delay circuit 550, and a selection signal generator 560. The oscillator 510 receives an enable signal (START) at its input (RST), which (e.g., when it is high) enables the generation of an oscillator signal (CLK) at its output (OUT). TRIG The oscillator 510 can be disabled when it is in a low state, or when it is in a low state. In this exemplary embodiment, the oscillator 510 includes a ring oscillator implemented by an odd number of inverting stages connected in the feedback loop. In alternative embodiments, the oscillator 510 includes a crystal oscillator, a voltage-controlled oscillator (VCO), a phase-locked loop (PLL), an LC oscillator, any other suitable oscillator, or a combination thereof.

[0047] Delay circuit 520 receives oscillator signal (CLK) from oscillator 510. TRIG '), for the oscillator signal (CLK) received therefrom TRIG A first delay is introduced, and an oscillator signal (CLK) is generated at its output. TRIG The first delayed version of '). In some embodiments, the delay circuit 520 includes one or more buffer circuits.

[0048] Clock signal selector 530 receives oscillator signal (CLK) from oscillator 510. TRIG '), receives oscillator signal (CLK) from delay circuit 520. TRIG The first delayed version of ') always selects the oscillator signal (CLK) TRIG '), that is, never select its delayed version and provide an oscillator signal (CLK) at its output. TRIG Therefore, the trigger clock signal (CLK) is activated. TRIG The clock signal selector 530 has a period that remains substantially constant over time. In this exemplary embodiment, the clock signal selector 530 includes a multiplexer having a first input terminal connected to the output terminal of the oscillator 510 and a second input terminal connected to the output terminal of the delay circuit 520. The multiplexer connects its first input terminal to its output terminal in response to a selection signal (S1).

[0049] Frequency divider 540 receives oscillator signal (CLK) from clock signal selector 530. TRIG '), and the oscillator signal (CLK) TRIG The frequency of the clock signal is divided by the divisor (N) received at its input, thereby triggering the clock signal generator 500 to generate a trigger clock signal (CLK). TRIG The frequency divider 540 provides a trigger clock signal (CLK) at its output. TRIG ).

[0050] Delay circuit 550 receives oscillator signal (CLK) from oscillator 510. TRIG '), for the oscillator signal (CLK) received therefrom TRIG A second time delay is introduced, and an oscillator signal (CLK) is generated. TRIG The second delayed version of '). In some embodiments, the delay circuit 550 includes one or more buffer circuits.

[0051] Select signal generator 560 to receive oscillator signal (CLK) from delay circuit 550. TRIG The second delayed version of ') generates a selection signal (S1) at its input in response to a control signal (SEL), and thus receives an oscillator signal (CLK).TRIG The second delayed version of ') is irrelevant. As a result, the trigger clock signal (CLK) TRIG It has a period that remains basically constant over time.

[0052] Figure 6 This is a schematic block diagram / circuit diagram illustrating another exemplary clock signal generator according to various embodiments of the present disclosure. Figure 6 As shown, the example clock signal generator 600 (e.g., sampling clock signal generators 140, 340, 440) includes an oscillator 610, a first delay circuit 620, a clock signal selector 630, a frequency divider 640, a second delay circuit 650, and a selection signal generator 660. The oscillator 610 receives an enable signal (START) at its input (RST), which (e.g., when it is high) enables the generation of an oscillator signal (CLK) at its output (OUT). SAMP The oscillator 610 may be disabled when it is in a low state. In this exemplary embodiment, the oscillator 610 includes a ring oscillator implemented by an odd number of inverting stages connected in a feedback loop. In an alternative embodiment, the oscillator 610 includes a crystal oscillator, VCO, PLL, LC oscillator, any other suitable oscillator, or a combination thereof.

[0053] Delay circuit 620 receives oscillator signal (CLK) from oscillator 610. SAMP '), for the oscillator signal (CLK) received therefrom SAMP A first delay is introduced, and an oscillator signal (CLK) is generated at its output. SAMP The first delayed version of '). In some embodiments, the delay circuit 520 includes one or more buffer circuits.

[0054] Clock signal selector 630 receives oscillator signal (CLK) from oscillator 610. SAMP '), receives oscillator signal (CLK) from delay circuit 620. SAMP The first delayed version of ') alternately selects the oscillator signal (CLK) SAMP ') and oscillator signal (CLK) SAMP The clock signal selector 630 includes a first delayed version of the clock signal selector 610 and provides them as outputs at its output terminal. In this exemplary embodiment, the clock signal selector 630 includes a multiplexer having a first input terminal connected to the output terminal of the oscillator 610 and a second input terminal connected to the output terminal of the delay circuit 620. The multiplexer connects its first input terminal or second input terminal to its output terminal in response to the selection signal (S2).

[0055] Frequency divider 640 receives the output of clock signal selector 630 and divides (or reduces) its frequency by the divisor (N) received at its input, thereby generating a sampling clock signal (CLK) by sampling clock signal generator 600. SAMP The frequency divider 640 provides a sampling clock signal (CLK) at its output. SAMP ).

[0056] Delay circuit 650 receives oscillator signal (CLK) from oscillator 610. SAMP '), for the oscillator signal (CLK) received therefrom SAMP A second time delay is introduced, and an oscillator signal (CLK) is generated. SAMP The second delayed version of '). In this exemplary embodiment, the delay circuit 650 includes one or more buffer circuits.

[0057] Select signal generator 660 to receive oscillator signal (CLK) from delay circuit 650. SAMP The second time delay of ') and its input response to the sampling clock signal (CLK) SAMP This generates a selection signal (S2). Therefore, the sampling clock signal (CLK) is... SAMP ) relative to the trigger clock signal (CLK) TRIG It delays by a factor of the delay (Δt).

[0058] Figure 7 This is a schematic circuit diagram illustrating another exemplary clock signal generator according to various embodiments of the present disclosure. Figure 7 As shown, an example clock signal generator 700 (e.g., clock signal generators 130, 140, 330, 340, 430, 440) includes an oscillator 710, a first delay circuit 720, a clock signal selector 730, a second delay circuit 750, and a selection signal generator 760. The oscillator 710 (e.g., oscillators 510, 610) includes a ring oscillator implemented by an odd number of inverting stages connected in a feedback loop. In alternative embodiments, the oscillator 710 includes a crystal oscillator, a VCO, a PLL, an LC oscillator, any other suitable oscillator, or a combination thereof.

[0059] A delay circuit 720 (e.g., delay circuits 520, 620) is connected between the oscillator 710 and a first input terminal of a clock signal selector 730 (e.g., clock signal selectors 530, 630). In this exemplary embodiment, the delay circuit 720 includes one or more buffer circuits. The clock signal selector 730 also has a second input terminal connected to the output terminal of the oscillator 710. In this exemplary embodiment, the clock signal selector 730 includes a multiplexer.

[0060] A delay circuit 750 (e.g., delay circuits 550, 650) is connected between the output of the oscillator 710 and the selection signal generator 760 (e.g., selection signal generators 560, 660). In this exemplary embodiment, the delay circuit 720 includes one or more buffer circuits. The selection signal generator 760 controls the operation of the clock signal generator 730. In some embodiments, the selection signal generator 760 includes one or more flip-flops and one or more logic gates. In other embodiments, various configurations of the selection signal generator 760 are contemplated.

[0061] Figure 8 This is a flowchart of an exemplary method 800 for sampling an input signal according to embodiments of the present disclosure. Further reference is made for ease of understanding. Figures 1-7 Example method 800 is described. It should be understood that method 800 is applicable to... Figures 1-7 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 800, additional operations may be provided before, during, and after method 800, and some of the operations described below may be replaced or eliminated.

[0062] In operation 810, the device (e.g., device 100, 300-700) generates a first clock signal, such as a trigger clock signal (CLK) whose period remains substantially constant over time. TRIG ).

[0063] In operation 820, the device generates a second clock signal, for example, relative to the trigger clock signal (CLK). TRIG The sampling clock signal (CLK) is delayed by a multiple of the delay (Δt). SAMP Each clock signal (CLK) TRIG CLK SAMP It transitions between high and low states and has rising and falling edges.

[0064] In operation 830, the device generates an input signal, such as a voltage signal (V). SENSE Its period is determined by the trigger clock signal (CLK). TRIG The rising and falling edges of the sampling clock signal (CLK) are defined. In operation 840, the device samples the clock signal (CLK). SAMP The voltage signal (V) is captured (or sampled) at the rising edge (and / or falling edge) of the signal. SENSE The voltage value of ) is stored (or retained), and these sampled values ​​are used together to provide the output signal (V). SUB ).

[0065] In one embodiment, a device having a clock signal generator includes a first clock signal generator, a second clock signal generator, an input signal generation circuit, and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock signal delayed relative to the first clock signal. Each of the first and second clocks transitions between a high state and a low state and has a rising edge and a falling edge. The input signal generation circuit includes a voltage signal generator and functional circuitry. The voltage signal generator generates a voltage signal having a period defined by the rising and falling edges of the first clock signal. The functional circuitry receives the voltage signal and performs one or more circuit functions. The input signal sampling circuitry samples the value of the voltage signal at the rising or falling edge of the second clock signal and provides the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0066] In some embodiments, the second clock signal is delayed by a number of delays relative to the first clock signal.

[0067] In some embodiments, the first rising edge of the first clock signal and the first rising edge of the second clock signal are separated by a first delay; and the second rising edge of the first clock signal and the second rising edge of the second clock signal are separated by a second delay longer than the first delay.

[0068] In some embodiments, the duration of the delay gradually increases over time.

[0069] In some embodiments, the period of the voltage signal is twice the period of the first clock signal.

[0070] In some embodiments, the first clock signal generator includes: a clock signal selector configured to receive a third clock signal and a delayed version of the third clock, and select the third clock as the output, but never select the delayed version of the third clock; and a frequency divider configured to reduce the frequency of the output and generate the first clock signal.

[0071] In some embodiments, the clock signal selector is configured to select a third clock signal in response to a selection signal (S1), wherein the selection signal is set to a first logic state and is never set to a second logic state, which is the inverse version of the first logic state.

[0072] In some embodiments, the second clock signal generator includes: a clock signal selector configured to receive a fourth signal and a delayed version of a fourth clock signal, alternately select the delayed version of the fourth signal and the fourth clock signal, and generate an output; and a frequency divider configured to reduce the frequency of the output and generate a second clock signal.

[0073] In some embodiments, the clock signal selector is configured to alternately select a fourth signal and a delayed version of the fourth clock signal in response to a second clock signal.

[0074] In another embodiment, a device with a clock signal generator includes a first clock signal generator, a second clock signal generator, and an input signal sampling circuit. The first clock signal generator includes a first clock signal selector and a first frequency divider. The first clock signal selector receives a first clock signal and a delayed version of the first clock signal, and selects the first clock signal as the output, while not selecting the first delayed version of the first clock. The second clock signal generator is configured to generate a third clock signal. The input signal sampling circuit samples the value of a voltage signal using the second and third clock signals and provides the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0075] In some embodiments, the first clock signal selector is further configured to select a first clock signal in response to a selection signal; and the selection signal is set to a first logic state and never set to a second logic state, the second logic state being the inverse version of the first logic state.

[0076] In some embodiments, the first clock signal generator further includes: an oscillator configured to generate a first clock signal; a first delay circuit connected between the oscillator and the first clock signal selector and configured to generate a delayed version of the first clock signal; a second delay circuit configured to generate a second delayed version of the first clock signal; and a selection signal generator connected between the second delay circuit and the first clock signal selector and configured to generate a selection signal independently of the second delayed version of the first clock signal.

[0077] In some embodiments, the second clock signal selector is further configured to alternately select a fourth clock signal and a delayed version of the fourth clock in response to a third clock signal.

[0078] In some embodiments, the second clock signal generator further includes: an oscillator configured to generate a fourth clock signal; a first delay circuit connected between the oscillator and the second clock signal selector and configured to generate a delayed version of the fourth clock signal; a second delay circuit configured to generate a second delayed version of the fourth clock signal; and a selection signal generator connected between the second delay circuit and the second clock signal selector and configured to generate a selection signal based on the second delayed version of the fourth clock signal.

[0079] In another embodiment, a method for sampling an input signal includes: generating a first clock signal; dividing the frequency of the first clock signal to generate a second clock signal; generating a third clock signal; introducing a delay to the third clock signal; alternately selecting the third clock signal and a delayed version of the third clock signal to generate an output; reducing the frequency of the output to generate a fourth clock signal; receiving a voltage signal; obtaining a value of the voltage signal using the second clock signal and the fourth clock signal; and providing the value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

[0080] In some embodiments, the method further includes: introducing a delay to the first clock signal before dividing the frequency of the first clock signal, and selecting the first clock signal as the output instead of selecting a delayed version of the first clock signal.

[0081] In some embodiments, the method further includes: in response to a fourth clock signal, alternately selecting a third clock signal and a delayed version of the third clock signal.

[0082] In some embodiments, the method further includes: introducing a delay to the first clock signal before dividing the frequency of the first clock signal; selecting the first clock signal as an output in response to the selection signal when the selection signal is in a first logic state; and setting the selection signal to the first logic state and never setting it to a second logic state, the second logic state being an inverted version of the first logic state.

[0083] In some embodiments, the method further includes: generating a voltage signal; applying the voltage signal to a functional circuit; and the functional circuit performing one or more circuit functions.

[0084] In some embodiments, the method further includes introducing a delay into a third clock signal, wherein the ratio of the period of the third clock signal to the delay is equal to or greater than 50.

[0085] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A device having a clock signal generator, comprising: A first clock signal generator is configured to generate a first clock signal; A second clock signal generator is configured to generate a second clock that is delayed relative to the first clock signal, wherein each of the first clock and the second clock transitions between a high state and a low state and has a rising edge and a falling edge. The input signal generation circuit includes: A voltage signal generator is configured to generate a voltage signal having a period defined by the rising and falling edges of the first clock signal; and Functional circuitry, configured to receive the voltage signal and perform one or more circuit functions; and An input signal sampling circuit is configured to sample the value of the voltage signal at the rising or falling edge of the second clock signal and provide the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

2. The device according to claim 1, wherein, The second clock signal is delayed by a number of delays relative to the first clock signal.

3. The device according to claim 2, wherein: The first rising edge of the first clock signal and the first rising edge of the second clock signal are separated by a first delay; and The second rising edge of the first clock signal and the second rising edge of the second clock signal are separated by a second delay that is longer than the first delay.

4. The device according to claim 2, wherein, The duration of the delay gradually increases over time.

5. The device according to claim 1, wherein, The first clock signal generator includes: A clock signal selector is configured to receive a third clock signal and a delayed version of the third clock, and select the third clock as the output, but never select the delayed version of the third clock; and A frequency divider is configured to reduce the frequency of the output and generate the first clock signal.

6. The device according to claim 5, wherein, The clock signal selector is configured to select the third clock signal in response to a selection signal, wherein the selection signal is set to a first logic state and is never set to a second logic state, the second logic state being the inverse version of the first logic state.

7. The device according to claim 1, wherein, The second clock signal generator includes: A clock signal selector is configured to receive a fourth signal and a delayed version of the fourth clock signal, alternately select the fourth signal and the delayed version of the fourth clock signal, and generate an output; and A frequency divider is configured to reduce the frequency of the output and generate the second clock signal.

8. A device having a clock signal generator, comprising: The first clock signal generator includes: The first clock signal selector is configured as follows: Receive a first clock signal and a delayed version of the first clock signal; and The first clock signal is selected as the output, instead of the first delayed version of the first clock; and A first frequency divider is configured to reduce the frequency of the output and generate a second clock signal; a second clock signal generator is configured to generate a third clock signal; and An input signal sampling circuit is configured to sample the value of a voltage signal using the second clock signal and the third clock signal, and provide the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

9. A method for sampling an input signal, the method comprising: Generate the first clock signal; Divide the frequency of the first clock signal to generate a second clock signal; Generate a third clock signal; A delay is introduced into the third clock signal; Alternately select the third clock signal and its delayed version to generate the output; Reduce the frequency of the output to generate a fourth clock signal; Receive voltage signal; The value of the voltage signal is obtained using the second clock signal and the fourth clock signal; as well as The value is provided as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

10. The method of claim 9, further comprising: A delay is introduced into the first clock signal before the frequency of the first clock signal is divided; When the selection signal is in the first logic state, the first clock signal is selected as the output in response to the selection signal. as well as The selection signal is set in the first logic state and never in the second logic state, which is the inverse version of the first logic state.

Images