DFT resource allocation prediction method, apparatus, electronic equipment and storage medium

Abstract

The present disclosure provides a DFT resource configuration prediction method and device, electronic equipment and storage medium, belonging to the technical field of electronic design automation. The method comprises the following steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on a chip planning area of the target chip and a predicted non-digital logic function area; correcting the effective digital logic layout area according to a utilization factor corresponding to a physical design constraint of the target chip to obtain an available standard cell layout capacity; generating a timing element quantity prediction interval of the target chip through a logic depth mapping model according to the standard cell layout capacity and the reference device density; and generating a design for test (DFT) architecture configuration parameter of the target chip according to the timing element quantity prediction interval. The chip register quantity can be quickly and accurately predicted and the DFT architecture configuration parameter can be generated at an early stage of chip design.

Description

Technical Field

[0001] This disclosure relates to the field of electronic design automation technology, and in particular to a DFT resource allocation prediction method, apparatus, electronic device and storage medium. Background Technology

[0002] In the Design for Testability (DFT) process of modern chip projects, the number of registers is a core data support for the initial DFT architecture and solution development. Currently, DFT engineers obtain the number of registers primarily by relying on early design data provided by the design team, combined with the pre-synthesis capabilities of Electronic Design Automation (EDA) tools, and then multiplying by an empirical coefficient, or by multiplying the factory standard density by the chip area and then subtracting the area of ​​memory and analog modules based on experience.

[0003] However, due to the instability of the Register Transfer Level (RTL) code in the early stages of the project, the estimation results are inaccurate or cannot be used as a reference; DFT tools have difficulty accessing all design information in the early analysis stage, especially before the design is fully synthesized or before placement and routing; manual or script-based statistics are prone to human error and are time-consuming and labor-intensive, which seriously affects the timeliness and accuracy of DFT planning. Summary of the Invention

[0004] This disclosure provides a DFT resource allocation prediction method, apparatus, electronic device, and storage medium to solve the technical problems of existing DFT resource allocation prediction relying on experience, having large estimation errors, and insufficient accuracy.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] Firstly, this disclosure provides a DFT resource allocation prediction method, which includes: determining the baseline device density based on the process node of the target chip; determining the effective digital logic layout area based on the chip planning area of ​​the target chip and the estimated non-digital logic functional areas; correcting the effective digital logic layout area according to the utilization factor corresponding to the physical design constraints of the target chip to obtain the available standard cell layout capacity; generating the timing component number prediction range of the target chip through a logic depth mapping model based on the standard cell layout capacity and the baseline device density; and generating the design-for-test (DFT) architecture configuration parameters of the target chip based on the timing component number prediction range. Firstly, by calling a standardized process database to obtain the baseline device density and combining it with the estimated non-digital logic functional areas (such as memory and analog modules), invalid areas are accurately stripped, eliminating the basic data deviation caused by rough deduction based solely on experience in traditional methods; furthermore, the utilization factor corresponding to the physical design constraints is introduced to correct the effective digital logic layout area, bringing the routing and resource occupancy constraints of the backend physical implementation to the architecture planning stage, significantly improving the realism and physical conformity of the estimation model. Secondly, by utilizing a logical deep mapping model based on historical big data, the corrected standard cell layout capacity is transformed into a predicted range for the number of timing components. This derivation process completely decouples from the dependency on RTL code, solving the problem of EDA tools being unable to analyze the code due to instability or missing code in the early stages of the project, thus enabling early DFT architecture planning. Finally, DFT architecture configuration parameters are generated based on the predicted range, reserving fault tolerance space for subsequent design iterations. This derivation process from process-level data to DFT architecture configuration parameters not only reduces reliance on individual expert experience but also ensures the robustness of the DFT solution, effectively avoiding uncontrolled chip redesign or testing costs due to insufficient resource estimation in the later stages.

[0007] In some embodiments, the non-digital logic functional region includes at least a memory macrocell region and an analog circuit intellectual property (IP) core region. Based on the chip planning area of ​​the target chip and the estimated non-digital logic functional region, the effective digital logic layout area is determined, including: establishing exclusion regions corresponding to the memory macrocell region and the analog circuit IP region within the chip planning area; and determining the effective digital logic layout area as the difference between the chip planning area and the area of ​​the exclusion regions. By establishing exclusion regions for memory and analog circuits within the chip planning area and determining the effective logic layout area based on the difference, invalid regions are eliminated, eliminating the largest source of error. This ensures that subsequent density-based calculations only target the true digital logic region, thereby reducing the error in the DFT resource budget and avoiding the overestimation that would lead to excessive reserved decompression circuit area or excessive allocation of I / O pins, thus saving valuable chip area and packaging costs.

[0008] In some embodiments, the physical design constraint is the number of metal interconnect layers used in the target chip planning, and the utilization factor is positively correlated with the number of metal interconnect layers. The more metal interconnect layers there are, the more abundant the routing resources are, the higher the placement density of standard cells can be, and the utilization factor increases accordingly. This makes the placement capacity of standard cells more consistent with the actual physical design and the prediction of the number of timing components more accurate.

[0009] In some embodiments, the DFT resource configuration prediction method further includes updating the utilization factor based on the functional type of the target chip. Targeted adjustments to the utilization factor based on the functional type of the target chip further improve the accuracy of predicting standard cell layout capacity and the number of timing components.

[0010] In some embodiments, the utilization factor is updated according to the functional type of the target chip, including: increasing the utilization factor when the target chip is a compute-intensive chip; and decreasing the utilization factor when the target chip is a wiring-congested chip. This allows for more accurate updates to the utilization factor for different functional types of chips.

[0011] In some embodiments, the logic depth mapping model includes a first conversion coefficient and a second conversion coefficient, which correspond to different logic cone depths, respectively. Based on the standard cell layout capacity and the baseline device density, the logic depth mapping model generates a predicted range for the number of timing components in the target chip. This includes: using the first conversion coefficient to determine an upper limit for the number of timing components corresponding to a high-density pipeline design scenario; and using the second conversion coefficient to determine a lower limit for the number of timing components corresponding to a complex control logic design scenario. The setting of the two conversion coefficients enables the predicted range to accurately reflect the range of timing component numbers under different design scenarios, providing a more accurate reference for DFT architecture design.

[0012] In some embodiments, the configuration budget of the DFT scan chain architecture includes at least one of the following: the number of scan chain channels, the compression ratio of the test compression logic, and the maximum power consumption budget in the test mode. Based on the predicted range of the number of timing components, the DFT architecture configuration parameters for the testability design of the target chip are generated, including: determining the number of scan chain channels and the compression ratio of the test compression logic required to meet the preset test time constraints based on the upper limit of the number of timing components; and determining the maximum power consumption budget in the test mode based on the upper limit of the number of timing components and the preset toggle rate. This clarifies the quantitative relationship between the DFT architecture configuration parameters and the predicted range of the number of timing components, making the generation of configuration parameters more scientific and reasonable, and avoiding problems such as low test efficiency, high test costs, or excessive power consumption caused by setting parameters based on experience. By optimizing the number of scan chain channels and the compression ratio, the resource consumption of the test equipment is reduced while meeting the test time constraints; and the accurate calculation of the maximum power consumption budget ensures the safety and stability of the test process.

[0013] Secondly, this disclosure provides a DFT resource configuration prediction apparatus, which includes: a determination part, a correction part, and a generation part; the determination part is configured to determine a baseline device density based on the process node of the target chip; and to determine an effective digital logic layout area based on the chip planning area of ​​the target chip and the estimated non-digital logic functional area; the correction part is configured to correct the effective digital logic layout area according to the utilization factor corresponding to the physical design constraints of the target chip to obtain the available standard cell layout capacity; the generation part is configured to generate a timing element number prediction range for the target chip through a logic depth mapping model based on the standard cell layout capacity and the baseline device density; and to generate Design for Testability (DFT) architecture configuration parameters for the target chip based on the timing element number prediction range.

[0014] Thirdly, this disclosure provides an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the DFT resource allocation prediction method as described in the first aspect.

[0015] Fourthly, this disclosure provides a computer-readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the DFT resource allocation prediction method as described in the first aspect.

[0016] Fifthly, this disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions, which, when run on a processor, cause the processor to execute the computer program or instructions to implement the steps of the DFT resource allocation prediction method as described in the first aspect.

[0017] In a sixth aspect, this disclosure provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the DFT resource allocation prediction method as described in the first aspect.

[0018] This disclosure provides a DFT resource configuration prediction method, apparatus, electronic device, and storage medium. The DFT resource configuration prediction method achieves accurate prediction of DFT resources in the early stages of chip design by combining process node baseline device density with physical design constraints. First, it obtains baseline device density by calling a standardized process database and accurately removes invalid areas by combining estimated non-digital logic functional areas (such as memory and analog modules), eliminating the basic data deviation caused by rough deduction based solely on experience in traditional methods. Then, it introduces a utilization factor corresponding to physical design constraints to correct the effective digital logic layout area, bringing the routing and resource usage constraints of the backend physical implementation forward to the architecture planning stage, significantly improving the accuracy and physical conformity of the estimation. Second, it uses a logic depth mapping model based on historical big data to convert the corrected standard cell layout capacity into a prediction range for the number of timing components. This derivation process completely decouples from the dependency on RTL code, solving the problem that EDA tools cannot analyze due to unstable or missing code in the early stages of the project, enabling earlier DFT architecture planning. Finally, DFT architecture configuration parameters are generated based on the prediction range, reserving fault tolerance space for subsequent design iterations. This process of deriving from underlying process data to DFT architecture configuration parameters not only reduces reliance on individual expert experience but also ensures the robustness of the DFT solution, effectively avoiding uncontrolled chip redesign or testing costs due to insufficient resource estimation in the later stages. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a DFT resource allocation prediction method provided in this disclosure.

[0020] Figure 2 This is a flowchart illustrating the process for determining the rejection region provided in this disclosure.

[0021] Figure 3 This is a schematic diagram of the exclusion region in the chip planning area provided in this disclosure.

[0022] Figure 4 This is a schematic diagram illustrating the process for determining the utilization factor provided in this disclosure.

[0023] Figure 5 This is a schematic diagram illustrating the mapping relationship between the number of metal interconnect layers and the utilization factor provided in this disclosure.

[0024] Figure 6 This is a schematic diagram of another DFT resource allocation prediction method provided in this disclosure.

[0025] Figure 7 This is a structural block diagram of a DFT resource allocation prediction device provided in this disclosure.

[0026] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in this disclosure. Detailed Implementation

[0027] The technical solutions in the embodiments of this disclosure will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure are within the scope of protection of this disclosure.

[0028] The terms “first,” “second,” etc., used in this disclosure are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that this disclosure can be implemented in orders other than those illustrated or described herein, and the objects distinguished by “first,” “second,” etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more.

[0029] Before describing the technical solution of this disclosure in detail, the core terms involved are defined to ensure consistency and accuracy in the description.

[0030] DFT refers to a design method in integrated circuit design that incorporates specific test circuit structures, such as scan chains and built-in self-test circuits, to make the chip easier to test after manufacturing, thereby identifying manufacturing defects.

[0031] EDA refers to the technology of using computer-aided design software to complete the functional design, synthesis, verification, and physical design of very large-scale integrated circuit chips. The method in this embodiment is usually integrated as a functional module into EDA software.

[0032] With the rapid development of semiconductor manufacturing processes, Moore's Law has driven the continuous improvement of the integration density of integrated circuit chips. The number of transistors integrated in modern systems-on-a-chip has increased from millions to billions or even tens of billions. At advanced process nodes, such as 7 nanometers, 5 nanometers, and more, the extremely high transistor density and complex logic structures make Design for Components (DFT) a critical step in the chip design process. As a key step in the chip design flow to ensure manufacturing yield and reduce testing costs, the scientific nature of the architecture planning in DFT directly determines the success or failure of the project.

[0033] In DFT architecture design, the number of timing elements (i.e., registers or flip-flops) is the core data for formulating test strategies. DFT engineers need to plan the number of channels in the scan chain, chain length, compression ratio of the test compression logic, power budget in the test mode, and required Automatic Test Equipment (ATE) resources based on the total number of registers.

[0034] However, in existing chip design flows, accurate register counts are not readily available in the early stages of a project. Initially, estimates are made based on RTL code. However, during project architecture planning or early design phases, RTL code is often in development iterations, not yet stable, and may even have missing code for some modules. At this point, accurate RTL design data is unavailable, making it impossible to obtain reliable register counts through code statistics or pre-synthesis using EDA tools.

[0035] Secondly, existing EDA tools have limitations in the early analysis stage. They usually require analysis based on a complete gate-level netlist or complete RTL code. Before the design is fully synthesized or placed and routed, the tools cannot access specific design information.

[0036] Furthermore, manual or script-based statistical methods are not only time-consuming and labor-intensive, but also prone to omissions or miscalculations due to failure to cover all complex register declaration syntax or parameterized configurations. In addition, differences in professional backgrounds between DFT engineers and the front-end design team may lead to distorted information transmission, and without a clear allocation of responsibilities, information gaps can easily form, affecting the timeliness of DFT planning.

[0037] Therefore, traditional techniques use a rough estimation method: multiplying the chip area by the standard density and then subtracting the areas of memory and analog modules based on experience. However, this estimation method often has an error of over ±30%. This huge error range makes it impossible for architects to perform accurate power network planning, clock tree synthesis prediction, and package thermal design, often leading to later design iterations or wasted resources.

[0038] Therefore, this disclosure aims to provide a DFT resource configuration prediction method that can quickly and accurately predict the number of chip registers and their fluctuation range based on a small amount of architecture planning data in the early stages of chip design.

[0039] This disclosure provides a DFT resource allocation prediction method, primarily applicable to the architecture planning phase or early RTL development phase of integrated circuit design. In this phase, traditional statistical methods based on specific circuit structures cannot be implemented due to the lack of a complete gate-level netlist. Figure 1 As shown, the DFT resource allocation prediction method includes steps S101 to S105.

[0040] In step S101, the reference device density is determined based on the process node of the target chip.

[0041] Reference device density refers to the theoretical number of transistors that can be placed on a unit area of ​​silicon wafer at a specific process node, typically measured in millions of transistors per square millimeter (MTr / mm²). Reference device density reflects the integration capability of the manufacturing process.

[0042] The EDA system first obtains the process node information input by the user. Process nodes represent the characteristic dimensions of a semiconductor manufacturing process, such as 5 nanometers, 7 nanometers, and 14 nanometers. Different process nodes correspond to different transistor sizes and arrangements.

[0043] The EDA system has a pre-built process database that stores measured or officially released transistor density data from major wafer foundries at different process nodes. For example, for a specific 5nm process, the database records a baseline device density of 171.3 MTr / mm². The EDA system, based on the input 5nm tag, indexes and extracts 171.3 MTr / mm² as the extracted baseline device density. This step eliminates the uncertainty of blindly estimating density based on experience in the early stages of design by utilizing standardized industrial data.

[0044] In step S102, the effective digital logic layout area is determined based on the chip planning area of ​​the target chip and the estimated non-digital logic functional area.

[0045] Effective digital logic layout area refers to the physical area remaining after deducting areas from the total chip area that are not tested through the scan chain or whose internal structure does not have standard cell logic characteristics, which is used to place digital logic circuits.

[0046] During the architecture planning phase, the chip's macroscopic dimensions, i.e., the planned chip area, are known, such as 100 square millimeters. However, not all of the planned chip area is used to house the digital logic requiring DFT scan testing. The chip also contains a large number of non-digital logic functional areas, including but not limited to:

[0047] Memory regions, such as Static Random Access Memory (SRAM) and Read Only Memory (ROM), are typically tested using Memory Built-In Self-Test (MBIST), where the transistors within the memory are not included in the scan chain size.

[0048] The analog, radio frequency, and interface areas, such as phase-locked loops (PLLs), analog-to-digital converters (ADCs), and physical layer interfaces (PHYs), are primarily composed of analog devices and do not participate in the scanning and testing of digital logic.

[0049] For example, the EDA system receives an input parameter indicating the percentage of non-digital logic functional areas. This input parameter can be a percentage estimated by the designer based on past project experience; for example, memory accounts for 30%, and analog circuits account for 20%. Then, the effective digital logic layout area = chip planned area × (1 - percentage of non-digital logic functional areas). If the chip planned area is 100 square millimeters, and the total non-digital area percentage is 50%, then the effective digital logic layout area is 50 square millimeters. This accurately determines the area that actually carries the digital standard cells from the physical layout, avoiding a significant overestimation of the number of scan flip-flops due to the inclusion of high-density modules such as memory.

[0050] In step S103, the effective digital logic layout area is corrected according to the utilization factor corresponding to the physical design constraints of the target chip to obtain the available standard cell layout capacity.

[0051] The utilization factor refers to the ratio of the actual area occupied by a standard cell in the physical design to the total rectangular layout area allocated to that module. This utilization factor reflects the logic density loss caused by the physical resources occupied by wiring channels, power networks, clock tree buffers, etc. For example, the effective digital logic layout area calculated above is 50 square millimeters. However, in actual manufacturing, this 50 square millimeters cannot be completely filled with transistors; space needs to be reserved for metal interconnects, power and ground lines, and spacing to avoid signal interference. This limitation of physical implementation is characterized by the utilization factor.

[0052] Physical design constraints, such as the planned number of metal layers and power grid density, determine the upper limit of this utilization factor. For example, in physical design experience, if metal wiring resources are scarce, the utilization rate of a standard cell may only reach 60%, while if resources are abundant, it can reach 80%.

[0053] Standard cell layout capacity refers to the actual physical area or equivalent total number of logic gates that can be placed within the effective digital logic layout area of ​​the target chip, under the premise of satisfying physical design rules and routing resource constraints. Based on the utilization factor, the determined available standard cell layout capacity = effective digital logic layout area × utilization factor. Continuing the example above, 50 square millimeters × 0.8 = 40 square millimeters. This 40 square millimeters represents the actual silicon area in the target chip used to build logic gates and registers, thus bringing the backend physical routing constraints forward to the architecture stage, significantly improving the accuracy of the prediction.

[0054] In step S104, based on the standard cell layout capacity and the reference device density, the timing element number prediction range of the target chip is generated through the logic depth mapping model.

[0055] A logic depth mapping model is a mathematical or empirical model that converts the number of transistors into the number of sequential elements (such as flip-flops and registers). It reflects, on average, how many transistors correspond to one sequential element under a specific logic design style. This model is constructed based on statistical analysis of historical project data. Specifically, by retrospectively analyzing a large amount of chip design data that has already been taped out, the ratio of the total number of transistors to the number of registers in different design styles (such as high-performance computing cores, low-power controllers, and data processing engines) is statistically analyzed. Through this large-scale statistical analysis, an empirical conversion coefficient range covering different logic depths is extracted.

[0056] Specifically, the available standard cell layout capacity is multiplied by the reference device density to obtain the estimated total number of effective transistors. For example, 40 square millimeters × 171.3 million / square millimeter = 6852 million (approximately 6.85 billion) transistors. Then, it is determined how many of these 6.85 billion transistors will form sequential elements.

[0057] A prediction interval is determined through a logical deep mapping model. For example, based on historical data, high-density designs have lower conversion coefficients (meaning dense registers), while low-density designs have higher conversion coefficients (meaning sparse registers). Based on the conversion coefficients, a range of timing element numbers containing minimum and maximum values ​​is generated. This range prediction method effectively covers the uncertainties in the design details during the architecture phase, providing fault tolerance for subsequent decisions.

[0058] In step S105, the DFT architecture configuration parameters of the target chip are generated based on the predicted interval of the number of timing elements.

[0059] DFT architecture configuration parameters refer to the top-level constraints of the specific DFT implementation, including the number of scan chain channels, the compression ratio of the test compression logic, and the maximum power consumption budget in test mode.

[0060] After obtaining the predicted range for the number of timing components, i.e., registers, the EDA system transforms it into specific DFT architecture configuration parameters, i.e., engineering design metrics, to guide subsequent DFT implementation. For example, based on the upper limit of the predicted range for the number of timing components (i.e., the maximum number of registers in the worst case), the required number of scan chain channels and the compression ratio of the compression logic are calculated to ensure that the test time still meets the requirements when the number of registers reaches the upper limit. Alternatively, the power budget in the test mode can be estimated based on this range to guide the design of the power network.

[0061] In this embodiment, by combining process node baseline device density with physical design constraints, accurate prediction of DFT resources is achieved in the early stages of chip design. First, a baseline device density is obtained by calling a standardized process database, and ineffective areas are precisely stripped from the estimated non-digital logic functional areas (such as memory and analog modules), eliminating the basic data bias caused by rough deductions based solely on experience in traditional methods. Then, a utilization factor corresponding to physical design constraints is introduced to correct the effective digital logic layout area, bringing the routing and resource constraints of the backend physical implementation forward to the architecture planning stage, significantly improving the accuracy and physical conformity of the estimation model. Second, a logic depth mapping model based on historical big data is used to convert the corrected standard cell layout capacity into a predicted range for the number of timing components. This derivation process completely decouples from the dependency on RTL code, solving the problem of EDA tools being unable to analyze due to unstable or missing code in the early stages of the project, enabling earlier DFT architecture planning. Finally, DFT architecture configuration parameters are generated based on the predicted range, reserving fault tolerance space for subsequent design iterations. This process of deriving from underlying process data to DFT architecture configuration parameters not only reduces reliance on individual expert experience but also ensures the robustness of the DFT solution, effectively avoiding uncontrolled chip redesign or testing costs due to insufficient resource estimation in the later stages.

[0062] In some embodiments, the non-digital logic functional area includes at least a memory macrocell area and an analog circuit IP area; such as Figure 2 As shown, the above step S102 can be specifically implemented through the following steps S201 and S202.

[0063] In step S201, exclusion regions corresponding to the memory macrocell region and the analog circuit IP region are established in the chip planning area.

[0064] The memory macrocell region refers to the physical area in an integrated circuit chip layout specifically designated for placing memory modules. In back-end chip design, memory is not assembled from standard cells but is placed as a single, fixed black-box module. For example, a 512KB SRAM array used for caching contains millions of transistors, but the testing of these transistors typically relies on built-in self-test circuitry and is not directly connected to the scan chain. Therefore, this area is excluded when calculating the DFT resources required for the scan chain.

[0065] The analog circuit IP area refers to the circuit module area within a chip used to implement analog signal processing, radio frequency communication, or power management functions. Analog circuit IP includes components such as PLLs, ADCs, DACs, high-speed interface physical layers, and power management units. These modules are primarily composed of capacitors, resistors, and large-size analog transistors, and contain almost no general-purpose registers that require scanning and testing.

[0066] A exclusion region refers to a specific geometric area marked as a no-placement zone for standard cells in a layout plan. In this embodiment, the area containing the memory macrocells and analog circuit IPs is the exclusion region.

[0067] Based on the architecture design document or early layout planning sketches, determine the memory macrocell region and calculate the estimated area of ​​all on-chip SRAM, ROM and other memory arrays. For example, if the target chip is planned to have a total SRAM capacity of 10MB, according to the process manual, its corresponding physical area is about 30 square millimeters. In the logic model, these 30 square millimeters are marked as the first type of repulsion region.

[0068] Based on the IP vendor's specifications, determine the analog circuit IP area. For example, if the target chip integrates a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, and a PLL module, the total area of ​​these analog circuit IPs is estimated to be 20 square millimeters. Mark this 20 square millimeters as the second type of exclusion region.

[0069] In the geometric model of the planned area of ​​the target chip, a first type of exclusion region corresponding to the aforementioned memory macrocell and a second type of exclusion region corresponding to the analog circuit IP are established. This part of the region is no longer regarded as the carrier of digital logic.

[0070] In step S202, the difference between the chip planning area and the area of ​​the exclusion region is determined as the effective digital logic layout area.

[0071] Perform a subtraction operation to subtract the area of ​​the exclusion region from the planned chip area; the difference is the effective digital logic layout area.

[0072] For example, such as Figure 3 The diagram shows the exclusion region in the chip planning area. In the chip planning area 30, the rectangular areas filled with diagonal lines represent memory macrocell areas, and the connected areas filled with vertical lines represent analog circuit IP areas. In the chip planning area 30, the blank areas are the finally determined effective digital logic layout area.

[0073] In modern System-on-Chips (SoCs), memory and analog circuitry often occupy 30% to 50% or more of the total chip area. This area has extremely high transistor density (e.g., SRAM) or extremely low density (e.g., high-power analog devices), and its testing primarily relies on MBIST or functional testing, consuming no scan chain resources. Existing techniques typically estimate the number of registers roughly by multiplying the total chip area by the average density. This method incorrectly assumes that memory and analog areas are also filled with logic registers requiring scan testing, leading to estimates that are often larger than the actual requirements.

[0074] In this embodiment of the disclosure, by establishing exclusion regions for memory and analog circuits in the chip planning area and determining the effective logic layout area by the difference, invalid regions are eliminated, thus eliminating the largest source of error. This ensures that subsequent density-based calculations only target the true digital logic region, thereby reducing the error of DFT resource budget and avoiding reserving too much decompression circuit area or allocating too many I / O pins due to overestimation, thereby saving valuable chip area and packaging costs.

[0075] The number of transistors obtained solely by multiplying the effective digital logic layout area by a baseline device density is often a theoretical limit, extremely difficult to achieve in practical engineering. To further approximate the actual physical implementation of a chip, in this embodiment, as... Figure 4 As shown, the process for determining the utilization factor in this DFT resource allocation prediction method includes the following steps S401 and S402.

[0076] In step S401, the utilization factor is determined based on the number of metal interconnect layers planned for use in the target chip.

[0077] Among them, the utilization factor is positively correlated with the number of metal interconnect layers.

[0078] The number of metal interconnect layers refers to the total number of metal wire layers located above transistors in an integrated circuit manufacturing process, used to connect different devices. More advanced process chips typically contain 10 or more metal layers, denoted as M1, M2, ..., M12. The bottom layer metal is typically used for internal and local connections within standard cells, the middle layer metal for inter-module connections, and the top layer metal for power grids and global clock signals. More metal layers mean more vertical wiring space, supporting a greater number of signal crossings, thus allowing for denser placement of the bottom layer standard cells. Conversely, if there are fewer metal layers, such as only 5, the placement density of the bottom layer standard cells must be reduced to prevent wiring congestion.

[0079] Based on a pre-stored mapping table or corresponding fitting curve of the number of metal interconnect layers and utilization factors, which is obtained by statistical regression based on the back-end physical design data of a large number of tape-out projects, the utilization of hundreds of functional modules under different metal interconnect layer configurations is determined by analyzing different process nodes (such as 28nm to 5nm).

[0080] For example, if a 5-layer metal structure is planned, the cabling resources are considered extremely limited, with a utilization factor of 0.50, meaning 50% of the area is used for standard units and 50% is reserved for cabling channels. If a 6-layer metal structure is planned, the utilization factor is 0.60. If a 7-layer metal structure is planned, the utilization factor is 0.70. If an 8-layer or higher metal structure is planned, cabling resources are relatively abundant, and the density of standard units is mainly limited by power supply thermal design and physical rules, with a utilization factor of 0.80.

[0081] In this embodiment, the more metal interconnect layers there are, the more abundant the routing resources are, the higher the layout density of the standard cell can be, and the utilization factor increases accordingly. This makes the layout capacity of the standard cell more consistent with the actual physical design and the prediction of the number of timing components more accurate.

[0082] In step S402, the utilization factor is updated according to the functional type of the target chip.

[0083] In some feasible approaches, the utilization factor is increased when the target chip is a compute-intensive chip, and decreased when the chip is a wiring-congested or control-intensive chip.

[0084] Wiring congestion chips refer to a type of chip with complex interconnections between internal logic modules, numerous long global interconnections, and a lack of regularity. Examples include central processing unit (CPU) cores, network switching chips, or complex control logic. Due to the randomness of their logic, wiring resources in these chips are often exhausted earlier than transistor resources, becoming a bottleneck limiting chip density.

[0085] Computationally intensive chips refer to chip types that contain a large number of repetitive arrays of computing units, with regular data flow and interconnections primarily based on proximity. Examples include artificial intelligence (AI) accelerators, shader cores in graphics processing units (GPUs), and digital signal processing (DSPs). These chips have a regular structure, less wiring pressure, and typically achieve high physical utilization.

[0086] If the target chip is a compute-intensive chip, and the utilization factor is determined to be within the first numerical range (higher range), the utilization factor is updated. The updated utilization factor is increased by a compensation value, for example, +0.03 to +0.05. For example, for an 8-layer metal AI chip, the utilization factor is 0.8, and the updated utilization factor is 0.83.

[0087] If the target chip is a wiring congestion-prone chip, and the utilization factor is determined to fall within the second numerical range (lower range), the utilization factor is updated. The updated utilization factor adds a compensation value, for example, -0.03 to -0.05. For example, for an 8-layer metal CPU, the utilization factor is 0.8, and the updated utilization factor is 0.75 to reserve more space for vias and wiring.

[0088] For example, such as Figure 5 The diagram illustrates the mapping relationship between the number of metal interconnect layers and the utilization factor. The horizontal axis represents the number of metal interconnect layers, and the vertical axis represents the utilization factor. Solid lines in the diagram indicate the correspondence between the number of metal interconnect layers and the utilization factor. Dashed lines indicate the correspondence between the number of metal interconnect layers and the updated utilization factor for compute-intensive target chips, while dotted lines indicate the correspondence between the number of metal interconnect layers and the updated utilization factor for routing-congested target chips.

[0089] In this embodiment of the disclosure, the utilization factor is adjusted in a targeted manner based on the functional type of the target chip, which further improves the accuracy of predicting the standard cell layout capacity and the number of timing components.

[0090] In some embodiments, the logic depth mapping model includes a first transformation coefficient and a second transformation coefficient, the first transformation coefficient and the second transformation coefficient respectively corresponding to different logic cone depths, and the DFT architecture configuration parameters include at least one of the following: the number of scan chain channels, the compression ratio of the test compression logic, and the maximum power budget in test mode; such as Figure 6 As shown, the DFT resource allocation prediction method includes the following steps S601 to S607.

[0091] In step S601, the reference device density is determined based on the process node of the target chip.

[0092] In step S602, the effective digital logic layout area is determined based on the chip planning area of ​​the target chip and the estimated non-digital logic functional area.

[0093] In step S603, the effective digital logic layout area is corrected according to the utilization factor corresponding to the physical design constraints of the target chip to obtain the available standard cell layout capacity.

[0094] The logic depth mapping model in this embodiment introduces a conversion factor reflecting the logic cone depth. The total number of transistors includes combinational logic (AND, OR, NOT gates) and sequential logic (registers). The ratio of the two depends on the logic cone depth of the design. Logic cone depth refers to the number of combinational logic gates (such as NAND gates, inverters) or the delay depth between two sequential elements (such as registers) in a digital circuit, reflecting the fineness of the pipeline segmentation. A shallow logic cone refers to a small number of combinational logic levels between two registers (e.g., 5 to 10 gates), typically seen in pipeline designs aiming for high clock frequencies, where the proportion of registers per transistor is high. A deep logic cone refers to a complex decoding, arithmetic, or state transition logic between two registers (e.g., 30 to 50 gates), where the proportion of registers per transistor is low.

[0095] Let A be the chip planning area, P be the reference device density, U be the determined updated utilization factor, R1 be the proportion of the memory macrocell region, and R2 be the proportion of the analog circuit IP region. Then the determined total number of effective transistors N is: N = A × P × (1 - R1) × (1 - R2) × U.

[0096] In step S604, the upper limit of the number of timing components corresponding to the high-density pipeline design scenario is determined using the first conversion coefficient.

[0097] In high-density pipelined design scenarios, the logic levels are short and the density of sequential components is extremely high. The logic depth mapping model calls the first transformation coefficient K1, which can be between 120 and 150, for example, K1=120. The upper limit Nmax=N / K1, which represents the maximum number of registers that the target chip may contain under the most aggressive pipelined design style.

[0098] In step S605, the lower limit of the number of timing elements corresponding to the complex control logic design scenario is determined using the second conversion coefficient.

[0099] In complex control logic design scenarios, the logic levels are deep, combinational logic dominates, and the density of sequential components is low. The logic depth mapping model calls the second transformation coefficient K2, which can be between 220 and 250, for example, K2=250. The lower limit value Nmin=N / K2, which represents the minimum number of registers that the target chip may contain under extremely complex logic conditions.

[0100] The setting of the two conversion coefficients enables the prediction range to accurately reflect the range of timing component quantities under different design scenarios, providing a more accurate reference for DFT architecture design.

[0101] In step S606, based on the upper limit of the number of timing components, the number of scan chain channels required to meet the preset test time constraints and the compression ratio of the test compression logic are determined.

[0102] Using Nmax in the above prediction interval, configuration budgets are generated for the preset time constraints and power consumption constraints, respectively.

[0103] The scan chain architecture is determined based on the upper limit Nmax. Test time is directly proportional to the amount of test data, which in turn depends on the total number of registers in the scan chain. To ensure that the preset test time requirement is met even in the worst-case scenario (Nmax with the maximum number of registers), the number of channels needs to be planned based on Nmax. The calculation process is as follows: Set the target maximum chain length as Lmax, and the required total number of internal scan chains Cinternal = Nmax / Lmax. If the number of available scan I / O channels at the top layer of the target chip is Cchannel, then the required compression ratio is Cinternal / Cchannel = Nmax / (Lmax × Cchannel).

[0104] For example, A is 100 mm 2 P is 171.3 MTr / mm 2R1 is 40%, R2 is 10%, and U is 0.80. Then N is: 100×171.3×(1 - 0.4)×(1 - 0.1)×0.80≈7400.16 Million Transistors, approximately 7.4 billion transistors. Set the first conversion coefficient K1=120, Nmax=7400.16 / 120≈61.67 Million Registers, set the second conversion coefficient K2=250, Nmin=7400.16 / 250≈29.6 Million Registers, that is, the predicted range of the number of sequential components is [29.6, 61.67]. Assuming the test equipment limits the maximum chain length L per chain to 5000 flip-flops, the required number of scan chain channels is approximately 61,670,000 / 5000 ≈ 12334. Assuming the top layer of the chip only provides 64 pairs of scan channels, the compression ratio is approximately 12334 / 64 ≈ 192.7. Therefore, in the DFT architecture configuration parameters, a 200x compression ratio EDT architecture is recommended to ensure that the preset test time is met even with the worst-case register count.

[0105] In step S607, the maximum power consumption budget in the test mode is determined based on the upper limit of the number of timing components and the preset toggle rate.

[0106] The toggle rate refers to the frequency at which a signal changes from 0 to 1 or from 1 to 0 per unit of time. A higher toggle rate results in greater dynamic power consumption. During testing, the output of each timing element may toggle; therefore, the more timing elements there are, the more nodes may toggle, and the higher the power consumption. Thus, the maximum power consumption budget can be determined based on the upper limit of the number of timing elements and the preset toggle rate of each timing element.

[0107] This disclosure clarifies the quantitative relationship between DFT architecture configuration parameters and the predicted range of timing element numbers, making the generation of configuration parameters more scientific and reasonable, and avoiding problems such as low test efficiency, high test costs, or excessive power consumption caused by setting parameters based on experience. By optimizing the number of scan chain channels and compression ratio, the resource occupation of test equipment is reduced while meeting test time constraints; and by accurately calculating the maximum power budget, the safety and stability of the test process are ensured.

[0108] Figure 7 This is a structural block diagram of a DFT resource allocation prediction device disclosed herein, such as... Figure 7 As shown, it includes: a determining part 701, a correcting part 702, and a generating part 703;

[0109] The determination section 701 is configured to determine the baseline device density based on the process node of the target chip; and to determine the effective digital logic layout area based on the chip planning area and the estimated non-digital logic functional area of ​​the target chip. The correction section 702 is configured to correct the effective digital logic layout area according to the utilization factor corresponding to the physical design constraints of the target chip to obtain the available standard cell layout capacity. The generation section 703 is configured to generate the timing element number prediction range of the target chip through a logic depth mapping model based on the standard cell layout capacity and the baseline device density; and to generate the design-for-test (DFT) architecture configuration parameters of the target chip based on the timing element number prediction range.

[0110] In some embodiments, the non-digital logic functional area includes at least a memory macrocell area and an analog circuit IP area; the determining portion 701 is configured to establish a rejection region corresponding to the memory macrocell area and the analog circuit IP area in the chip planning area; and the area difference between the chip planning area and the rejection region is determined as the effective digital logic layout area.

[0111] In some embodiments, the physical design constraint is the number of metal interconnect layers to be used in the target chip planning, and the utilization factor is positively correlated with the number of metal interconnect layers.

[0112] In some embodiments, the DFT resource configuration prediction apparatus further includes an update portion configured to update the utilization factor based on the functional type of the target chip.

[0113] In some embodiments, the update portion is configured to increase the utilization factor when the target chip is a compute-intensive chip, and decrease the utilization factor when the target chip is a wiring-congested chip.

[0114] In some embodiments, the logic depth mapping model includes a first conversion coefficient and a second conversion coefficient, the first conversion coefficient and the second conversion coefficient corresponding to different logic cone depths; the generation part 703 is configured to use the first conversion coefficient to determine an upper limit value for the number of timing elements corresponding to a high-density pipeline design scenario; and to use the second conversion coefficient to determine a lower limit value for the number of timing elements corresponding to a complex control logic design scenario.

[0115] In some embodiments, the DFT architecture configuration parameters include at least one of the following: the number of scan chain channels, the compression ratio of the test compression logic, and the maximum power budget in the test mode; the generation section 703 is configured to determine the number of scan chain channels and the compression ratio of the test compression logic required to meet the preset test time constraints based on an upper limit value of the number of timing elements; and to determine the maximum power budget in the test mode based on an upper limit value of the number of timing elements and a preset toggle rate.

[0116] In this embodiment, each part can implement the DFT resource allocation prediction method provided in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0117] Please refer to Figure 8 This illustration shows a schematic diagram of the hardware structure of an electronic device provided in an exemplary embodiment of this disclosure. In some examples, the electronic device may be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The electronic device has communication functions and can access wired or wireless networks. The term "electronic device" can refer to one of multiple terminals; those skilled in the art will understand that the number of such terminals may be more or less. It is understood that the electronic device undertakes the computation and processing work of the technical solution of this disclosure, and this disclosure does not limit this aspect.

[0118] like Figure 8 As shown, the electronic device in this disclosure may include one or more of the following components: processor 810 and memory 820.

[0119] Optionally, the processor 810 connects various parts within the electronic device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 820, and by calling data stored in the memory 820. Optionally, the processor 810 can be implemented using at least one hardware form of DSP, Field Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 810 can integrate one or more of the following: CPU, GPU, Neural-network Processing Unit (NPU), and baseband chip. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement AI functions; and the baseband chip is used to handle wireless communication. It is understood that the baseband chip can also be implemented as a separate chip without being integrated into the processor 810.

[0120] The memory 820 may include random access memory (RAM) or ROM. Optionally, the memory 820 may include non-transitory computer-readable storage medium. The memory 820 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 820 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created based on the use of the electronic device, etc.

[0121] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above figures does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0122] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the DFT resource allocation prediction method as described in the various embodiments above.

[0123] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the DFT resource allocation prediction method described in the above embodiments.

[0124] This disclosure also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described DFT resource allocation prediction method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0125] It should be understood that the chip mentioned in the embodiments of this disclosure may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0126] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, servers, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0129] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0130] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0131] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0132] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A DFT resource configuration prediction method, characterized in that, The DFT resource configuration prediction method comprises: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on a chip planning area of the target chip and an estimated non-digital logic functional area; correcting the effective digital logic layout area according to a utilization factor corresponding to a physical design constraint of the target chip to obtain an available standard cell layout capacity; generating a timing element quantity prediction interval of the target chip through a logic depth mapping model according to the standard cell layout capacity and the reference device density; generating a design for test (DFT) architecture configuration parameter of the target chip according to the timing element quantity prediction interval; the logic depth mapping model comprises first and second conversion coefficients, the first and second conversion coefficients correspond to different logic cone depths respectively; the generating of the timing element quantity prediction interval of the target chip through the logic depth mapping model according to the standard cell layout capacity and the reference device density comprises: determining an upper limit value of the timing element quantity corresponding to a high-density pipeline design scenario by using the first conversion coefficient; determining a lower limit value of the timing element quantity corresponding to a complex control logic design scenario by using the second conversion coefficient; the DFT architecture configuration parameter comprises at least one of a scan chain channel quantity, a compression ratio of test compression logic and a maximum power consumption budget in a test mode; the generating of the DFT architecture configuration parameter of the target chip according to the timing element quantity prediction interval comprises: determining the scan chain channel quantity and the compression ratio of test compression logic required to meet a preset test time constraint based on the upper limit value of the timing element quantity; determining the maximum power consumption budget in the test mode based on the upper limit value of the timing element quantity and a preset flip rate.

2. The DFT resource configuration prediction method of claim 1, wherein, the non-digital logic functional area at least comprises a memory macro cell area and an analog circuit intellectual property (IP) area; the determining of the effective digital logic layout area based on the chip planning area of the target chip and the estimated non-digital logic functional area comprises: establishing exclusion zones corresponding to the memory macro cell area and the analog circuit IP area in the chip planning area; determining the effective digital logic layout area as a difference between the chip planning area and the area of the exclusion zones.

3. The DFT resource configuration prediction method of claim 1, wherein, the physical design constraint is a number of metal interconnection layers planned for the target chip, and the utilization factor is positively correlated with the number of metal interconnection layers.

4. The DFT resource configuration prediction method of claim 3, wherein, The DFT resource configuration prediction method further comprises: updating the utilization factor according to a function type of the target chip.

5. The DFT resource configuration prediction method of claim 4, wherein, The updating of the utilization factor according to the function type of the target chip comprises: increasing the utilization factor in a case where the target chip is a compute-intensive chip; and decreasing the utilization factor in a case where the target chip is a wiring congestion type chip.

6. A DFT resource configuration prediction apparatus, characterized by, The DFT resource configuration prediction device comprises a determination part, a correction part and a generation part. The determining part is configured to determine a reference device density based on a process node of a target chip; and determine an effective digital logic layout area based on a chip planning area of the target chip and an estimated non-digital logic function area; The correction part is configured to correct the effective digital logic layout area according to a utilization factor corresponding to a physical design constraint of the target chip to obtain available standard cell layout capacity; The generation part is configured to generate a timing element quantity prediction interval of the target chip by a logic depth mapping model according to the standard cell layout capacity and the reference device density; and generate a design for test (DFT) architecture configuration parameter of the target chip according to the timing element quantity prediction interval; The logic depth mapping model includes first conversion coefficients and second conversion coefficients, the first conversion coefficients and the second conversion coefficients correspond to different logic cone depths respectively; the DFT architecture configuration parameter includes at least one of the following: a scan chain channel quantity, a compression ratio of test compression logic, and a maximum power consumption budget in a test mode; The generation part is specifically configured to determine an upper limit value of a timing element quantity corresponding to a high-density pipeline design scenario by using the first conversion coefficients; and determine a lower limit value of a timing element quantity corresponding to a complex control logic design scenario by using the second conversion coefficients; and determine the scan chain channel quantity and the compression ratio of the test compression logic required to meet a preset test time constraint based on the upper limit value of the timing element quantity; and determine the maximum power consumption budget in the test mode based on the upper limit value of the timing element quantity and a preset flip rate. 7.An electronic device comprising a memory and a processor, the memory having stored therein a computer program, characterized in that, The processor executes the computer program to implement the DFT resource configuration prediction method in any one of claims 1 to 5.

8. A computer readable storage medium having stored thereon computer instructions, wherein, The instructions are executed to cause a computer system to perform the DFT resource configuration prediction method in any one of claims 1 to 5.

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