Performance optimization method and device of power supply protection circuit, equipment and storage medium

Abstract

The invention relates to the technical field of power protection, and discloses a performance optimization method, device and equipment for a power protection circuit and a storage medium, and the method comprises the steps: constructing a high-frequency circuit model of the power protection circuit, and carrying out the simulation of the frequency response characteristic of the high-frequency circuit model under the action of an ESD pulse signal, so as to obtain a simulation result; determining a target resonance point of the power supply protection circuit according to the simulation result; and adjusting the power supply protection circuit based on the target resonance point so as to optimize the ESD protection performance of the power supply protection circuit on the target resonance point. The protection performance of the power supply protection circuit on high-frequency ESD interference can be effectively improved, and the risk of damage to a rear-end load caused by energy coupling of the ESD interference is reduced.

Description

Technical Field

[0001] This application relates to the field of power protection technology, and in particular to a method, apparatus, device and storage medium for optimizing the performance of a power protection circuit. Background Technology

[0002] In electronic devices, on the one hand, it is necessary to avoid permanent damage caused by reverse power connection, and on the other hand, it is necessary to pass the strict electrostatic discharge (ESD) immunity test. Therefore, corresponding power protection circuits are set at the power input terminal.

[0003] In related technologies, power supply protection circuits typically utilize reverse polarity protection diodes and transient voltage suppressor (TVS) diodes to achieve the aforementioned protection functions. However, when facing high-frequency ESD interference, the protection effect of these technical solutions is unstable and difficult to effectively protect downstream loads, potentially subjecting them to unexpected damage risks. Summary of the Invention

[0004] This application provides a method, apparatus, device, and storage medium for optimizing the performance of a power protection circuit. It solves the technical problem that current power protection circuits have unstable protection effects against high-frequency ESD interference and are difficult to effectively protect downstream loads. It can effectively improve the protection performance of power protection circuits against high-frequency ESD interference and reduce the risk of damage to downstream loads caused by the energy coupling of ESD interference.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, this application provides a method for optimizing the performance of a power supply protection circuit, the method comprising: A high-frequency circuit model of the power supply protection circuit is constructed, and the frequency response characteristics of the high-frequency circuit model under the action of ESD pulse signal are simulated to obtain simulation results. The target resonant point of the power supply protection circuit is determined based on the simulation results. The power supply protection circuit is adjusted based on the target resonant point to optimize its ESD protection performance at the target resonant point.

[0006] The performance optimization method proposed in this application constructs a high-frequency circuit model and simulates its frequency response characteristics under ESD pulse signals. This accurately simulates the performance of the power supply protection circuit under actual ESD impact, providing a precise basis for determining the target resonant point. Based on the target resonant point, the critical frequency points in the circuit that may be significantly affected by ESD are accurately located. Subsequently, the power supply protection circuit is adjusted to avoid the main distribution frequency band of ESD energy at the target resonant point, effectively reducing the energy coupling amplification of ESD at the target resonant point. This improves the ESD immunity of the power supply protection circuit, thereby enhancing system reliability and stability and reducing the risk of damage to downstream loads due to ESD.

[0007] Optionally, simulating the frequency response characteristics of the high-frequency circuit model under the action of an ESD pulse signal to obtain simulation results includes: The ESD pulse signal is input into the high-frequency circuit model, wherein the ESD pulse signal is generated by a pre-constructed current source model; A frequency sweep analysis is performed on the impedance or scattering parameters of the high-frequency circuit model in response to the ESD pulse signal to obtain the frequency domain characteristic curve of the impedance or scattering parameters, and the frequency domain characteristic curve is used as the simulation result.

[0008] This application utilizes a current source model to generate ESD pulse signals to accurately simulate ESD interference waveforms. It also performs frequency sweep analysis on the impedance or scattering parameters of the high-frequency circuit model within the frequency domain of the ESD pulse signals. The resulting frequency domain characteristic curves accurately reflect the characteristics of the power supply protection circuit at each frequency point, thereby more accurately determining the target resonant point. This provides an accurate data basis for subsequent targeted optimization of the ESD protection performance of the power supply protection circuit at the target resonant point.

[0009] Optionally, determining the target resonant point of the power supply protection circuit based on the simulation results includes: The initial resonance point is determined based on the valley point of the frequency domain characteristic curve; Target resonance points that meet preset conditions are selected from the initial resonance points.

[0010] This application selects target resonant points that affect the ESD protection performance of the circuit from the initial resonant points, so as to make targeted adjustments later, thereby improving the efficiency of ESD performance optimization of the power supply protection circuit.

[0011] Optionally, the high-frequency circuit model includes a reverse polarity protection diode D1, a TVS diode D2, and a parasitic inductor L. p Parasitic capacitance C p First junction capacitance C j1 and the second junction capacitance Cj2 ; Among them, the reverse polarity protection diode D1, the TVS diode D2, and the parasitic inductor L p The parasitic capacitance C p The first junction capacitance C is connected in series. j1 The second junction capacitance C is connected in parallel across the anti-reverse connection diode D1. j2 It is connected in parallel across the two ends of the TVS tube D2.

[0012] In the process of constructing the high-frequency circuit model, this application takes into account the influence of the reverse polarity protection diode D1, TVS diode D2, and the junction capacitance, parasitic capacitance, and parasitic inductance caused by the circuit routing on the resonant characteristics of the circuit, thereby accurately simulating the response of the power supply protection circuit under the action of ESD pulse signal, providing an accurate basis for subsequent simulation analysis.

[0013] Optionally, adjusting the power supply protection circuit based on the target resonant point includes: When the target resonant point is within a preset interference frequency band, the parasitic inductance L... p and the parasitic capacitance C p Adjustments were made, and the adjusted high-frequency circuit model was obtained; Verify the frequency response characteristics of the adjusted high-frequency circuit model under the action of the ESD pulse signal, and if the verification is successful, adjust the wiring parameters of the power protection circuit according to the adjusted high-frequency circuit model.

[0014] This application modifies the parasitic inductance L in the high-frequency circuit model. p and parasitic capacitance C p This allows the resonant point of the adjusted high-frequency circuit model to be far away from the preset interference frequency band when facing ESD pulse interference, thereby reducing the adverse effects of ESD pulse signals on the circuit in this frequency band. Based on this, the wiring parameters in the power supply protection circuit are adjusted, which not only ensures the effective improvement of the ESD protection performance of the power supply protection circuit, but also reduces the modification cost of circuit adjustment.

[0015] Optionally, adjusting the power supply protection circuit based on the target resonant point includes: When the target resonant point is within a preset interference frequency band, the first junction capacitance C j1 and the second junction capacitance C j2 Adjustments were made, and the adjusted high-frequency circuit model was obtained; Verify the frequency response characteristics of the adjusted high-frequency circuit model under the action of the ESD pulse signal, and if the verification is successful, adjust the component parameters of the power supply protection circuit according to the adjusted high-frequency circuit model.

[0016] Optionally, adjusting the power supply protection circuit based on the target resonant point includes: When the target resonance point is within a preset interference frequency band, the key position of the high-frequency circuit model is determined, and passive components are added at the key position to obtain the adjusted high-frequency circuit model. Verify the frequency response characteristics of the adjusted high-frequency circuit model under the action of the ESD pulse signal, and if the verification is successful, add the passive device to the power protection circuit according to the adjusted high-frequency circuit model.

[0017] This application adjusts the junction capacitance parameters of the reverse polarity protection diode D1 and the TVS diode D2, or adds passive components, so that the resonant point of the adjusted high-frequency circuit model is far away from the preset interference frequency band when facing ESD pulse interference. This reduces the adverse effects of ESD pulse signals on the circuit in this frequency band. Based on this, the adjustment of component parameters in the power supply protection circuit is guided. While ensuring effective improvement of the ESD protection performance of the power supply protection circuit, it does not require complex changes to the circuit layout, thus reducing the difficulty of performance optimization.

[0018] Secondly, this application provides a performance optimization device for a power supply protection circuit, the device comprising: The simulation module is used to construct a high-frequency circuit model of the power supply protection circuit and to simulate the frequency response characteristics of the high-frequency circuit model under the action of ESD pulse signal to obtain simulation results. The resonance analysis module is used to determine the target resonance point of the power supply protection circuit based on the simulation results. An adjustment module is used to adjust the power supply protection circuit based on the target resonant point in order to optimize the ESD protection performance of the power supply protection circuit at the target resonant point.

[0019] The performance optimization device proposed in this application accurately simulates the performance of power supply protection circuits under actual ESD impacts by constructing a high-frequency circuit model and simulating its frequency response characteristics under ESD pulse signals. This provides an accurate basis for determining the target resonant point, allowing for precise location of key frequency points in the circuit that may be significantly affected by ESD. Subsequently, the power supply protection circuit is adjusted to avoid the main ESD energy distribution frequency band, effectively reducing ESD energy coupling amplification at the target resonant point. This enhances the ESD immunity of the power supply protection circuit, thereby improving system reliability and stability and reducing the risk of ESD-induced damage to downstream loads.

[0020] Thirdly, this application provides a computer device, comprising: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes these computer instructions to perform the aforementioned power protection circuit performance optimization method.

[0021] Fourthly, this application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the above-described power protection circuit performance optimization method. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 One of the flowcharts for a performance optimization method of a power protection circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a high-frequency circuit model provided in an embodiment of this application; Figure 3 A second schematic flowchart illustrating a performance optimization method for a power protection circuit provided in an embodiment of this application; Figure 4 A third schematic flowchart illustrating a performance optimization method for a power protection circuit provided in an embodiment of this application; Figure 5 A schematic diagram of the frequency domain characteristic curve of a high-frequency circuit model responding to an ESD pulse signal, as provided in the embodiments of this application; Figure 6 A schematic diagram of the structure of a performance optimization device for a power protection circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0026] In related technologies, power supply protection circuits generally include a reverse connection protection diode and a TVS diode. The reverse connection protection diode is connected between the power input terminal and the downstream load. When the power supply is reversed, the diode's unidirectional conductivity blocks the reverse current, preventing damage to the downstream load from reverse current surges. The TVS diode is connected between the power input terminal and ground, i.e., in parallel with the power input terminal, to quickly conduct when an abnormally high voltage ESD pulse occurs, achieving high voltage clamping.

[0027] However, the relevant technologies neglect the high-frequency resonant characteristics formed by the parasitic parameters of the anti-reverse diode, the loop layout capacitance, and the loop layout inductance. The resonant point of this high-frequency resonant characteristic is very likely to be within the energy concentration band of the ESD pulse. Once the ESD pulse excites this resonant point, the circuit will generate strong oscillations. These oscillations not only fail to attenuate the energy of the ESD pulse, but may also amplify the energy through the resonance effect and couple it more effectively to the downstream load. This leads to a decrease in the clamping effect of the TVS diode and greatly increases the risk of damage to the downstream circuitry.

[0028] Furthermore, related technologies often rely on experience and static parameters in device specifications for power supply protection circuit design. It is difficult to identify and resolve the energy coupling amplification risk caused by the high-frequency resonance characteristics during the design phase, which leads to a significant cost for iterative improvements after circuit development.

[0029] Therefore, there is an urgent need for a method that can identify the high-frequency resonance risk of power supply protection circuits during the design phase and optimize the ESD protection performance of power supply protection circuits accordingly.

[0030] To address the aforementioned problems, this application provides a method for optimizing the performance of a power supply protection circuit, such as... Figure 1 As shown, the method includes the following steps: Step S1: Construct a high-frequency circuit model of the power supply protection circuit, and simulate the frequency response characteristics of the high-frequency circuit model under the action of ESD pulse signal to obtain simulation results.

[0031] Specifically, in this embodiment, a high-frequency circuit model is built using simulation software. This high-frequency circuit model is based on an actual power protection circuit, including key components such as reverse polarity protection diodes and TVS diodes, and the device parameters of these key components are set. Simultaneously, equivalent parasitic devices and corresponding parasitic parameters are set according to the actual power protection circuit's traces, pads, and vias to ensure that the model can accurately reflect the high-frequency resonance characteristics of the circuit. Then, the connection node between the reverse polarity protection diode and the TVS diode is used as the signal input terminal of the high-frequency circuit model, and an ESD pulse signal is sent to this signal input terminal to simulate the frequency response characteristics of the high-frequency circuit model. Preferably, the simulation result obtained is the frequency domain characteristic curve of the impedance or scattering parameters (S-parameters) of the high-frequency circuit model.

[0032] Step S3: Determine the target resonant point of the power supply protection circuit based on the simulation results.

[0033] This application's embodiments determine the target resonant point based on the valley point of the frequency domain characteristic curve. Specifically, the junction capacitance of the reverse-connection protection diode, along with parasitic devices such as traces, pads, and vias, form a series LC resonant circuit. In the case of parasitic inductance and capacitance in series, i.e., series resonance, when the ESD pulse frequency coincides with the inherent resonant frequency of the circuit, the inductive reactance of the parasitic inductance and the capacitive reactance of the parasitic capacitance are equal in magnitude and opposite in phase, thus canceling each other out. This causes the total impedance of the circuit to drop to a minimum point, i.e., the valley point on the frequency domain characteristic curve. In other words, the inherent resonant frequency of the power supply protection circuit can be determined based on the valley point of the frequency domain characteristic curve. Furthermore, the ESD energy coupling efficiency is highest near the circuit's resonant frequency, leading to unstable ESD protection at that resonant frequency.

[0034] Step S5: Adjust the power supply protection circuit based on the target resonant point to optimize the ESD protection performance of the power supply protection circuit at the target resonant point.

[0035] Specifically, the embodiments of this application optimize the device parameters and design layout of the power protection circuit based on the target resonant point, thereby changing the inherent resonant frequency of the power protection circuit. This makes the adjusted inherent resonant frequency far away from the main distribution frequency band of ESD pulses, fundamentally reducing ESD energy coupling efficiency and achieving the goal of improving the ESD protection performance of the power protection circuit.

[0036] The performance optimization method provided in this embodiment constructs a high-frequency circuit model and simulates its frequency response characteristics under ESD pulse signals. This accurately simulates the performance of the power supply protection circuit under actual ESD impact, providing a precise basis for determining the target resonant point. Based on the target resonant point, the critical frequency points in the circuit that may be significantly affected by ESD are accurately located. Subsequently, the power supply protection circuit is adjusted for the target resonant point, thereby avoiding the main distribution frequency band of ESD energy. This effectively reduces the energy coupling amplification of ESD at the target resonant point, improves the ESD anti-interference capability of the power supply protection circuit, and ultimately enhances system reliability and stability, reducing the risk of damage to downstream loads due to ESD.

[0037] Figure 2 The circuit structure of the above high-frequency circuit model is shown, as follows: Figure 2 As shown, in some embodiments of this application, the high-frequency circuit model includes a reverse polarity protection diode D1, a TVS diode D2, and a parasitic inductor L. p Parasitic capacitance C p First junction capacitance C j1 and the second junction capacitance C j2 Among them, the reverse polarity protection diode D1, the TVS diode D2, and the parasitic inductance L... p Parasitic capacitance C p The first junction capacitance C is connected in series. j1 The second junction capacitance C is connected in parallel across the reverse polarity protection diode D1. j2 It is connected in parallel across the two ends of TVS tube D2.

[0038] Specifically, the first junction capacitance C j1 To prevent the parasitic capacitance of the reverse-connected diode D1, the second junction capacitance C j2 The parasitic capacitance of TVS diode D2 is expressed in the high-frequency circuit model through the first junction capacitance C. j1 Second junction capacitance C j2 Simulate the inherent PN junction capacitance characteristics of the reverse polarity protection diode D1 and the TVS diode D2. Parasitic inductance L p and parasitic capacitance C p This is equivalent to the distributed inductance and distributed capacitance generated in the PCB layout, such as PCB traces, pads, and vias, in the power protection circuit.

[0039] In some embodiments of this application, the scattering parameters of the power supply protection circuit can be measured using a vector network analyzer (VNA), which characterizes the signal transmission characteristics between circuit ports. The scattering parameters may include the input reflection coefficient S11 and the output reflection parameter S22. Taking the input reflection coefficient S11 as an example, the parasitic inductance L is determined by the following formulas (1) and (2). pand parasitic capacitance C p : (1) (2) In the formula, The characteristic impedance is preferably 50Ω. The input reflection coefficient S11 corresponds to the angular frequency.

[0040] In other embodiments of this application, a three-dimensional model of the PCB traces and device packages can also be created in ANSYS HFSS / Q3D software, and parameters such as circuit materials, frequency range, and boundary conditions can be set. The software is then run to calculate and extract the parasitic inductance L through a distributed parameter network. p and parasitic capacitance C p .

[0041] In the construction of the high-frequency circuit model, this application takes into account the influence of the reverse polarity protection diode D1, TVS diode D2, and the junction capacitance, parasitic capacitance, and parasitic inductance caused by the circuit traces on the resonant characteristics of the circuit, thereby accurately simulating the response of the power supply protection circuit under the action of ESD pulse signal, providing an accurate basis for subsequent simulation analysis.

[0042] In some embodiments of this application, such as Figure 3 As shown, step S1 above may include the following steps: Step S11: Input the ESD pulse signal into the high-frequency circuit model, wherein the ESD pulse signal is generated by a pre-constructed current source model.

[0043] Specifically, in some embodiments of this application, a current source model is constructed according to ESD immunity test standards, such as the IEC 61000-4-2 standard, so that the current source model can generate interference signals with extremely fast rise time, short duration but extremely high energy, and its spectrum can reach the MHz level, thereby accurately simulating the interference environment of ESD pulses.

[0044] Step S13: Perform frequency sweep analysis on the impedance or scattering parameters of the high-frequency circuit model in response to the ESD pulse signal to obtain the frequency domain characteristic curve of the impedance or scattering parameters, and use the frequency domain characteristic curve as the simulation result.

[0045] Specifically, in this embodiment, the frequency sweep range is set using simulation software such as ADS and LTspice to cover the spectral range of ESD pulses, for example, from 0 to 1 GHz. During the frequency sweep analysis, impedance data or scattering parameters of the high-frequency circuit model at different frequencies are continuously collected, and the collected frequency-impedance or frequency-scattering parameters are fitted to generate a continuous frequency domain characteristic curve. This curve can intuitively reflect the high-frequency response law of the circuit at different frequencies, providing data support for the subsequent determination of the target resonant point.

[0046] This application embodiment utilizes a current source model to generate ESD pulse signals to accurately simulate ESD interference waveforms. Furthermore, it performs frequency sweep analysis on the impedance or scattering parameters of the high-frequency circuit model within the frequency domain of the ESD pulse signals. The resulting frequency domain characteristic curves accurately reflect the characteristics of the power supply protection circuit at each frequency point, thereby more precisely determining the target resonant point. This provides an accurate data basis for subsequent targeted optimization of the power supply protection circuit's ESD protection performance at the target resonant point.

[0047] like Figure 4 As shown, in some embodiments of this application, step S3 may include the following steps: Step S31: Determine the initial resonance point based on the valley point of the frequency domain characteristic curve.

[0048] Specifically, with Figure 4 Taking the high-frequency circuit model shown as an example, Figure 5 The frequency domain characteristic curves of the scattering parameters of this high-frequency circuit model in response to ESD pulse signals are shown, as follows: Figure 5 As shown, the horizontal axis of the frequency domain characteristic curve corresponds to the frequency sweep range of the ESD pulse, and the vertical axis corresponds to the scattering parameters of the high-frequency circuit model responding to ESD pulses of different frequencies. For example, a frequency sweep analysis of the high-frequency circuit model of the power protection circuit corresponding to the turn signal system reveals obvious extreme value characteristics at multiple frequency points, such as 0.2579677GHz, 0.504GHz, 0.6100514GHz, and 0.8565974GHz. Figure 4 It can be seen that the model is a series resonance, therefore these valley points are the initial resonance points mentioned above.

[0049] Step S33: Select target resonance points that meet the preset conditions from the initial resonance points.

[0050] Specifically, preset conditions can be set based on preset limits for impedance or scattering parameters. For example, initial resonant points with scattering parameters below -20dB can be selected as target resonant points. Target resonant points selected through preset conditions are the critical resonant points with the highest risk of ESD interference energy and circuit resonance effects superimposed. Initial resonant points that do not meet the preset conditions are considered to have a minor impact on the performance of the power supply protection circuit and can be ignored. However, due to the energy coupling amplification of ESD pulses at these resonant points, the ESD protection performance of the power supply protection circuit at these target resonant points will be greatly reduced. Therefore, subsequent circuit adjustments are required for these target resonant points.

[0051] In this application embodiment, target resonant points that affect the ESD protection performance of the circuit are selected from the initial resonant points so that they can be adjusted in a targeted manner in the future, thereby improving the efficiency of ESD performance optimization of the power supply protection circuit.

[0052] In some embodiments of this application, step S5 may include: When the target resonant point is within the preset interference frequency band, the parasitic inductance L p and parasitic capacitance C p Adjustments were made to obtain the adjusted high-frequency circuit model. The frequency response characteristics of the adjusted high-frequency circuit model under ESD pulse signal were verified, and if the verification was successful, the routing parameters of the power supply protection circuit were adjusted according to the adjusted high-frequency circuit model.

[0053] Specifically, in this embodiment, the preset interference frequency band is determined based on the energy concentration band of the ESD pulse, for example, 100MHz to 300MHz. If the target resonant point is within the preset interference frequency band, the parasitic inductance L in the high-frequency circuit model can be adjusted. p and parasitic capacitance C p In order to obtain the adjusted high-frequency circuit model, the impedance and scattering parameters of the LC resonant circuit in the high-frequency circuit model are changed, so that the target resonant point is shifted away from the energy concentration band of the ESD pulse.

[0054] Subsequently, the parasitic inductance L was verified using simulation software on the adjusted high-frequency circuit model. p and parasitic capacitance C pThe effectiveness of the adjustment is determined. The simulation analysis during the verification process can be referenced in step S1 above. A frequency sweep analysis is performed on the impedance or scattering parameters of the high-frequency circuit model within the 100MHz to 300MHz frequency band, and the simulated frequency domain characteristic curve is used as the verification result. If, based on the verification result, the resonant frequency of the target resonant point is shifted to a frequency band with lower ESD pulse energy, such as a low-frequency band below 100MHz, or to a frequency band far exceeding the concentration of ESD pulse energy, such as a high-frequency band above 300MHz, then the verification is considered successful. Furthermore, if the verification is successful, the adjusted high-frequency circuit model can be used as a reference to adjust the width, length, or stack-up structure of the PCB traces in the actual power protection circuit to actively adjust the parasitic inductance L of the traces. p and parasitic capacitance C p This optimizes ESD protection performance.

[0055] This application embodiment changes the parasitic inductance L in the high-frequency circuit model. p and parasitic capacitance C p This allows the resonant point of the adjusted high-frequency circuit model to be far away from the preset interference frequency band when facing ESD pulse interference, thereby reducing the adverse effects of ESD pulse signals on the circuit in this frequency band. Based on this, the wiring parameters in the power supply protection circuit are adjusted, which not only ensures the effective improvement of the ESD protection performance of the power supply protection circuit, but also reduces the modification cost of circuit adjustment.

[0056] It should be noted that in the early stages of power supply protection circuit design, it is preferable to optimize ESD performance by adjusting the wiring, as this method is less costly than other adjustment methods.

[0057] In other embodiments of this application, step S5 may include: When the target resonant point is within the preset interference frequency band, the first junction capacitance C j1 Second junction capacitance C j2 Adjustments were made to obtain the adjusted high-frequency circuit model. The frequency response characteristics of the adjusted high-frequency circuit model under ESD pulse signal were verified, and if the verification was successful, the component parameters of the power supply protection circuit were adjusted according to the adjusted high-frequency circuit model.

[0058] Specifically, in this embodiment, the preset interference frequency band is also determined based on the energy concentration band of the ESD pulse. If the target resonant point is within the preset interference frequency band, the position of the resonant point can be changed by replacing the anti-reverse diode with a different junction capacitance, i.e., adjusting the first junction capacitance C in the high-frequency circuit model. j1 Second junction capacitance C j2The capacitance value is obtained to obtain the adjusted high-frequency circuit model, thereby changing the impedance and scattering parameters of the LC resonant circuit in the high-frequency circuit model, so that the target resonant point shifts away from the energy concentration band of the ESD pulse.

[0059] Similarly, simulation software is used to verify whether the adjustment of junction capacitance is effective in the adjusted high-frequency circuit model. If the verification is successful, the adjusted high-frequency circuit model can be used as a reference to adjust the selection of anti-reverse diodes or TVS diodes in the actual power supply protection circuit. For example, other diode devices with different junction capacitances can be selected to optimize ESD protection performance.

[0060] In some other embodiments of this application, step S5 may include: With the target resonant point within a preset interference frequency band, the key locations of the high-frequency circuit model are determined, and passive components are added at these key locations to obtain the adjusted high-frequency circuit model. The frequency response characteristics of the adjusted high-frequency circuit model under ESD pulse signals are verified, and if the verification is successful, passive components are added to the power supply protection circuit based on the adjusted high-frequency circuit model.

[0061] Specifically, the embodiments of this application also determine the aforementioned preset interference frequency band based on the energy concentration band of the ESD pulse. If the target resonant point is within the preset interference frequency band, passive devices can be added at key locations such as the anti-reverse diode. For example, a ferrite bead or a resistor with a small resistance value can be connected in series with the anti-reverse diode, or a capacitor can be connected in parallel across the anti-reverse diode. This results in an adjusted high-frequency circuit model, which changes the impedance or scattering parameters of the LC resonant circuit in the high-frequency circuit model, causing the target resonant point to shift away from the energy concentration band of the ESD pulse.

[0062] Similarly, the effectiveness of the newly added passive components can be verified using simulation software on the adjusted high-frequency circuit model. If the verification is successful, the adjusted high-frequency circuit model can be used as a reference to add corresponding passive components at the corresponding positions in the actual power supply protection circuit to optimize the ESD protection performance.

[0063] This application embodiment adjusts the junction capacitance parameters of the reverse polarity protection diode D1 and the TVS diode D2, or adds passive components, so that the resonant point of the adjusted high-frequency circuit model is far away from the preset interference frequency band when facing ESD pulse interference. This reduces the adverse effects of ESD pulse signals on the circuit in this frequency band. Based on this, the component parameters in the power supply protection circuit are adjusted. While ensuring effective improvement of the ESD protection performance of the power supply protection circuit, it does not require complex changes to the circuit layout, thus reducing the difficulty of performance optimization.

[0064] It should be noted that since the PCB layout of the power protection circuit is usually fixed in the later stages of design, the above adjustment methods, such as adjusting the junction capacitance or adding passive components, can be used in the later stages of design to reduce the difficulty of adjusting the circuit structure.

[0065] Furthermore, overshoot caused by resonance requires TVS diodes to have lower clamping voltages and stronger energy absorption capabilities. Compared with related technologies, the embodiments of this application effectively eliminate resonance overshoot by proactively adjusting the circuit PCB layout in the early stages of design. This allows the TVS diodes to operate in their optimal design state, enabling the selection of lower-specification and lower-cost TVS diodes to achieve the same required ESD protection performance. Moreover, the embodiments of this application can reduce the potential ESD failure risk caused by parasitic parameters in advance during the design phase, thereby reducing trial-and-error costs and the number of test iterations in the R&D cycle, improving the first-time success rate and reliability of the design, and ultimately optimizing system costs.

[0066] Furthermore, in some embodiments of this application, after adjusting the power supply protection circuit, vector network analysis can be used to analyze the scattering parameters of the actual test power supply circuit, and the actual resonant point can be determined by measuring the input reflection coefficient, thereby ensuring that the final design meets the requirements through iteration.

[0067] Accordingly, please refer to Figure 6 This application also provides a performance optimization device for a power supply protection circuit, wherein the device includes: The simulation module 100 is used to construct a high-frequency circuit model of the power supply protection circuit and to simulate the frequency response characteristics of the high-frequency circuit model under the action of ESD pulse signal to obtain simulation results. For details, please refer to step S1.

[0068] The resonance analysis module 200 is used to determine the target resonance point of the power supply protection circuit based on the simulation results. For details, please refer to step S3.

[0069] The adjustment module 300 is used to adjust the power supply protection circuit based on the target resonant point in order to optimize the ESD protection performance of the power supply protection circuit at the target resonant point. For details, please refer to step S5.

[0070] In some embodiments of this application, the simulation module 100 includes: The pulse input unit 110 is used to input the ESD pulse signal into the high-frequency circuit model, wherein the ESD pulse signal is generated by a pre-built current source model. The frequency sweep analysis unit 120 performs frequency sweep analysis on the impedance or scattering parameters of the high-frequency circuit model in response to the ESD pulse signal to obtain the frequency domain characteristic curve of the impedance or scattering parameters, and uses the frequency domain characteristic curve as the simulation result.

[0071] In some embodiments of this application, the resonance analysis module 200 includes: The initial resonance point is determined based on the valley point of the frequency domain characteristic curve; The resonance point determination unit 210 selects target resonance points that meet preset conditions from the initial resonance points.

[0072] The resonant point screening unit 220 selects target resonant points that meet preset conditions from the initial resonant points.

[0073] In some embodiments of this application, the adjustment module 300 includes: The first adjustment unit 310 is used to adjust the parasitic inductance L when the target resonant point is within a preset interference frequency band. p and parasitic capacitance C p Adjustments were made to obtain the adjusted high-frequency circuit model; the frequency response characteristics of the adjusted high-frequency circuit model under the action of ESD pulse signal were verified, and if the verification was successful, the wiring parameters of the power protection circuit were adjusted according to the adjusted high-frequency circuit model.

[0074] The second adjustment unit 320 is used to adjust the first junction capacitance C when the target resonant point is within a preset interference frequency band. j1 Second junction capacitance C j2 Adjustments were made to obtain the adjusted high-frequency circuit model; the frequency response characteristics of the adjusted high-frequency circuit model under ESD pulse signal were verified, and if the verification was successful, the component parameters of the power supply protection circuit were adjusted according to the adjusted high-frequency circuit model. The third adjustment unit 330 is used to determine the key position of the high-frequency circuit model when the target resonance point is within the preset interference frequency band, and to add passive components at the key position to obtain the adjusted high-frequency circuit model; and to verify the frequency response characteristics of the adjusted high-frequency circuit model under the action of ESD pulse signal, and, if the verification is successful, to add passive components in the power protection circuit according to the adjusted high-frequency circuit model.

[0075] The specific configurations and further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0076] The performance optimization device proposed in this application constructs a high-frequency circuit model and simulates its frequency response characteristics under ESD pulse signals. This allows for accurate simulation of the power supply protection circuit's performance under actual ESD impact, providing a precise basis for determining the target resonant point. Based on the target resonant point, key frequency points in the circuit that may be significantly affected by ESD are accurately located. Subsequently, the power supply protection circuit is adjusted for the target resonant point, thereby avoiding the main distribution frequency band of ESD energy. This effectively reduces the energy coupling amplification of ESD at the target resonant point, improves the ESD anti-interference capability of the power supply protection circuit, and ultimately enhances system reliability and stability, reducing the risk of damage to downstream loads due to ESD.

[0077] In this embodiment, the performance optimization device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0078] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application, such as... Figure 7 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0079] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0080] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0081] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0082] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0083] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0084] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0085] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0086] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

[0087] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0088] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0089] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0090] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0091] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0092] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for optimizing the performance of a power supply protection circuit, characterized in that, The method includes: A high-frequency circuit model of the power supply protection circuit is constructed, and the frequency response characteristics of the high-frequency circuit model under the action of ESD pulse signal are simulated to obtain simulation results. The target resonant point of the power supply protection circuit is determined based on the simulation results. The power supply protection circuit is adjusted based on the target resonant point to optimize its ESD protection performance at the target resonant point.

2. The performance optimization method for the power supply protection circuit according to claim 1, characterized in that, The simulation of the frequency response characteristics of the high-frequency circuit model under the action of ESD pulse signal, to obtain simulation results, includes: The ESD pulse signal is input into the high-frequency circuit model, wherein the ESD pulse signal is generated by a pre-constructed current source model; A frequency sweep analysis is performed on the impedance or scattering parameters of the high-frequency circuit model in response to the ESD pulse signal to obtain the frequency domain characteristic curve of the impedance or scattering parameters, and the frequency domain characteristic curve is used as the simulation result.

3. The performance optimization method for the power supply protection circuit according to claim 2, characterized in that, Determining the target resonant point of the power supply protection circuit based on the simulation results includes: The initial resonance point is determined based on the valley point of the frequency domain characteristic curve; Target resonance points that meet preset conditions are selected from the initial resonance points.

4. The performance optimization method for the power supply protection circuit according to claim 1, characterized in that, The high-frequency circuit model includes a reverse polarity protection diode D1, a TVS diode D2, and a parasitic inductor L. p Parasitic capacitance C p First junction capacitance C j1 and the second junction capacitance C j2 ; Among them, the reverse polarity protection diode D1, the TVS diode D2, and the parasitic inductor L p The parasitic capacitance C p The first junction capacitance C is connected in series. j1 The second junction capacitance C is connected in parallel across the anti-reverse connection diode D1. j2 It is connected in parallel across the two ends of the TVS tube D2.

5. The performance optimization method for the power supply protection circuit according to claim 4, characterized in that, The adjustment of the power supply protection circuit based on the target resonant point includes: When the target resonant point is within a preset interference frequency band, the parasitic inductance L... p and the parasitic capacitance C p Adjustments were made, and the adjusted high-frequency circuit model was obtained; Verify the frequency response characteristics of the adjusted high-frequency circuit model under the action of the ESD pulse signal, and if the verification is successful, adjust the wiring parameters of the power protection circuit according to the adjusted high-frequency circuit model.

6. The performance optimization method for the power supply protection circuit according to claim 4, characterized in that, The adjustment of the power supply protection circuit based on the target resonant point includes: When the target resonant point is within a preset interference frequency band, the first junction capacitance C j1 and the second junction capacitance C j2 Adjustments were made, and the adjusted high-frequency circuit model was obtained; Verify the frequency response characteristics of the adjusted high-frequency circuit model under the action of the ESD pulse signal, and if the verification is successful, adjust the component parameters of the power supply protection circuit according to the adjusted high-frequency circuit model.

7. The performance optimization method for the power supply protection circuit according to claim 4, characterized in that, The adjustment of the power supply protection circuit based on the target resonant point includes: When the target resonance point is within a preset interference frequency band, the key position of the high-frequency circuit model is determined, and passive components are added at the key position to obtain the adjusted high-frequency circuit model. Verify the frequency response characteristics of the adjusted high-frequency circuit model under the action of the ESD pulse signal, and if the verification is successful, add the passive device to the power protection circuit according to the adjusted high-frequency circuit model.

8. A performance optimization device for a power supply protection circuit, characterized in that, The device includes: The simulation module is used to construct a high-frequency circuit model of the power supply protection circuit and to simulate the frequency response characteristics of the high-frequency circuit model under the action of ESD pulse signal to obtain simulation results. The resonance analysis module is used to determine the target resonance point of the power supply protection circuit based on the simulation results. An adjustment module is used to adjust the power supply protection circuit based on the target resonant point in order to optimize the ESD protection performance of the power supply protection circuit at the target resonant point.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the performance optimization method of the power protection circuit according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the performance optimization method for the power protection circuit according to any one of claims 1 to 7.

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