PCB multi-heat-source optimal arrangement method and device based on ecological algorithm

Abstract

The invention relates to the technical field of circuit layout, in particular to a PCB multi-heat-source optimal arrangement method and device based on an ecological algorithm, and the method comprises the steps: obtaining the convective heat transfer coefficient distribution of the surface of a target PCB based on a preset convective heat transfer coefficient relation and the shape of the target PCB, and obtaining the convective heat transfer coefficient distribution of the surface of the target PCB based on the power and number of target chips of the target PCB; the method comprises the following steps: generating a chip sequence, then generating a distribution placement position of a target chip, calculating a heat dissipation area needing to be distributed to the target chip based on a preset ecological algorithm, and detecting whether a preset geometric constraint condition is met or not, so that when the preset geometric constraint condition is detected to be met and placement of the target chip is completed, the target chip is distributed to the target chip. And generating a multi-chip heat source arrangement scheme on the target PCB. Therefore, the technical problems that the PCB optimized layout does not meet the actual heat dissipation requirement and the universality is poor due to the fact that the actual physical mechanism of PCB heat dissipation is not fully combined in the related technology are solved.

Description

Technical Field

[0001] This application relates to the field of circuit layout technology, and in particular to a method and apparatus for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm. Background Technology

[0002] In recent years, with the development of manufacturing processes and the increasing demands of users, electronic devices and energy storage systems have been trending towards miniaturization, while their internal power has continued to rise. Simultaneously, the heat flux of different chip heat sources varies greatly, making it easy for localized high-temperature hotspots to occur when multiple chip heat sources are arranged. These localized hotspots can lead to the accumulation of localized thermal stress, causing wafer warping and deformation, and in severe cases, even cracking and other structural damage, significantly impacting the normal operation and lifespan of the devices. Therefore, ensuring good heat dissipation performance of the product structure has become a key consideration in electronic product design. In current small electronic devices, chip heat sources are mainly concentrated on the printed circuit board (PCB). A large amount of heat is generated and accumulates on the PCB surface; therefore, the heat dissipation effect of the PCB surface directly determines the heat dissipation performance of the electronic product, making PCB surface heat dissipation a critical aspect of electronic product thermal design. Optimizing the layout of multiple chip heat sources on the PCB is an effective means to solve the problem of localized high-temperature hotspots on the PCB surface and improve the PCB's heat dissipation performance.

[0003] In related technologies, heat source layout primarily relies on engineers' engineering experience to provide a general layout plan. It also utilizes computers to perform extensive calculations based on specific optimization algorithms to obtain the optimal layout solution. Commonly used optimization algorithms include Ant Colony Optimization (ACO), Simulated Annealing, Genetic Algorithm (GA), Particle Swarm Optimization, as well as deep learning, neural architectures, and greedy biomimetic methods. These algorithms either seek optimal solutions by mimicking the evolution of ecosystems, simulate the greedy characteristics of organisms to obtain local optima, or derive optimal solutions based on first-principles logical deduction, providing technical support for PCB layout optimization to a certain extent.

[0004] However, in related technologies, due to the complexity of multiple heat source fields, the diversity of device heat dissipation structures, and the fluid-structure-thermal coupling characteristics of heat dissipation systems, theoretical derivation is difficult to form a universally applicable optimal layout scheme. This makes it impossible to provide stable support for PCB layout optimization from a theoretical perspective. At the same time, the optimization logic is derived by simply imitating natural phenomena, biological characteristics, or relying on basic principles, without fully combining the actual physical mechanism of PCB heat dissipation. This makes it impossible to provide an optimized PCB layout that meets actual heat dissipation requirements from the perspective of heat dissipation theory, which urgently needs to be solved. Summary of the Invention

[0005] This application provides a method and apparatus for optimizing the layout of multiple heat sources on a PCB board based on an ecological algorithm, in order to solve the problem in related technologies that the optimized layout of the PCB does not meet the actual heat dissipation requirements and has poor universality due to the failure to fully combine the actual physical mechanism of PCB heat dissipation.

[0006] The first aspect of this application provides a method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm, comprising the following steps: obtaining at least one size parameter of a target PCB board to determine the shape of the target PCB board; obtaining the convective heat transfer coefficient distribution on the surface of the target PCB board based on a preset convective heat transfer coefficient relationship and the shape; generating a chip sorting based on the power and number of target chips on the target PCB board; generating the allocation and placement positions of the target chips based on the convective heat transfer coefficient distribution and the chip sorting, and calculating the heat dissipation area to be allocated to the target chips based on a preset ecological algorithm, and detecting whether a preset geometric constraint condition is met; if the preset geometric constraint condition is met and all target chips are placed, generating a multi-chip heat source arrangement scheme on the target PCB board according to the allocation and placement positions of the target chips and the corresponding heat dissipation area.

[0007] Through the above technical means, the embodiments of this application can obtain the convective heat transfer coefficient distribution on the surface of the target PCB board, and generate a chip sorting based on the power and number of target chips on the target PCB board, thereby generating the allocation and placement positions of the target chips, calculating the heat dissipation area to be allocated to the target chips, and detecting whether the preset geometric constraints are met. Thus, a multi-chip heat source arrangement scheme on the target PCB board is generated according to the allocation and placement positions of the target chips and the corresponding heat dissipation area. On the one hand, the convective heat transfer coefficient distribution can be used to provide a layout basis that conforms to the real thermal environment, fully combining the actual physical mechanism of PCB heat dissipation. On the other hand, the preset ecological algorithm can be used to calculate the heat dissipation area of ​​the target chips, realizing a dynamic balance between the heat dissipation requirements of the target chips and the heat dissipation capacity of the area, which not only meets the actual heat dissipation requirements, but also enhances the universality of PCB optimization layout.

[0008] Optionally, in one embodiment of this application, obtaining the convective heat transfer coefficient distribution of the surface of the target PCB board includes: obtaining an initial convective heat transfer coefficient distribution based on a pre-built slit convective heat transfer model using an empirical formula for the slit convective heat transfer coefficient; dividing the target PCB board from bottom to top into multiple segments, and correcting the initial convective heat transfer coefficient distribution based on the convective heat transfer coefficient function relationship of each segment to obtain the convective heat transfer coefficient distribution.

[0009] Through the above technical means, the embodiments of this application can establish the calculation basis of the convective heat transfer coefficient based on the slit convective heat transfer model, ensuring that the analysis has theoretical rigor. In addition, the flow channel changes that may exist from the bottom to the top of the target PCB board can be modified in segments to adapt to the local flow field characteristics, making up for the adaptation defects of the single model to the actual structure. Thus, the distribution of the convective heat transfer coefficient can reflect the real heat exchange capacity of the target PCB board surface, providing a reliable basis for layout optimization.

[0010] Optionally, in one embodiment of this application, the step of calculating the heat dissipation area to be allocated to the target chip based on a preset ecological algorithm includes: setting a random placement position for the target chip, wherein the random placement position is the location of the chip center; calculating the heat dissipation area to be allocated to the target chip using the preset ecological algorithm; detecting whether the heat dissipation area to be allocated to the target chip overlaps with the heat dissipation area to be allocated to other chips, wherein if they do not overlap, the setting is iterative, otherwise the calculation is iterative, until the heat dissipation area to be allocated to the target chip is obtained.

[0011] Through the above technical means, the embodiments of this application can realize the dynamic balance simulation of the heat dissipation requirements of the target chip and the heat dissipation capacity of the area according to the ecological algorithm, so that the heat dissipation area calculation conforms to the actual heat dissipation law. At the same time, conflict detection can be performed to ensure that the heat dissipation area has no spatial overlap, ensuring the feasibility of optimized layout, thereby improving the overall heat dissipation efficiency of the target PCB board and reducing the risk of local hot spots.

[0012] Optionally, in one embodiment of this application, the step of calculating the heat dissipation area to be allocated to the target chip using the preset ecological algorithm includes: calculating the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB board; calculating the global average heat flux density when the target PCB board reaches ecological balance; reading the power of the target chip and obtaining the local convective heat transfer coefficient at the center of the chip, so as to calculate the heat dissipation area to be allocated to the target chip by making the local heat flux density equal to the global average heat flux density.

[0013] Through the above technical means, the embodiments of this application can ensure that the heat dissipation area is allocated within the physical capacity range of the target PCB board based on the calculation of total power and total area, avoiding engineering infeasibility caused by over-allocation. At the same time, by constraining the local heat flux density to be equal to the global average heat flux density, the overall heat distribution of the target PCB board is made more uniform, avoiding local heat flux concentration or resource waste, and reducing the risk of local hot spots.

[0014] Optionally, in one embodiment of this application, the formula for calculating the area of ​​the heat dissipation region is: , , , , , , in, The total power of the target chip. The power of the target chip. This refers to the area of ​​the heat dissipation area that needs to be allocated to the target chip. The average temperature of the target chip is the temperature difference between the target chip and the gas. The local convective heat transfer coefficient of the target chip is denoted as . The radius corresponding to the area of ​​the heat dissipation region allocated to the target chip. The convective heat transfer coefficient is... Nu For Nusselt numbers, The thermal conductivity of air, air velocity, The kinematic viscosity of air, For the channel height, The characteristic length of the airflow direction. It is the Reynolds number.

[0015] Through the above technical means, the embodiments of this application can calculate the heat dissipation area that the target chip needs to be allocated, provide a theoretical basis for the layout of the target PCB board, match the heat dissipation requirements of the target chip with the heat dissipation capacity of the area, effectively avoid local overheating, and improve the overall heat dissipation efficiency.

[0016] A second aspect of this application provides a PCB board multi-heat source optimization layout device based on an ecological algorithm, comprising: a determining module, configured to acquire at least one size parameter of a target PCB board to determine the shape of the target PCB board; an acquiring module, configured to acquire the convective heat transfer coefficient distribution on the surface of the target PCB board based on a preset convective heat transfer coefficient relationship and the shape; a first generating module, configured to generate a chip sorting based on the power and number of target chips on the target PCB board; a detecting module, configured to generate the allocation and placement positions of the target chips based on the convective heat transfer coefficient distribution and the chip sorting, calculate the heat dissipation area to be allocated to the target chips based on a preset ecological algorithm, and detect whether a preset geometric constraint condition is met; and a second generating module, configured to generate a multi-chip heat source layout scheme on the target PCB board according to the allocation and placement positions of the target chips and the corresponding heat dissipation area when the preset geometric constraint condition is met and all target chips are placed.

[0017] Through the above technical means, the embodiments of this application can obtain the convective heat transfer coefficient distribution on the surface of the target PCB board, and generate a chip sorting based on the power and number of target chips on the target PCB board, thereby generating the allocation and placement positions of the target chips, calculating the heat dissipation area to be allocated to the target chips, and detecting whether the preset geometric constraints are met. Thus, a multi-chip heat source arrangement scheme on the target PCB board is generated according to the allocation and placement positions of the target chips and the corresponding heat dissipation area. On the one hand, the convective heat transfer coefficient distribution can be used to provide a layout basis that conforms to the real thermal environment, fully combining the actual physical mechanism of PCB heat dissipation. On the other hand, the preset ecological algorithm can be used to calculate the heat dissipation area of ​​the target chips, realizing a dynamic balance between the heat dissipation requirements of the target chips and the heat dissipation capacity of the area, which not only meets the actual heat dissipation requirements, but also enhances the universality of PCB optimization layout.

[0018] Optionally, in one embodiment of this application, the acquisition module includes: a first generation unit, used to obtain an initial convection heat transfer coefficient distribution based on a pre-built slit convection heat transfer model and using an empirical formula for the slit convection heat transfer coefficient; and a second generation unit, used to divide the target PCB board from bottom to top into multiple segments, and correct the initial convection heat transfer coefficient distribution based on the convection heat transfer coefficient function relationship of each segment to obtain the convection heat transfer coefficient distribution.

[0019] Through the above technical means, the embodiments of this application can establish the calculation basis of the convective heat transfer coefficient based on the slit convective heat transfer model, ensuring that the analysis has theoretical rigor. In addition, the flow channel changes that may exist from the bottom to the top of the target PCB board can be modified in segments to adapt to the local flow field characteristics, making up for the adaptation defects of the single model to the actual structure. Thus, the distribution of the convective heat transfer coefficient can reflect the real heat exchange capacity of the target PCB board surface, providing a reliable basis for layout optimization.

[0020] Optionally, in one embodiment of this application, the detection module includes: a setting unit, used to set a random placement position of the target chip, wherein the random placement position is the location of the chip center; a calculation unit, used to calculate the heat dissipation area to be allocated to the target chip using the preset ecological algorithm; and a third generation unit, used to detect whether the heat dissipation area to be allocated to the target chip overlaps with the heat dissipation area to be allocated to other chips, wherein if they do not overlap, the setting is iterative, otherwise the calculation is iterative, until the heat dissipation area to be allocated to the target chip is obtained.

[0021] Through the above technical means, the embodiments of this application can realize the dynamic balance simulation of the heat dissipation requirements of the target chip and the heat dissipation capacity of the area according to the ecological algorithm, so that the heat dissipation area calculation conforms to the actual heat dissipation law. At the same time, conflict detection can be performed to ensure that the heat dissipation area has no spatial overlap, ensuring the feasibility of optimized layout, thereby improving the overall heat dissipation efficiency of the target PCB board and reducing the risk of local hot spots.

[0022] Optionally, in one embodiment of this application, the calculation unit includes: a first calculation subunit for calculating the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB board; a second calculation subunit for calculating the global average heat flux density when the target PCB board reaches ecological balance; and a generation subunit for reading the power of the target chip and obtaining the local convective heat transfer coefficient at the center of the chip, so as to calculate the heat dissipation area that the target chip needs to be allocated by making the local heat flux density equal to the global average heat flux density.

[0023] Through the above technical means, the embodiments of this application can ensure that the heat dissipation area is allocated within the physical capacity range of the target PCB board based on the calculation of total power and total area, avoiding engineering infeasibility caused by over-allocation. At the same time, by constraining the local heat flux density to be equal to the global average heat flux density, the overall heat distribution of the target PCB board is made more uniform, avoiding local heat flux concentration or resource waste, and reducing the risk of local hot spots.

[0024] Optionally, in one embodiment of this application, the formula for calculating the area of ​​the heat dissipation region is: , , , , , , in, The total power of the target chip. The power of the target chip. This refers to the area of ​​the heat dissipation area that needs to be allocated to the target chip. The average temperature of the target chip is the temperature difference between the target chip and the gas. The local convective heat transfer coefficient of the target chip is denoted as . The radius corresponding to the area of ​​the heat dissipation region allocated to the target chip. The convective heat transfer coefficient is... Nu For Nusselt numbers, The thermal conductivity of air, air velocity, The kinematic viscosity of air, For the channel height, The characteristic length of the airflow direction. It is the Reynolds number.

[0025] Through the above technical means, the embodiments of this application can calculate the heat dissipation area that the target chip needs to be allocated, provide a theoretical basis for the layout of the target PCB board, match the heat dissipation requirements of the target chip with the heat dissipation capacity of the area, effectively avoid local overheating, and improve the overall heat dissipation efficiency.

[0026] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor executes the program to implement the PCB board multi-heat source optimization layout method based on ecological algorithms as described in the above embodiments.

[0027] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm.

[0028] The fifth aspect of this application provides a computer program product, including a computer program that, when executed, implements the above-described method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm.

[0029] This application embodiment can obtain the convective heat transfer coefficient distribution on the surface of the target PCB board, and generate a chip sorting based on the power and number of target chips on the target PCB board. It then generates the assigned placement positions of the target chips, calculates the required heat dissipation area for each target chip, and checks whether preset geometric constraints are met. Based on the assigned placement positions of the target chips and the corresponding heat dissipation area, a multi-chip heat source arrangement scheme is generated on the target PCB board. On the one hand, the convective heat transfer coefficient distribution provides a layout basis that conforms to the real thermal environment, fully combining the actual physical mechanism of PCB heat dissipation. On the other hand, a preset ecological algorithm is used to calculate the heat dissipation area of ​​the target chip, achieving a dynamic balance between the heat dissipation requirements of the target chip and the heat dissipation capacity of the area. This not only meets actual heat dissipation requirements but also enhances the universality of PCB optimized layout. Therefore, it solves the problem in related technologies where the failure to fully combine the actual physical mechanism of PCB heat dissipation leads to PCB optimized layouts that do not meet actual heat dissipation requirements and have poor universality.

[0030] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0031] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of an optimization system provided according to an embodiment of this application; Figure 2 This is a flowchart of a method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm, according to an embodiment of this application. Figure 3 This is a schematic diagram of a target PCB board size parameter input interface according to an embodiment of this application; Figure 4 This is a schematic diagram of airflow between a target PCB board and a surrounding baffle according to an embodiment of this application; Figure 5 This is a schematic diagram of the height variation curve of a target PCB board according to an embodiment of this application; Figure 6 This is a schematic diagram of air flowing on the surface of a target PCB board according to an embodiment of this application; Figure 7 This is a schematic diagram of an air control body for height variation according to an embodiment of this application; Figure 8 This is a schematic diagram of the input interface for the global convective heat transfer coefficient distribution of a target PCB board according to an embodiment of this application; Figure 9 This is a schematic diagram of the convective heat transfer coefficient distribution obtained by using a slotted convection heat transfer model for a target PCB board according to an embodiment of this application; Figure 10 This is a schematic diagram of the target chip power and number input interface to be arranged according to an embodiment of this application; Figure 11 This is a schematic diagram of the arrangement of 7 chips on a PCB board according to an embodiment of this application, provided by using an optimization algorithm. Figure 12 This is a schematic diagram of the thermal simulation results of the target PCB board and target chip in the initial layout according to an embodiment of this application; Figure 13 This is a schematic diagram of the simulation results of the target PCB board and target chip in optimized layout according to an embodiment of this application; Figure 14 This is a schematic diagram showing a temperature comparison between an optimized layout and an initial layout of a target chip according to an embodiment of this application. Figure 15 This is a flowchart illustrating the working principle of the PCB board multi-heat source optimization layout method based on ecological algorithms provided in the embodiments of this application; Figure 16 This is a schematic diagram of a block diagram of a PCB board multi-heat source optimization layout device based on an ecological algorithm provided in an embodiment of this application; Figure 17 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application.

[0032] Figure label: 101-PCB board, 102-chip; 160-PCB board multi-heat source optimization layout device based on ecological algorithm, 100-determination module, 200-acquisition module, 300-first generation module, 400-detection module, 500-second generation module; 1701-memory, 1702-processor, 1703-communication interface. Detailed Implementation

[0033] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0034] The following describes, with reference to the accompanying drawings, a method and apparatus for optimizing the layout of multiple heat sources on a PCB board based on an ecological algorithm, according to embodiments of this application. Addressing the problems mentioned in the background art, where the failure to fully incorporate the actual physical mechanisms of PCB heat dissipation leads to PCB optimization layouts that do not meet actual heat dissipation requirements and have poor universality, this application provides a method for optimizing the layout of multiple heat sources on a PCB board based on an ecological algorithm. In this method, the convective heat transfer coefficient distribution on the surface of the target PCB board is obtained. Based on the power and number of target chips on the target PCB board, a chip sorting is generated, followed by the generation of the target chip's allocation and placement positions. The required heat dissipation area for the target chip is calculated, and whether preset geometric constraints are met is checked. Thus, a multi-chip heat source layout scheme is generated on the target PCB board based on the target chip's allocation and placement positions and the corresponding heat dissipation area. On the one hand, the convective heat transfer coefficient distribution provides a layout basis that conforms to the real thermal environment, fully incorporating the actual physical mechanisms of PCB heat dissipation. On the other hand, the preset ecological algorithm is used to calculate the heat dissipation area of ​​the target chip, achieving a dynamic balance between the target chip's heat dissipation requirements and the area's heat dissipation capacity. This not only meets actual heat dissipation requirements but also enhances the universality of the optimized PCB layout. This solves the problem in related technologies where the failure to fully incorporate the actual physical mechanisms of PCB heat dissipation leads to PCB optimization layouts that do not meet actual heat dissipation requirements and have poor universality.

[0035] Before introducing the PCB board multi-heat source optimization layout method based on ecological algorithm provided in the embodiments of this application, the optimization system will be briefly introduced first.

[0036] like Figure 1 As shown, the optimization system includes a PCB board 101 and chips 102. The shape of the PCB board is variable, and the number and power of the chips are variable. Each chip has a corresponding heat dissipation power, and heat can be removed through air convection.

[0037] In the optimization system, the embodiments of this application can incorporate biomimetic concepts. The dynamic balance of multiple populations within an ecosystem depends on the matching degree between resource supply and the needs of each species population: when resource supply can meet the needs of various populations, a stable coexistence can be maintained among the populations; when resource supply cannot meet the needs of various populations, it is difficult for them to maintain a stable coexistence, which can easily lead to competitive exclusion or aggressive behavior, resulting in local ecological imbalance. This dynamic balance mechanism driven by resource supply and demand is the core foundation of ecosystem stability.

[0038] Based on biomimetic principles, this embodiment of the application treats the entire PCB board as an ecosystem, with the chips on the board corresponding to species within the system. The power parameters of each chip correspond to the heat it needs to dissipate in a balanced state; this heat dissipation requirement can be understood as the survival needs of that species. Therefore, if the ecological resources provided by the PCB board ecosystem are rationally allocated to ensure that the heat dissipation requirements of each chip are met in a balanced manner, it can be inferred from biomimetic principles that each chip will be in a locally uniform temperature field centered on itself. This not only effectively alleviates local hotspot problems but also significantly improves the overall heat exchange efficiency of the PCB board.

[0039] Specifically, Figure 2 This is a flowchart of a method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm, according to an embodiment of this application.

[0040] like Figure 2 As shown, the PCB board multi-heat source optimization layout method based on ecological algorithm includes the following steps: In step S201, at least one dimensional parameter of the target PCB board is obtained to determine the shape of the target PCB board.

[0041] It is understandable that although the actual structure of a PCB board is relatively complex, it can still be regarded as a rectangular board as a whole. In this embodiment of the application, this rectangular board can be simply cut into two square areas, the lower left corner and the lower right corner.

[0042] like Figure 3The image shows the input interface for inputting the dimensions of the target PCB board. The dimensions can include, but are not limited to, PCB board height, PCB board width, side a, side b, side c, and side d. PCB board height represents the length of the target PCB board, PCB board width represents the width of the target PCB board, side a represents the length of the cut-off portion at the lower left corner of the target PCB board, side b represents the width of the cut-off portion at the lower left corner of the target PCB board, side c represents the length of the cut-off portion at the lower right corner of the target PCB board, and side d represents the width of the cut-off portion at the lower right corner of the target PCB board.

[0043] In some cases, embodiments of this application input the dimensional parameters of the target PCB board, including the following steps: (1) Input the length and width of the target PCB board, with a maximum accuracy of [insert value here]. .

[0044] (2) Input the length and width of the cut-off portion at the lower left corner of the target PCB board, with a maximum accuracy of [missing information]. .

[0045] (3) Input the length and width of the cut-off portion at the lower right corner of the target PCB board, with a maximum accuracy of [missing information]. .

[0046] In step S202, the convective heat transfer coefficient distribution of the target PCB board surface is obtained based on the preset convective heat transfer coefficient relationship and shape.

[0047] In the embodiments of this application, the convective heat transfer coefficient refers to a physical quantity that characterizes the heat transfer capacity between a fluid (such as air, coolant) and a solid surface (such as the surface of a PCB board); the convective heat transfer coefficient relationship is a mathematical correlation describing the relationship between the convective heat transfer coefficient and influencing factors (such as wind speed, fluid temperature, surface roughness); the convective heat transfer coefficient distribution is a spatial variation law reflecting the mapping relationship between spatial location and corresponding convective heat transfer coefficient.

[0048] It is understood that 80% of the heat generated by the chip on the PCB is dissipated through the convective heat transfer process on the PCB surface, and the remaining 20% ​​is dissipated from the chip surface and the back of the PCB. Therefore, the convective heat transfer coefficient distribution of the target PCB surface can be obtained in advance in this embodiment of the application.

[0049] The following details the process of obtaining the convective heat transfer coefficient distribution on the surface of the target PCB board.

[0050] Specifically, in one embodiment of this application, obtaining the convective heat transfer coefficient distribution on the surface of the target PCB board includes: obtaining an initial convective heat transfer coefficient distribution based on a pre-built slit convective heat transfer model using an empirical formula for the slit convective heat transfer coefficient; dividing the target PCB board from bottom to top into multiple segments, and correcting the initial convective heat transfer coefficient distribution based on the convective heat transfer coefficient function relationship of each segment to obtain the convective heat transfer coefficient distribution.

[0051] In the embodiments of this application, the slit convection heat transfer model can be understood as simplifying the flow channel between the target PCB board surface and the air into a slit convection heat transfer analysis model, so as to simplify the calculation process of the convection heat transfer coefficient.

[0052] In some cases, embodiments of this application obtain the convective heat transfer coefficient distribution on the surface of the target PCB board by including the following steps: (1) such as Figure 4 As shown, air flows between the target PCB board and the surrounding baffles. Figure 5 As shown, by It can be seen that among them For the channel height, Given the characteristic length of the airflow direction, embodiments of this application can determine that the airflow on the target PCB surface conforms to the slit convection heat transfer model. The basic expression for the convection heat transfer coefficient can be, but is not limited to, the following: , in, The convective heat transfer coefficient is... Nu For Nusselt numbers, Let be the thermal conductivity of air. In the slit convection heat transfer model, the empirically related expression for the Nusselt number can be, but is not limited to, the following: , in, Re Let be the Reynolds number. The Reynolds number can be expressed, but is not limited to, as: , in, air velocity, Let be the kinematic viscosity of air. Considering all three formulas and eliminating intermediate variables, the final form of the convective heat transfer coefficient can be obtained in the embodiments of this application. Its expression can be, but is not limited to, as:

[0053] , in, This is a constant for combining elements. According to the above expression, the convective heat transfer coefficient is mainly determined by the air velocity and the channel height. For example... Figure 6 As shown, due to the airflow At this point, air will begin to flow out of the outlet, and the continuity equation will no longer be satisfied. Therefore, the subsequent relationship between air velocity and channel height is derived as follows: like Figure 7 As shown, assuming the fluid is a steady, incompressible fluid during the flow process, according to the continuity equation, the volumetric flow rate flowing into the control volume is equal to the volumetric flow rate flowing out, and its expression can be, but is not limited to, as follows: , in, , To control the inflow volume flow rate of the two parts of the volume, , Let be the two outflow volumetric flow rates. Since the interference between layers in laminar flow is relatively small, we further assume that the inflow and outflow volumetric flow rates of the second part are equal. Its expression can be, but is not limited to, as follows: , In this embodiment, the two equations above can be combined to obtain that the first part of the inflow and outflow volumetric flow rates are equal, and its expression can be, but is not limited to, as follows: , Furthermore, in this embodiment, the influence of the boundary layer can be ignored, and it is assumed that the flow velocity is equal at different locations of the control volume. Its expression can be, but is not limited to, as follows:

[0054] Therefore, the ratio of the two inflow flows can be expressed, but is not limited to, as:

[0055] Furthermore, embodiments of this application consider the flow rates of two surfaces perpendicular to the fluid flow direction, and their expressions can be, but are not limited to, as follows:

[0056]

[0057] in, air density, b The width of the slit in the direction perpendicular to the paper (always the same), footer L Indicates the left side of the control body, footer R Indicates the right side of the control body.

[0058] Thus we can conclude that, In the final region, the fluid velocity along the flow direction remains constant. Since the velocity is constant in this region, the global convective heat transfer coefficient can be calculated using the formula for calculating the convective heat transfer coefficient.

[0059] (2) such as Figure 8As shown, this embodiment of the application can modify the slit convection heat transfer model. The modification settings can divide the target PCB board into multiple segments from bottom to top. The modification process can input the start and end positions of each segment, and then set the convection heat transfer coefficient function relationship of each segment. The start position of the first segment must be the bottom of the target PCB board, and the end position of the last segment must be the top of the target PCB board.

[0060] (3) In this embodiment of the application, the target PCB board can be divided into numerous grid points, and then the local convective heat transfer coefficient of each grid point can be calculated and stored to obtain the convective heat transfer coefficient distribution, as shown in the figure. Figure 9 As shown.

[0061] The embodiments of this application can establish the calculation basis of the convective heat transfer coefficient based on the slit convective heat transfer model, ensuring that the analysis has theoretical rigor. In addition, the flow channel changes that may exist from the bottom to the top of the target PCB board can be adapted to the local flow field characteristics by segmental correction, which makes up for the adaptation defects of the single model to the actual structure. Thus, the distribution of the convective heat transfer coefficient can reflect the real heat exchange capacity of the target PCB board surface, providing a reliable basis for layout optimization.

[0062] In step S203, a chip sorting is generated based on the power and number of target chips on the target PCB board.

[0063] In some cases, such as Figure 10 As shown in the embodiment of this application, the power and number of target chips on the target PCB board can be input to generate a chip sorting, including the following steps: (1) Input the power of a new target chip.

[0064] (2) Repeat step (1) until the input is complete.

[0065] (3) Count the total number of input target chips and sort and number the target chips according to their power.

[0066] In the embodiments of this application, there are 7 target chips, and the power of the target chips is arranged from largest to smallest as follows: 0.5W, 0.5W, 0.5W, 0.176W, 0.175W, 0.175W, and 0.084W.

[0067] In step S204, based on the distribution of convective heat transfer coefficient and chip sorting, the allocation and placement position of the target chip is generated, and the heat dissipation area to be allocated to the target chip is calculated based on the preset ecological algorithm, and it is detected whether the preset geometric constraints are met.

[0068] In the embodiments of this application, the preset ecological algorithm can be understood as a pre-constructed optimization algorithm that simulates the population competition, resource allocation, and dynamic balance mechanism of a natural ecosystem. Specifically, the preset ecological algorithm maps the target chip to a population that depends on heat dissipation resources, and achieves a reasonable allocation of heat dissipation area by simulating resource competition (such as competitive exclusion when heat dissipation area overlaps) and adaptation (such as adjusting area size to match space) between populations.

[0069] Furthermore, the preset geometric constraints can be understood as pre-set rules that strictly adhere to physical space limitations during the allocation of heat dissipation area. These rules cover requirements such as the minimum spacing between target chips and the minimum distance between the target chip and the edge of the target PCB board, and are used to ensure the manufacturability, electrical performance, and heat dissipation rationality of the layout. The specific preset geometric constraints can be set by those skilled in the art according to actual conditions, and this application does not impose any specific limitations.

[0070] In some cases, embodiments of this application may allocate placement locations and heat dissipation area for the target chip, including the following steps: (1) is the serial number The target chip is assigned a placement location, which is the center of the chip. This is the initial placement. .

[0071] (2) Calculate the heat dissipation area to be allocated for the current target chip using the ecological algorithm.

[0072] (3) Check whether the heat dissipation area allocated to the current target chip overlaps with the heat dissipation area of ​​the previous target chip and the boundary of the target PCB board.

[0073] Specifically, the radius of the heat dissipation area can be calculated from the area of ​​the heat dissipation area. In this embodiment, the heat dissipation area of ​​the current target chip and the center position of the current target chip can be used to jointly determine whether the boundary of the heat dissipation area of ​​the current target chip intersects with the boundary of the target PCB board. If they intersect, it is determined that there is overlap.

[0074] Meanwhile, in this embodiment, it can determine whether the heat dissipation areas of the current target chip and the previous target chip intersect based on whether the distance between the center of the current target chip and the center of the previous target chip is greater than the sum of the radii of their heat dissipation areas. If they intersect, it is determined that they overlap.

[0075] It should be noted that in this embodiment of the application, when the heat dissipation area allocated to the current target chip does not overlap with the heat dissipation area of ​​the previous target chip or the boundary of the target PCB board, the overall determination is that there is no overlap.

[0076] (4) If there is overlap, repeat steps (2) and (3); if there is no overlap, Repeat steps (1), (2) and (3).

[0077] Specifically, in one embodiment of this application, calculating the heat dissipation area to be allocated to the target chip based on a preset ecological algorithm includes: setting a random placement position for the target chip, wherein the random placement position is the location of the chip center; calculating the heat dissipation area to be allocated to the target chip using the preset ecological algorithm; detecting whether the heat dissipation area to be allocated to the target chip overlaps with the heat dissipation area to be allocated to other chips, wherein if they do not overlap, the setting is iterative, otherwise the calculation is iterative, until the heat dissipation area to be allocated to the target chip is obtained.

[0078] In some cases, embodiments of this application can set a random placement position for the target chip, using the chip center as a reference, to provide initial spatial coordinates for calculating the heat dissipation area, avoiding getting trapped in local optima. Then, based on a preset ecological algorithm, combined with parameters such as chip power and convective heat transfer coefficient, the heat dissipation area required by the target chip to maintain thermal balance is calculated, so that the heat dissipation requirements of the target chip match the heat dissipation capacity of the area. Then, by detecting whether the heat dissipation area of ​​the target chip overlaps with the heat dissipation area of ​​other chips, the optimization path is dynamically adjusted. If there is no overlap, it means that the current position is feasible, and the initial positions of other chips are iteratively adjusted to expand the solution space. If there is an overlap, it means that the current position is not feasible, and the calculation parameters of the preset ecological algorithm are iteratively used to recalculate the heat dissipation area until a reasonable result without spatial conflicts is obtained.

[0079] The embodiments of this application can realize the dynamic balance simulation of the heat dissipation requirements of the target chip and the heat dissipation capacity of the area based on the ecological algorithm, so that the heat dissipation area calculation conforms to the actual heat dissipation law. At the same time, conflict detection can be performed to ensure that the heat dissipation area has no spatial overlap, ensuring the feasibility of optimized layout, thereby improving the overall heat dissipation efficiency of the target PCB board and reducing the risk of local hot spots.

[0080] Furthermore, in one embodiment of this application, the heat dissipation area to be allocated to the target chip is calculated using a preset ecological algorithm, including: calculating the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB board; calculating the global average heat flux density when the target PCB board reaches ecological balance; reading the power of the target chip and obtaining the local convective heat transfer coefficient at the center of the chip, so as to calculate the heat dissipation area to be allocated to the target chip by making the local heat flux density equal to the global average heat flux density.

[0081] In the embodiments of this application, the global average heat flux density refers to the average heat generated per unit area on the upper surface of the target PCB board, which is related to the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB board, analogous to the resource carrying capacity limit per unit space in an ecosystem. Additionally, the local heat flux density refers to the heat generated per unit area in the region where the target chip is located, which is related to the power of the target chip and the area of ​​the heat dissipation region of the target chip.

[0082] In addition, the local convective heat transfer coefficient refers to the heat exchange efficiency between the air and the surface of the target PCB board at the center of the target chip. This parameter is related to the local flow field (such as wind speed and airflow disturbance) and geometry.

[0083] In some cases, embodiments of this application may first calculate the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB board. Then, based on the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB board, the global average heat flux density when the target PCB board reaches ecological balance is calculated. Then, the power of the target chip is read, and the local convective heat transfer coefficient is obtained through the location of the chip center. Based on the principle that the local heat flux density is equal to the global average heat flux density, the heat dissipation area that the target chip needs to be allocated is calculated.

[0084] The embodiments of this application can ensure that the heat dissipation area is allocated within the physical capacity range of the target PCB board based on the calculation of total power and total area, avoiding engineering infeasibility caused by over-allocation. At the same time, by constraining the local heat flux density to be equal to the global average heat flux density, the overall heat distribution of the target PCB board is more uniform, avoiding local heat flux concentration or resource waste, and reducing the risk of local hot spots.

[0085] Optionally, in one embodiment of this application, the formula for calculating the area of ​​the heat dissipation region is: , , , , , , in, The total power of the target chip, For the power of the target chip, The area of ​​the heat dissipation area that needs to be allocated to the target chip. The average temperature of the target chip and the temperature difference of the gas. The local convective heat transfer coefficient of the target chip is denoted as . The radius corresponding to the area of ​​the heat dissipation region allocated to the target chip. The convective heat transfer coefficient is... Nu For Nusselt numbers, The thermal conductivity of air, air velocity, The kinematic viscosity of air, For the channel height, The characteristic length of the airflow direction. It is the Reynolds number.

[0086] In actual implementation, the embodiments of this application can quantify and deduce the heat dissipation area that the target chip needs to be allocated based on the fact that the local heat flux density is equal to the global average heat flux density and by using the empirical correlation between the Nusselt number and the Reynolds number in the slit convection scenario.

[0087] The embodiments of this application can calculate the heat dissipation area that the target chip needs to be allocated, providing a theoretical basis for the layout of the target PCB board, so that the heat dissipation requirements of the target chip are matched with the heat dissipation capacity of the area, effectively avoiding local overheating and improving the overall heat dissipation efficiency.

[0088] Furthermore, the expression used in this application embodiment to calculate whether the heat dissipation area to be allocated to the target chip coincides with the heat dissipation area of ​​the previous target chip and the boundary of the PCB board can be, but is not limited to, as follows: , , , , , in, Let x be the x-coordinate of the target chip. The vertical coordinate of the target chip is denoted as . Let be the radius of the heat dissipation area of ​​the target chip. This represents the maximum horizontal coordinate of the heat dissipation area of ​​the target chip. Let x be the minimum value of the heat dissipation area of ​​the target chip. This represents the maximum value of the ordinate of the heat dissipation area of ​​the target chip. Let be the minimum value of the ordinate of the heat dissipation area of ​​the target chip. This represents the center distance between the target chip and the previous target chip.

[0089] In step S205, when it is detected that the preset geometric constraints are met and all target chips have been placed, a multi-chip heat source arrangement scheme on the target PCB is generated according to the assigned placement position of the target chips and the corresponding heat dissipation area.

[0090] In some cases, embodiments of this application can generate a multi-chip heat source arrangement scheme on the target PCB board based on the allocation and placement position of the target chip and the corresponding heat dissipation area. The steps are as follows: (1) Check whether all target chips have been successfully placed. If successful, this embodiment of the application can draw a multi-chip heat source arrangement scheme on the target PCB board according to the position of the target chip and the corresponding heat dissipation area, and then output the arrangement result, thereby ending the optimization layout; if unsuccessful, this embodiment of the application executes step (2).

[0091] (2) Reduce the total area that can be allocated on the upper surface of the target PCB board in step S204, and repeat step S204 until all target chips are successfully placed.

[0092] For example, such as Figure 11 As shown, this embodiment of the application ultimately generates a multi-chip heat source arrangement scheme on the target PCB board. For example... Figure 12 As shown, in this embodiment of the application, the initial layout of the target PCB board is simulated on simulation software to obtain temperature simulation results. For example... Figure 13 As shown, this embodiment of the application utilizes a multi-chip heat source arrangement scheme on the target PCB board, performs simulation on the same thermal simulation software, obtains temperature simulation results, and then compares them with the temperature simulation results of the initial arrangement. It can be seen that after utilizing the multi-chip heat source arrangement scheme on the target PCB board, the chip junction temperature on the target PCB board is reduced by 7.13℃, and the average temperature of the entire target PCB board is reduced by 8.24℃. Figure 14 As shown in the embodiments of this application, the comparative cooling of the target chip is illustrated.

[0093] The working principle of the PCB board multi-heat source optimization layout method based on ecological algorithm proposed in this application will be introduced below with reference to a specific embodiment.

[0094] Figure 15 This is a flowchart illustrating the working principle of the PCB board multi-heat source optimization layout method based on ecological algorithm provided in the embodiments of this application.

[0095] Step S1501: Input the number of target chips.

[0096] The number of target chips is expressed as N .

[0097] Step S1502: Input the power of the target chip.

[0098] In this embodiment, the power of the target chip can be verified to be positive. If the power of the target chip is positive, the power of the target chip can be input.

[0099] Step S1503: Input at least one dimension parameter of the target PCB board.

[0100] Step S1504: Generate the allocation and placement location of the target chip, and calculate the heat dissipation area that the target chip needs to be allocated.

[0101] In this embodiment, the area requiring the largest heat dissipation area can be prioritized. S For the first target chip, start the layout from the second target chip and set... k =2, and according to the sequence number k Heat dissipation area allocated as needed S k Place the target chip.

[0102] Step S1505: Check whether the preset geometric constraints are met.

[0103] In this embodiment, the heat dissipation area allocated to the current target chip can be checked to see if it overlaps with the heat dissipation area of ​​the previous target chip and the boundary of the target PCB board. If they do not overlap, the preset geometric constraints are met, and the following settings are made. k= k+ 1. Continue to lay out the subsequent target chips. When they overlap, adjust the heat dissipation area to be allocated to the target chips and re-check whether the preset geometric constraints are met.

[0104] Step S1506: Generate a multi-chip heat source layout scheme on the target PCB board.

[0105] Among them, k=N In this embodiment of the application, the layout of all target chips is completed, thereby generating a multi-chip heat source arrangement scheme on the target PCB board.

[0106] According to the PCB board multi-heat source optimization layout method based on ecological algorithm proposed in this application, the PCB board surface convective heat transfer coefficient distribution can be obtained. Based on the power and number of target chips on the target PCB board, a chip sorting is generated, and then the allocation and placement positions of the target chips are generated. The required heat dissipation area of ​​the target chips is calculated, and whether the preset geometric constraints are met is checked. Thus, a multi-chip heat source layout scheme is generated on the target PCB board according to the allocation and placement positions of the target chips and the corresponding heat dissipation area. On the one hand, the convective heat transfer coefficient distribution can be used to provide a layout basis that conforms to the real thermal environment, fully combining the actual physical mechanism of PCB heat dissipation. On the other hand, the preset ecological algorithm can be used to calculate the heat dissipation area of ​​the target chips, realizing a dynamic balance between the heat dissipation requirements of the target chips and the heat dissipation capacity of the area. This not only meets the actual heat dissipation requirements but also enhances the universality of PCB optimization layout. Therefore, the problem of poor universality and failure to fully combine the actual physical mechanism of PCB heat dissipation in related technologies, which leads to PCB optimization layouts that do not meet actual heat dissipation requirements, is solved.

[0107] Next, referring to the accompanying drawings, we describe the PCB board multi-heat source optimization arrangement device based on ecological algorithms proposed in the embodiments of this application.

[0108] Figure 16 This is a schematic diagram of a block diagram of a PCB board multi-heat source optimization layout device based on an ecological algorithm provided in an embodiment of this application.

[0109] like Figure 16 As shown, the PCB board multi-heat source optimization layout device 160 based on ecological algorithm includes: a determination module 100, an acquisition module 200, a first generation module 300, a detection module 400, and a second generation module 500.

[0110] The determining module 100 is used to obtain at least one dimensional parameter of the target PCB board in order to determine the shape of the target PCB board.

[0111] The acquisition module 200 is used to acquire the convective heat transfer coefficient distribution on the surface of the target PCB board based on the preset convective heat transfer coefficient relationship and shape.

[0112] The first generation module 300 is used to generate a chip sorting based on the power and number of target chips on the target PCB board.

[0113] The detection module 400 is used to generate the allocation and placement position of the target chip based on the distribution of convective heat transfer coefficient and chip sorting, calculate the heat dissipation area to be allocated to the target chip based on the preset ecological algorithm, and detect whether the preset geometric constraints are met.

[0114] The second generation module 500 is used to generate a multi-chip heat source arrangement scheme on the target PCB board based on the allocated placement position of the target chips and the corresponding heat dissipation area when it is detected that the preset geometric constraints are met and the target chips have been placed.

[0115] Optionally, in one embodiment of this application, the acquisition module 200 includes: a first generation unit and a second generation unit.

[0116] The first generation unit is used to obtain the initial convective heat transfer coefficient distribution based on the pre-built slit convective heat transfer model and the empirical formula of the slit convective heat transfer coefficient.

[0117] The second generation unit is used to divide the target PCB board into multiple segments from bottom to top, and correct the initial convection heat transfer coefficient distribution based on the convection heat transfer coefficient function relationship of each segment to obtain the convection heat transfer coefficient distribution.

[0118] Optionally, in one embodiment of this application, the detection module 400 includes: a setting unit, a calculation unit, and a third generation unit.

[0119] The setting unit is used to set the random placement position of the target chip, which is the center of the chip.

[0120] The computing unit is used to calculate the heat dissipation area that needs to be allocated to the target chip using a preset ecological algorithm.

[0121] The third generation unit is used to detect whether the heat dissipation area to be allocated to the target chip overlaps with the heat dissipation area to be allocated to other chips. If they do not overlap, the heat dissipation area is set iteratively; otherwise, the heat dissipation area to be allocated to the target chip is calculated iteratively until the heat dissipation area to be allocated to the target chip is obtained.

[0122] Optionally, in one embodiment of this application, the computing unit includes: a first computing subunit, a second computing subunit, and a generation subunit.

[0123] The first calculation subunit is used to calculate the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB.

[0124] The second calculation subunit is used to calculate the global average heat flux density when the target PCB board reaches ecological balance.

[0125] A sub-unit is generated to read the power of the target chip and obtain the local convective heat transfer coefficient at the center of the chip. The heat dissipation area to be allocated to the target chip is calculated by making the local heat flux density equal to the global average heat flux density.

[0126] Optionally, in one embodiment of this application, the formula for calculating the area of ​​the heat dissipation region is: , , , , , , in, The total power of the target chip, For the power of the target chip, The area of ​​the heat dissipation area that needs to be allocated to the target chip. The average temperature of the target chip and the temperature difference of the gas. The local convective heat transfer coefficient of the target chip is denoted as . The radius corresponding to the area of ​​the heat dissipation region allocated to the target chip. The convective heat transfer coefficient is... Nu For Nusselt numbers, The thermal conductivity of air, air velocity, The kinematic viscosity of air, For the channel height, The characteristic length of the airflow direction. It is the Reynolds number.

[0127] It should be noted that the foregoing explanation of the embodiment of the PCB board multi-heat source optimization layout method based on ecological algorithm also applies to the PCB board multi-heat source optimization layout device based on ecological algorithm in this embodiment, and will not be repeated here.

[0128] According to the PCB board multi-heat source optimization layout device based on ecological algorithm proposed in this application, the PCB board surface convective heat transfer coefficient distribution can be obtained. Based on the power and number of target chips on the target PCB board, a chip sorting is generated, and then the allocation and placement positions of the target chips are generated. The heat dissipation area to be allocated to the target chips is calculated, and whether the preset geometric constraints are met is checked. Thus, a multi-chip heat source layout scheme is generated on the target PCB board according to the allocation and placement positions of the target chips and the corresponding heat dissipation area. On the one hand, the convective heat transfer coefficient distribution can be used to provide a layout basis that conforms to the real thermal environment, fully combining the actual physical mechanism of PCB heat dissipation. On the other hand, the preset ecological algorithm can be used to calculate the heat dissipation area of ​​the target chips, realizing a dynamic balance between the heat dissipation requirements of the target chips and the heat dissipation capacity of the area. This not only meets the actual heat dissipation requirements but also enhances the universality of PCB optimization layout. Therefore, the problem of poor universality and failure to fully combine the actual physical mechanism of PCB heat dissipation in related technologies, which leads to PCB optimization layouts that do not meet actual heat dissipation requirements, is solved.

[0129] Figure 17 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. The electronic device may include: The memory 1701, the processor 1702, and the computer program stored on the memory 1701 and executable on the processor 1702.

[0130] When the processor 1702 executes the program, it implements the PCB board multi-heat source optimization layout method based on ecological algorithm provided in the above embodiments.

[0131] Furthermore, electronic devices also include: Communication interface 1703 is used for communication between memory 1701 and processor 1702.

[0132] Memory 1701 is used to store computer programs that can run on processor 1702.

[0133] The memory 1701 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0134] If the memory 1701, processor 1702, and communication interface 1703 are implemented independently, then the communication interface 1703, memory 1701, and processor 1702 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 17 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0135] Optionally, in a specific implementation, if the memory 1701, processor 1702, and communication interface 1703 are integrated on a single chip, then the memory 1701, processor 1702, and communication interface 1703 can communicate with each other through an internal interface.

[0136] The processor 1702 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0137] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm.

[0138] This application also provides a computer program product, including a computer program that, when executed, implements the above-described method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm.

[0139] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0140] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0141] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0142] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0143] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or more of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0144] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0145] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0146] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for optimizing the arrangement of multiple heat sources on a PCB board based on an ecological algorithm, characterized in that, Includes the following steps: Obtain at least one dimensional parameter of the target PCB board to determine the shape of the target PCB board; Based on the preset convective heat transfer coefficient relationship and the shape, the convective heat transfer coefficient distribution on the surface of the target PCB board is obtained; Based on the power and number of target chips on the target PCB board, a chip sorting is generated; Based on the convective heat transfer coefficient distribution and the chip sorting, the allocation and placement position of the target chip is generated, and the heat dissipation area to be allocated to the target chip is calculated based on the preset ecological algorithm, and it is detected whether the preset geometric constraints are met. If the preset geometric constraints are met and all target chips are placed, a multi-chip heat source arrangement scheme is generated on the target PCB board according to the assigned placement position of the target chips and the corresponding heat dissipation area.

2. The method according to claim 1, characterized in that, The step of obtaining the convective heat transfer coefficient distribution on the surface of the target PCB board includes: Based on the pre-built slit convection heat transfer model, the initial convective heat transfer coefficient distribution is obtained using the empirical formula of the slit convection heat transfer coefficient. The target PCB board is divided into multiple segments from bottom to top, and the initial convective heat transfer coefficient distribution is corrected based on the convective heat transfer coefficient function relationship of each segment to obtain the convective heat transfer coefficient distribution.

3. The method according to claim 1, characterized in that, The calculation of the heat dissipation area to be allocated to the target chip based on a preset ecological algorithm includes: Set a random placement position for the target chip, where the random placement position is the center of the chip; The preset ecological algorithm is used to calculate the heat dissipation area that needs to be allocated to the target chip; It is determined whether the heat dissipation area to be allocated to the target chip overlaps with the heat dissipation area to be allocated to other chips. If they do not overlap, the setting is iteratively set; otherwise, the calculation is iteratively performed until the heat dissipation area to be allocated to the target chip is obtained.

4. The method according to claim 3, characterized in that, The step of calculating the required heat dissipation area for the target chip using the preset ecological algorithm includes: Calculate the total power of the target chip and the total area that can be allocated on the upper surface of the target PCB board; Calculate the global average heat flux density when the target PCB board reaches ecological balance; The power of the target chip is read, and the local convective heat transfer coefficient at the center of the chip is obtained. The heat dissipation area to be allocated to the target chip is calculated by making the local heat flux density equal to the global average heat flux density.

5. The method according to claim 1, characterized in that, The formula for calculating the area of ​​the heat dissipation zone is: ， ， ， ， ， ， in, The total power of the target chip. The power of the target chip. This refers to the area of ​​the heat dissipation area that needs to be allocated to the target chip. The average temperature of the target chip is the temperature difference between the target chip and the gas. The local convective heat transfer coefficient of the target chip is denoted as . The radius corresponding to the area of ​​the heat dissipation region allocated to the target chip. The convective heat transfer coefficient is... Nu For Nusselt numbers, The thermal conductivity of air, air velocity, The kinematic viscosity of air, For the channel height, The characteristic length of the airflow direction. It is the Reynolds number.

6. A PCB board multi-heat source optimization layout device based on ecological algorithms, characterized in that, include: A determining module is used to obtain at least one dimensional parameter of the target PCB board in order to determine the shape of the target PCB board; The acquisition module is used to acquire the convective heat transfer coefficient distribution on the surface of the target PCB board based on a preset convective heat transfer coefficient relationship and the shape. The first generation module is used to generate a chip sorting based on the power and number of target chips on the target PCB board. The detection module is used to generate the allocation and placement position of the target chip based on the convective heat transfer coefficient distribution and the chip sorting, calculate the heat dissipation area to be allocated to the target chip based on a preset ecological algorithm, and detect whether the preset geometric constraints are met. The second generation module is used to generate a multi-chip heat source arrangement scheme on the target PCB board based on the allocated placement position of the target chips and the corresponding heat dissipation area when the preset geometric constraints are met and all target chips are placed.

7. The apparatus according to claim 6, characterized in that, The step of obtaining the convective heat transfer coefficient distribution on the surface of the target PCB board includes: The first generation unit is used to obtain the initial convection heat transfer coefficient distribution based on the pre-built slit convection heat transfer model and the empirical formula of the slit convection heat transfer coefficient. The second generation unit is used to divide the target PCB board into multiple segments from bottom to top, and correct the initial convection heat transfer coefficient distribution based on the convection heat transfer coefficient function relationship of each segment to obtain the convection heat transfer coefficient distribution.

8. An electronic device, characterized in that, include: The memory, the processor, and the computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the PCB board multi-heat source optimization layout method based on the ecological algorithm as described in any one of claims 1-5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the PCB board multi-heat source optimization layout method based on the ecological algorithm as described in any one of claims 1-5.

10. A computer program product, comprising a computer program, characterized in that, The computer program is executed to implement the PCB board multi-heat source optimization layout method based on ecological algorithms as described in any one of claims 1-5.

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