Sampling tube structure and design method thereof
By symmetrically arranging sampling transistors around the main power transistor and utilizing the mutual compensation of sampling ratio changes, the problem of unstable sampling ratio caused by process fluctuations is solved, achieving higher sampling accuracy and stability, and improving the performance and reliability of the power management chip.
Patent Information
- Application Number
- CN202511608532.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-02-10
AI Technical Summary
In existing technologies, fluctuations in semiconductor processes and the orientation of layout result in low sampling ratio accuracy and poor stability of sampling tubes, which affects the performance and reliability of power management chips.
Design a sampling tube structure that symmetrically arranges at least two sampling tubes around the main power tube, so that the sampling ratio change of a single sampling tube caused by process fluctuations can be compensated by the changes of other sampling tubes, thereby maintaining the overall sampling ratio stability of the sampling unit.
It improves sampling accuracy and stability, expands the process window, increases production yield, enhances layout flexibility, and improves the overall performance and reliability of power management chips.
Smart Images
Figure CN121503402A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and particularly to a sampling tube structure and a design method thereof. BACKGROUND
[0002] In the design of semiconductor chips, especially the design of power management chips, the sampling circuit is a key component to realize the functions of accurate control and protection. The sampling circuit usually samples a small part of the current or voltage of the main power tube (for example, a large power MOSFET) to obtain the working state of the main power tube in real time, thereby realizing the functions of over-current protection, current limiting or voltage feedback. The accuracy of the sampling circuit is usually measured by the sampling ratio, which is defined as the ratio of the source current (IS_P) of the main power tube to the source current (IS_S) of the sampling tube, that is: sampling ratio = IS_P / IS_S. Therefore, the accuracy and stability of the sampling circuit directly affect the performance and reliability of the entire power management system.
[0003] In the prior art, the sampling circuit usually adopts one or more sampling tubes, which are designed as transistor units in parallel with the main power tube and much smaller in size than the main power tube on the layout. Please refer to Figure 1 which schematically shows a common single-side sampling structure layout in the prior art. As shown in the figure, a sampling tube is arranged on one side of the main power tube, forming an asymmetric structure. However, this single-side structure has significant defects.
[0004] In the manufacturing process of semiconductors, due to the slight deviation of the process steps such as photolithography and ion implantation, that is, process fluctuation, the physical structure of the device will deviate from the expected position on the layout. For the above-mentioned single-side sampling structure, such deviation will seriously affect the accuracy of the sampling ratio. Taking a lateral diffusion metal oxide semiconductor (LDMOS) transistor as an example, Figure 2 and Figure 3 schematically show the device cross-section and the influence of process fluctuation thereon.
[0005] Please refer to Figure 2 When the process fluctuation causes the P-type implantation region (Ptype) in the device to deviate towards the source (Source), it will change the electrical characteristics of the transistor channel, causing the source current (IS_S) of the sampling tube to decrease. According to the definition of the sampling ratio, in the case that the source current (IS_P) of the main power tube remains unchanged, the decrease of IS_S will cause the sampling ratio to increase, deviating from the designed target value.
[0006] On the contrary, please refer to Figure 3When the process fluctuation causes the P-type injection region to shift towards the drain direction, the source current (IS_S) of the sampling tube will increase. In this case, the sampling ratio will decrease accordingly, and deviate from the design target value.
[0007] The sampling ratio drift caused by the process fluctuation is unpredictable and difficult to control. Figure 4 The curve of "Ratio_OK" represents the sampling ratio under ideal process or as expected by the design, which is stable in the target range (e.g. around 60). The curve of "Ratio_NG" represents the actual measured sampling ratio after the process shift, which has deviated from the target and dropped to an error level (e.g. around 40). This significant deviation can cause the sampling circuit to fail, which in turn can jeopardize the stability and reliability of the entire chip. In addition, the layout direction of the chip in different products can also affect this asymmetric structure, further deteriorating the consistency of sampling.
[0008] Therefore, how to overcome the adverse effects of process fluctuation and layout direction on the sampling accuracy, and design a sampling tube structure with higher stability and reliability, is a technical problem that technicians in the field are eager to solve. SUMMARY
[0009] The purpose of the present application is to solve the technical problem of low sampling ratio accuracy and poor stability of the sampling tube caused by semiconductor process fluctuation and layout direction in the prior art, and to provide a sampling tube structure and design method that can effectively offset the effects of process fluctuation and improve sampling accuracy and reliability.
[0010] To achieve the above-mentioned purpose, the present application provides the following technical solutions:
[0011] The present application provides a sampling tube structure, comprising: a main power tube; and a sampling unit configured to sample the main power tube; wherein the sampling unit comprises at least two sampling tubes symmetrically arranged around the main power tube, and the at least two sampling tubes are arranged such that the sampling ratio change of a single sampling tube caused by semiconductor process fluctuation can be compensated by the sampling ratio change of the other sampling tube in the at least two sampling tubes, to maintain the overall sampling ratio of the sampling unit stable.
[0012] Preferably, the at least two sampling tubes comprise a first sampling tube and a second sampling tube symmetrically arranged on both sides of the main power tube along a first direction.
[0013] Preferably, the first sampling tube and the second sampling tube are configured such that when process fluctuations cause the physical position of the P-type injection region of the first sampling tube to shift, the change in the sampling ratio of the first sampling tube is opposite to the change in the sampling ratio of the second sampling tube, thereby canceling each other out.
[0014] Preferably, the at least two sampling tubes include: a first sampling tube and a second sampling tube symmetrically disposed on both sides of the main power tube along a first direction; and a third sampling tube and a fourth sampling tube symmetrically disposed on both sides of the main power tube along a second direction perpendicular to the first direction.
[0015] Preferably, the main power transistor and at least two sampling transistors are all laterally diffused metal-oxide-semiconductor transistors.
[0016] This application also provides a design method for a sampling tube structure, including the following steps:
[0017] Step 1: Provide the main power transistor;
[0018] Step 2: Arrange at least two sampling transistors symmetrically around the main power transistor to form a sampling unit; wherein, the arrangement of at least two sampling transistors is such that when semiconductor process fluctuations cause a change in the sampling ratio of any one sampling transistor, the sampling ratio of the other sampling transistor will undergo a compensatory change, thereby maintaining the overall sampling ratio stability of the sampling unit.
[0019] Preferably, in step two, at least two sampling tubes include a first sampling tube and a second sampling tube, which are symmetrically arranged on both sides of the main power tube along a first direction.
[0020] Preferably, in step two, when process fluctuations cause the P-type injection region in the first sampling tube to shift towards its source, the P-type injection region in the second sampling tube shifts accordingly towards its drain, thereby causing the sampling ratio change of the first sampling tube to cancel each other out with the sampling ratio change of the second sampling tube.
[0021] Preferably, in step two, at least two sampling tubes include a first sampling tube, a second sampling tube, a third sampling tube, and a fourth sampling tube; the first sampling tube and the second sampling tube are symmetrically arranged on both sides of the main power tube along a first direction; and the third sampling tube and the fourth sampling tube are symmetrically arranged on both sides of the main power tube along a second direction perpendicular to the first direction.
[0022] Preferably, in step two, the arrangement of the first sampling tube, the second sampling tube, the third sampling tube, and the fourth sampling tube ensures that the overall sampling ratio of the sampling unit can remain stable through mutual compensation of the sampling ratio changes when placed in any direction on the chip layout.
[0023] As described above, the sampling tube structure and its design method of the present invention have the following beneficial effects:
[0024] This invention utilizes the structural symmetry of symmetrically arranging at least two sampling transistors around the main power transistor. This allows the sampling ratio deviation of a single sampling transistor caused by process fluctuations (such as P-type implantation region offset) to be compensated and offset by the opposite deviations generated by other symmetrically positioned sampling transistors. This makes the overall sampling ratio highly immune to process fluctuations, thereby improving sampling accuracy and stability. Secondly, because the structure of this application can effectively compensate for process fluctuations, the requirements for process steps such as photolithography alignment accuracy and ion implantation uniformity are relaxed, thus expanding the process window and helping to improve production yield. Thirdly, especially for the four-sided symmetrical embodiment, its structure is insensitive to the chip placement orientation, enhancing layout flexibility and simplifying the design process. Finally, accurate current sampling is crucial for achieving reliable overcurrent protection and current limiting functions. This application, by fundamentally improving sampling accuracy, directly enhances the overall performance and reliability of the entire power management chip and even the electronic system. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of a single-sided sampling tube structure in the prior art;
[0026] Figure 2 This is a cross-sectional schematic diagram illustrating the effect of the P-type injection region shifting towards the source pole on the sampling tube structure in the prior art.
[0027] Figure 3 This is a cross-sectional schematic diagram illustrating the impact of the P-type injection region shifting towards the drain direction on the sampling tube structure in the prior art.
[0028] Figure 4 This is a schematic diagram illustrating the deviation of the sampling ratio from the design target due to process fluctuations in existing technologies.
[0029] Figure 5 This application provides a schematic diagram of a bilateral symmetrical sampling tube structure layout.
[0030] Figure 6 A schematic diagram of a four-sided symmetrical sampling tube structure (horizontal layout) provided for an embodiment of this application;
[0031] Figure 7 A schematic diagram of a quadrilateral symmetrical sampling tube structure (vertical layout) provided for an embodiment of this application;
[0032] Figure 8 This is a flowchart illustrating a sampling tube structure design method provided in an embodiment of this application. Detailed Implementation
[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0034] As described in the background section, traditional single-sided sampling structures, due to their asymmetry, suffer from unpredictable drift in the sampling ratio when faced with semiconductor process fluctuations (such as positional shifts in the P-type injection region), thereby reducing the accuracy and reliability of the sampling circuit. To address this technical problem, this application provides a novel sampling tube structure and its design method.
[0035] This application provides a sampling transistor structure, including: a main power transistor; and a sampling unit configured to sample the main power transistor. The sampling unit includes at least two sampling transistors symmetrically arranged around the main power transistor. The arrangement of the at least two sampling transistors ensures that variations in the sampling ratio of a single sampling transistor caused by semiconductor process variations can be compensated by variations in the sampling ratio of the other sampling transistors in the at least two sampling transistors, thereby maintaining the overall sampling ratio stability of the sampling unit. Through this symmetrical compensation design, this structure can effectively offset device characteristic variations introduced by process variations such as photolithography alignment errors and ion implantation angle deviations, thereby ensuring that the sampling ratio maintains high consistency and accuracy under different process standards and different chip layouts, significantly improving the performance and yield of the power management chip.
[0036] In some embodiments, the main power transistor and at least two sampling transistors are all laterally diffused metal-oxide-semiconductor (LDMOS) transistors. LDMOS transistors are widely used in power management integrated circuits because they can withstand higher voltages and provide larger currents. The following describes a typical LDMOS structure in more detail, which can be used for both the main power transistor and the sampling transistors, differing only in size and the number of transistors connected in parallel.
[0037] In one specific embodiment, the main power transistor and sampling transistor can be fabricated on a semiconductor substrate, such as a P-type doped single-crystal silicon substrate (i.e., PSUB). In the substrate, a deep N-well (DNW in the attached figure) is first formed by ion implantation or epitaxial growth. The deep N-well is used to electrically isolate the high-voltage portion of the device from the P-type substrate and serves as part of the lateral drift region of the LDMOS to withstand high voltage.
[0038] Inside the deep N-well, a P-type body region (i.e., Ptype, which is crucial to the sampling ratio in the attached diagram) is formed through ion implantation. This P-type body region determines the transistor's turn-on threshold voltage, and its edge near the gate forms the device channel. On the source side of the device, a P-well (PW) is typically formed, containing a heavily doped N+ region for source connection and a heavily doped P+ region for body potential connection. The drain of the device is another heavily doped N+ region formed on the side of the deep N-well furthest from the gate.
[0039] A gate structure typically includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer can be thermally grown silicon dioxide (SiO2), or, in more advanced processes, a high-k material such as hafnium oxide (HfO2) to reduce gate leakage current. The gate electrode layer is typically heavily doped polysilicon, which may be covered with a metal silicide, such as titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi), to reduce gate resistance. Dielectric sidewalls, such as those made of silicon nitride (Si3N4) or silicon dioxide, are usually formed on both sides of the gate to enable self-alignment during subsequent source / drain implantation.
[0040] To reduce the resistance of the source, drain, and body contacts, metal silicide layers are formed on the surfaces of the corresponding N+ and P+ regions. Finally, by depositing an interlayer dielectric (ILD) over the device, etching contact holes, and filling them with a conductive material (such as tungsten, W), contact plugs are formed to connect to the source, drain, gate, and body. These contact plugs are then connected to external circuitry using subsequent metal wiring processes (such as aluminum or copper processes). Isolation between devices can be achieved using techniques such as shallow trench isolation (STI) or localized silicon oxide (LOCOS).
[0041] Of course, the structural design concept of this application is not limited to LDMOS, and can also be applied to other types of power transistors, such as vertical double-diffused metal-oxide-semiconductor (VDMOS) transistors, trench-gate MOSFETs, or insulated-gate bipolar transistors (IGBTs) in applications requiring current sampling. These transistors can be manufactured using common semiconductor materials, such as silicon (Si), or, in applications with higher performance requirements, wide-bandgap semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), can be used to achieve higher operating frequencies, lower conduction losses, or superior high-temperature performance.
[0042] In some embodiments, at least two sampling tubes include a first sampling tube and a second sampling tube symmetrically disposed on both sides of the main power tube along a first direction. This structure is a bilaterally symmetrical structure. Please refer to... Figure 5It schematically illustrates a layout of a bilaterally symmetrical structure, in which sampling transistors A and B (corresponding to the first and second sampling transistors, respectively) are symmetrically arranged on both sides of the main power transistor. When process fluctuations are along the first direction (e.g., Figure 5 When a systematic offset is generated in the vertical direction (in the middle), this symmetrical layout is the basis for achieving sampling ratio compensation.
[0043] In some embodiments, the first and second sampling tubes are configured such that when process fluctuations cause a shift in the physical position of the P-type injection region of the first sampling tube, the change in the sampling ratio of the first sampling tube and the change in the sampling ratio of the second sampling tube are in opposite directions, thus canceling each other out. Specifically, please refer to... Figure 5 and combined Figure 2 and Figure 3 The principle illustrated here details this compensation mechanism. Assume a systematic process offset that causes the overall features on the layout to shift upwards. For the upper sampling transistor A, this offset manifests as its P-type body region moving relatively towards its source. This leads to a decrease in the source current (IS_S) of sampling transistor A, and according to the relationship between sampling ratio = power transistor source current / sampling transistor source current, sampling ratio A will increase. Simultaneously, for the lower sampling transistor B, symmetrical to sampling transistor A, the same systematic process offset manifests as its P-type body region moving relatively towards its drain. This leads to an increase in the source current (IS_S) of sampling transistor B, thus decreasing its sampling ratio. Ultimately, when the sampling circuit performs combined sampling on both sampling transistors A and B, the deviation caused by the increased sampling ratio of sampling transistor A and the decreased sampling ratio of sampling transistor B exactly cancel each other out, allowing the overall sampling ratio of the sampling unit to remain highly stable and largely unaffected by process fluctuations in this direction.
[0044] In some embodiments, at least two sampling tubes include: a first sampling tube and a second sampling tube symmetrically disposed on both sides of the main power tube along a first direction; and a third sampling tube and a fourth sampling tube symmetrically disposed on both sides of the main power tube along a second direction perpendicular to the first direction. This structure is a quadrilateral symmetrical structure. Please refer to... Figure 6The diagram schematically illustrates a quadrilateral symmetrical layout. In this structure, four sampling transistors, A, B, C, and D, are symmetrically arranged on the four sides of the main power transistor. Compared to a bilateral symmetrical structure, the quadrilateral symmetrical structure provides a more comprehensive compensation effect. For example, when process offset occurs in the vertical direction, the sampling ratio deviations of sampling transistors A and B cancel each other out; similarly, when process offset occurs in the horizontal direction, the sampling ratio deviations of sampling transistors C and D also cancel each other out. Therefore, regardless of whether the offset of the P-type body region is along the X-axis, Y-axis, or any other diagonal direction, it can always be decomposed into components in the X and Y directions and compensated for by the corresponding symmetrical sampling transistor pairs (A and B, C and D). This design makes the overall sampling ratio highly immune to process fluctuations in any direction, achieving a higher level of sampling accuracy.
[0045] Furthermore, this four-sided symmetrical structure offers another significant advantage: it is insensitive to the placement orientation of the chip layout. Please also refer to... Figure 6 and Figure 7 , Figure 6 It shows a horizontally placed layout, while Figure 7 A vertically positioned layout is shown. Due to the four-sided symmetry of the structure, the relative geometric relationship between the sampling transistor and the main power transistor remains unchanged regardless of whether the chip is rotated 90 degrees, 180 degrees, or 270 degrees, and its compensation mechanism for process fluctuations is exactly the same. This means that designers no longer need to worry about the placement orientation of the sampling circuit affecting its performance when performing top-level chip placement, thus gaining greater design freedom and greatly expanding the process window, ensuring high consistency and stability of product performance in different application scenarios and different batch productions.
[0046] Those skilled in the art will understand that the bilateral and quadrilateral symmetrical structures described above are specific examples of the core ideas of this application. Based on the same principle of symmetry compensation, the number and layout of sampling tubes can be further expanded and complicated. For example, hexagonal, octagonal, or circular symmetrical layouts can be used, with six, eight, or more sampling tubes evenly and symmetrically distributed around the main power transistor. In some high-precision applications, sampling tubes can also be arranged at each corner position to form a corner symmetrical layout, specifically to compensate for process gradient effects that may be more significant at the corners. In addition, hierarchical symmetrical structures can be used, for example, each sampling tube constituting a quadrilateral symmetrical structure is itself composed of smaller bilateral symmetrical sampling tube pairs. These more complex symmetrical layouts can provide higher-order process fluctuation compensation and have stronger stability against more complex process gradients (such as nonlinear or radial gradients), thus playing an important role in applications requiring extremely high precision. Therefore, any sampling tube layout surrounding the main power transistor and utilizing symmetry to offset the effects of process fluctuations should fall within the scope of the protection concept of this application.
[0047] Please refer to Figure 8 This application also provides a design method for a sampling tube structure, including the following steps:
[0048] Step 1: Providing the main power transistor; this step may specifically include: designing and layout the transistor using electronic design automation (EDA) tools based on the chip's electrical performance specifications, such as operating voltage, maximum output current, and on-resistance (RDS(on)). The formation of the main power transistor typically involves a series of semiconductor process steps, such as epitaxial growth, ion implantation, photolithography, etching, thin film deposition, and metallization. The designer will determine its dimensions, doping profile, and the layout of the gate, source, and drain.
[0049] Step 2: Symmetrically arrange at least two sampling transistors around the main power transistor to form a sampling unit. The arrangement of at least two sampling transistors ensures that when semiconductor process fluctuations cause a change in the sampling ratio of one sampling transistor, the sampling ratio of the other sampling transistor will compensate, thus maintaining the overall sampling ratio stability of the sampling unit. This step is the core of this design method. By actively introducing symmetry during the layout design stage, potential process deviations are transformed into self-compensating structural characteristics, thereby shifting from passively accepting the impact of process fluctuations to actively using structural design to counteract their effects.
[0050] In some embodiments, in step two, at least two sampling tubes include a first sampling tube and a second sampling tube, which are symmetrically arranged on both sides of the main power tube along a first direction.
[0051] In some embodiments, in step two, when process fluctuations cause the physical position of the P-type injection region in the first sampling tube to shift, the P-type injection region in the second sampling tube shifts accordingly toward its drain direction, thereby causing the sampling ratio change of the first sampling tube to cancel out the sampling ratio change of the second sampling tube.
[0052] In some embodiments, in step two, at least two sampling tubes include a first sampling tube, a second sampling tube, a third sampling tube, and a fourth sampling tube; the first sampling tube and the second sampling tube are symmetrically arranged on both sides of the main power tube along a first direction; and the third sampling tube and the fourth sampling tube are symmetrically arranged on both sides of the main power tube along a second direction perpendicular to the first direction.
[0053] In some embodiments, the arrangement of the first, second, third, and fourth sampling tubes in step two ensures that the overall sampling ratio of the sampling units remains stable through mutual compensation of sampling ratio variations, regardless of their placement along any direction on the chip layout. The sampling tube structure obtained using this design method significantly reduces the sensitivity of sampling accuracy to process fluctuations and eliminates the uncertainty caused by the layout orientation, ultimately contributing to improved overall chip performance, stability, and production yield.
[0054] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A sampling tube structure, characterized in that, include: Main power transistor; The sampling unit is configured to sample the main power transistor; The sampling unit includes at least two sampling tubes symmetrically arranged around the main power transistor. The arrangement of the at least two sampling tubes is such that the sampling ratio change of a single sampling tube caused by semiconductor process fluctuations can be compensated by the sampling ratio change of other sampling tubes in the at least two sampling tubes, so as to maintain the overall sampling ratio stability of the sampling unit.
2. The sampling tube structure according to claim 1, characterized in that: The at least two sampling tubes include a first sampling tube and a second sampling tube symmetrically arranged on both sides of the main power tube along a first direction.
3. The sampling tube structure according to claim 2, characterized in that: The first sampling tube and the second sampling tube are configured such that when process fluctuations cause the physical position of the P-type injection region of the first sampling tube to shift, the change in the sampling ratio of the first sampling tube and the change in the sampling ratio of the second sampling tube are in opposite directions, thus canceling each other out.
4. The sampling tube structure according to claim 1, characterized in that: The at least two sampling tubes include: a first sampling tube and a second sampling tube symmetrically disposed on both sides of the main power tube along a first direction; and a third sampling tube and a fourth sampling tube symmetrically disposed on both sides of the main power tube along a second direction perpendicular to the first direction.
5. The sampling tube structure according to claim 1, 2, or 4, characterized in that: The main power transistor and the at least two sampling transistors are all laterally diffused metal-oxide-semiconductor transistors.
6. A method for designing a sampling tube structure, characterized in that, include: Step 1: Provide the main power transistor; Step 2: Arrange at least two sampling tubes symmetrically around the main power transistor to form a sampling unit; The at least two sampling tubes are configured such that when semiconductor process fluctuations cause a change in the sampling ratio of any one of the at least two sampling tubes, the sampling ratio of the other sampling tube will undergo a compensatory change, thereby maintaining the overall sampling ratio stability of the sampling unit.
7. The design method of the sampling tube structure according to claim 6, characterized in that: In step two, the at least two sampling tubes include a first sampling tube and a second sampling tube, which are symmetrically arranged on both sides of the main power tube along a first direction.
8. The design method of the sampling tube structure according to claim 7, characterized in that: In step two, when process fluctuations cause the P-type injection region in the first sampling tube to shift towards its source, the P-type injection region in the second sampling tube shifts accordingly towards its drain, thereby causing the sampling ratio change of the first sampling tube and the sampling ratio change of the second sampling tube to cancel each other out.
9. The design method of the sampling tube structure according to claim 6, characterized in that: In step two, the at least two sampling tubes include a first sampling tube, a second sampling tube, a third sampling tube, and a fourth sampling tube; the first sampling tube and the second sampling tube are symmetrically arranged on both sides of the main power tube along a first direction; and the third sampling tube and the fourth sampling tube are symmetrically arranged on both sides of the main power tube along a second direction perpendicular to the first direction.
10. The design method of the sampling tube structure according to claim 9, characterized in that: The arrangement of the first, second, third, and fourth sampling tubes ensures that the overall sampling ratio of the sampling unit remains stable through mutual compensation of sampling ratio changes when it is placed in any direction on the chip layout.