Method and system for arranging signal pins of adjacent functional modules in chip

Abstract

The invention discloses a signal pin layout method and system for adjacent function modules in a chip. The method comprises the following steps: acquiring a physical layout diagram of two function modules in the chip; segmenting the physical layout diagram based on different segmentation modes to form at least two segmentation transformation diagrams; combining different segmentation transformation diagrams belonging to different functional modules to form a plurality of combined diagrams; in each combined diagram, calculating the linear distance between the unit diagrams to which different function modules belong to obtain a plurality of distance values; selecting a line segment corresponding to the minimum distance value in all the calculated distance values in all the combined graphs as a reference line; and determining a pin point for placing a signal pin between the two functional modules based on the area to which the reference line belongs. According to the technical signal pin layout method, efficient and accurate pin position determination is achieved in the signal pin layout of the adjacent function module, meanwhile, the requirement for computing resources is greatly reduced, and the technical signal pin layout method is suitable for a large chip design scene.

Description

Technical Field

[0001] This invention relates to the field of chip fabrication and design technology, and in particular to a method and system for arranging signal pins of adjacent functional modules in a chip. Background Technology

[0002] In the field of chip physical layout design, the placement of signal pins is a critical task that directly impacts chip performance and manufacturing efficiency. Currently, mainstream physical design tools on the market generally employ the global route method for signal pin placement. In this method, the tool calculates the cost of all possible routing paths within the entire chip based solely on the center point of the connected modules as the start and end points, determining the suitable pin placement location on the lowest-cost path. However, when dealing with large-area chips, the sheer size and numerous traces drastically increase the required server cache and computing power, sometimes exceeding the limits of existing servers, making convergence difficult. Therefore, in practical applications, especially in large-chip design, designers often need to manually set constraints to reduce computational complexity.

[0003] Regarding the signal pin layout problem of adjacent functional modules, the global routing method fails to make full use of the proximity of modules and still requires comprehensive calculation of the path throughout the entire chip, which is inefficient and consumes a lot of resources. Summary of the Invention

[0004] The purpose of this invention is to provide a method and system for laying out signal pins of adjacent functional modules in a chip, which can quickly determine the position of signal pins for adjacent functional modules to improve layout efficiency and reduce the demand for computing resources.

[0005] To achieve the above objectives, the present invention provides a method for arranging signal pins of adjacent functional modules in a chip, comprising: Obtain the physical layout diagram of two adjacent and connected functional modules in the chip; For either of the two functional modules, the physical layout diagram is divided based on different segmentation methods to form at least two segmentation transformation diagrams, wherein any sub-region in each segmentation transformation diagram is a regular unit diagram. Any segmentation transformation diagram belonging to one of the functional modules is combined with any segmentation transformation diagram belonging to another functional module to form multiple combined diagrams; In each composite diagram, the straight-line distance between any unit diagram to which one of the functional modules belongs and any unit diagram to which another functional module belongs is calculated to obtain multiple distance values; Select the line segment corresponding to the smallest distance value calculated in all the combined graphs as the reference line; The pin point for placing the signal pin between the two functional modules is determined based on the area to which the reference line belongs.

[0006] Preferably, the method for determining the pin point based on the region to which the reference line belongs includes: In the combined diagram corresponding to the reference line, a reference diagram with the same shape as the unit diagram is constructed based on the reference line; Find the common subgraph of the unit graph to which the two endpoints of the reference graph and the reference line belong; The center of the common subgraph is used as the pin point.

[0007] Preferably, the method for determining the pin point based on the region to which the reference line belongs further includes: The unit diagrams to which the two endpoints of the reference line belong are enlarged proportionally, and then the common sub-diagram of the two enlarged unit diagrams and the reference diagram is obtained.

[0008] Preferably, the side length of the unit graph to which the two endpoints of the reference line belong is increased by 100-500 μm.

[0009] Preferably, when the common area between the reference map and the unit map to which the two endpoints of the reference line belong is empty, the distance value corresponding to the current reference line is discarded, and according to the sorting of the distance values, the largest one is selected from the remaining distance values ​​to obtain a new reference line.

[0010] Preferably, the unit diagram is a rectangular diagram.

[0011] Preferably, the distance between the unit diagrams is determined based on the center point position of each unit diagram.

[0012] The present invention also provides a signal pin layout system, which includes a data server, the data server generating pin points in the chip as signal pins for placing two functional modules based on the signal pin layout method described above.

[0013] The present invention also provides a signal pin layout system, comprising: One or more processors; Memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the signal pin layout method as described above.

[0014] The present invention also provides a computer-readable storage medium comprising a computer program that can be executed by a processor to perform the signal pin layout method described above.

[0015] Compared to existing technologies, the signal pin placement method provided by the above-mentioned technical solution firstly focuses on the local area between adjacent modules by segmenting and combining their physical layout diagrams for two adjacent and connected functional modules in the chip, without having to calculate all possible paths across the entire chip as in traditional global routing methods. This significantly reduces computational complexity and improves the efficiency of signal pin placement. Secondly, by segmenting and transforming the physical layout diagrams of adjacent functional modules and calculating the distances between the unit diagrams, this method can quickly pinpoint the appropriate placement of signal pins, avoiding the server cache and computing power spikes caused by calculating all possibilities in global routing methods. This effect is particularly pronounced in large-area chip designs. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the generation process of a segmentation transformation diagram for one of the functional modules in an embodiment of the present invention.

[0017] Figure 2 This is a flowchart illustrating the generation process of a segmentation transformation graph for another functional module in this embodiment of the invention.

[0018] Figure 3 This is a combination diagram of various different combined states in the embodiments of the present invention.

[0019] Figure 4 for Figure 3 An enlarged view of one of the group diagrams.

[0020] Figure 5 This is a flowchart illustrating the signal pin layout generation process in an embodiment of the present invention. Detailed Implementation

[0021] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0022] This embodiment discloses a method for arranging signal pins of adjacent functional modules in a chip, which is used for the physical arrangement of signal pins between adjacent functional modules in a chip.

[0023] like Figure 5 And in conjunction with reference Figures 1 to 3 The layout method includes the following process: S1: Obtain the physical layout diagram of two adjacent and interconnected functional modules in the chip. Assume these two functional modules are module A and module B, as follows: Figure 1 and Figure 2 Its physical layout Figure 1 It is generally an irregular geometric plane diagram.

[0024] S2: For either of the two functional modules, i.e., for the physical layout diagrams of module A and module B, divide them according to different segmentation methods to form at least two segmentation transformation diagrams. Each sub-region in each segmentation transformation diagram is a regular cell diagram.

[0025] For example, module A is divided horizontally and vertically to form two different segmentation transformation diagrams, A1 and A2. Module B is also divided horizontally and vertically to form two different segmentation transformation diagrams, B1 and B2.

[0026] The unit diagrams in A1 are A11 and A12, and the unit diagrams in A2 are A21 and A22.

[0027] The unit diagrams in B1 are B11 and B12, and the unit diagrams in B2 are B21 and B22.

[0028] S3: Combine any segmentation transformation diagram belonging to module A with any segmentation transformation diagram belonging to module B to form multiple combined diagrams. This combination method can generate various possible layout combinations, providing a basis for subsequently finding the optimal signal pin positions.

[0029] Specifically, such as Figure 3 Combine A1 and B1 to obtain combination diagram P1; combine A1 and B2 to obtain combination diagram P2; combine A2 and B1 to obtain combination diagram P3; combine A2 and B2 to obtain combination diagram P4.

[0030] S4: In each combined graph, calculate the distance between any unit graph to which module A belongs and any unit graph to which module B belongs, and obtain multiple distance values.

[0031] Specifically, in the composite diagram P1, calculate the distances D1 between A11 and B11, D2 between A11 and B12, D3 between A12 and B11, and D4 between A12 and B12.

[0032] Therefore, by calculating the distance values ​​of the four combined graphs, 16 distance values ​​were obtained.

[0033] S5: From all the distance values ​​calculated in all the combination diagrams, select the line segment corresponding to the smallest distance as the reference line. This reference line reflects the closest combination of unit diagrams between module A and module B, representing the area with the shortest possible signal transmission path.

[0034] For example, by comparison, it is confirmed that the distance between A22 and B11 in the composite diagram P3 is the shortest, then the line segment L1 representing this distance is used as the reference line.

[0035] S6: Based on the area to which the reference line belongs, determine the pin locations for placing the signal pins between module A and module B. Specifically, the pin placement positions can be precisely located by further analyzing the geometric center or boundary conditions of the area, thereby completing the signal pin layout design.

[0036] It should be noted that converting an irregular polygonal planar diagram into a regular diagram, such as a set of rectangles, can be achieved using a polygon segmentation algorithm. This algorithm is common knowledge in the field and will not be elaborated upon here.

[0037] Through the steps described above, this embodiment first performs segmentation and combination analysis on two adjacent and connected functional modules within the chip based on their physical layout diagram. It directly focuses on the local area between adjacent modules, eliminating the need to calculate all possible paths across the entire chip as in traditional global routing methods. Therefore, it significantly reduces computational complexity and improves the efficiency of signal pin layout.

[0038] Secondly, by segmenting and transforming the physical layout diagram of adjacent functional modules and calculating the distance between unit diagrams, this method can quickly lock the reasonable placement position of signal pins, avoiding the server cache and computing power surge problems caused by calculating all possibilities in the global routing method. This effect is especially obvious in large-area chip design.

[0039] Furthermore, this method selects the line segment corresponding to the smallest distance value in all combination diagrams as a reference line, and determines the pin point based on the area to which the reference line belongs. This ensures that the signal pins are placed in the optimal position between adjacent modules, thereby reducing the signal transmission path length and improving chip performance.

[0040] On the other hand, the distance between unit diagrams is determined based on the location of the center point of each unit diagram.

[0041] This embodiment uses the geometric center point of each unit graph as a reference point to calculate the distance (such as Euclidean distance) between the center points of corresponding unit graphs in the two modules, thereby determining the shortest path or optimal connection region between them.

[0042] In addition, in the segmentation transformation diagram, each sub-region is a rectangular diagram, that is, an irregular planar diagram is transformed into multiple rectangular diagrams.

[0043] On the other hand, methods for determining pin points based on the region to which the reference line belongs include: In the composite diagram corresponding to the reference line, a reference diagram with the same shape as the unit diagram is constructed based on the reference line; Find the common subgraph of the unit graphs to which the two endpoints of the reference graph and the reference line belong; The center of the common subgraph is used as the pin point.

[0044] Specifically, such as Figure 4 Since line segment L1 is the shortest in the combined graph P3, meaning the distance between A22 and B11 is the smallest among the 16 distance values, a reference graph C0 with a rectangular shape is constructed based on line segment L1. The common subgraph region of C0, A22, and B11 is Q, and the center of Q is taken as the pin point.

[0045] It is worth noting that a common subgraph can be a line or a surface.

[0046] Reference lines can be used as the side lengths, diagonals, or central axes of newly constructed graphs to form reference graphs.

[0047] In addition, to ensure that the reference diagram and the cell diagrams at both ends of the reference line have a common area in most cases, without affecting the layout quality of the pin points, the cell diagrams at both ends of the reference line are scaled up before calculating the intersection of the reference diagram and the cell diagrams at both ends of the reference line. That is, A22 and B11 are scaled up so that they have an intersection and a common intersection with the reference diagram.

[0048] Specifically, the side length of the cell diagram to which the two endpoints of the reference line belong is increased by 100-500 μm.

[0049] On the other hand, when the common area between the unit maps to which the two endpoints of the reference map and the reference line belong is empty, the distance value corresponding to the current reference line is discarded, and the largest of the remaining distance values ​​is selected according to the sorting of the distance values ​​to obtain a new reference line.

[0050] For example, if the current distance value D1 is the smallest, the common area between the reference map constructed based on the reference line formed by D1 and the cell maps to which the two endpoints of the reference line belong is empty. Then, continue searching for the smallest distance value from the remaining 15 distance values, such as D2. Then, construct a new reference map based on the reference line formed by D2, and find the intersection between the new reference map and the cell maps to which the two endpoints of the new reference line belong. If it is still empty, then continue selecting a new reference line in the above manner. If an intersection exists, then the center of the generated common submap is taken as the pin point.

[0051] In summary, this invention discloses a signal pin layout method, such as... Figure 1 value Figure 4 The specific process is as follows: For two adjacent functional modules, first perform a segmentation transformation to obtain a segmentation transformation diagram; Then, for each segmentation transformation diagram of each functional module, the geometric center is calculated.

[0052] Next, the different segmentation transformation diagrams belonging to different functional modules are combined to generate a combined diagram. The geometric centers of the different unit diagrams belonging to different functional modules in the combined diagram are connected, and the length of the geometric center connection is calculated, which is the distance between the different unit diagrams. Then, find the smallest of the multiple distance values, and use the line connecting the geometric centers of the composite graph corresponding to the smallest distance as the reference line; Next, a reference diagram is constructed based on the reference line, and the cell diagrams to which the two endpoints of the reference line belong are enlarged proportionally.

[0053] Then, find the common subgraph of the reference diagram and the unit diagrams to which the two endpoints of the reference line belong.

[0054] Finally, the center of the common subgraph is calculated, and the center of the common subgraph is used as the pin point for arranging signal pins.

[0055] In another preferred embodiment of the present invention, a signal pin layout system is also disclosed, which includes a data server, wherein the data server generates pin points in the chip as signal pins for placing two functional modules based on the signal pin layout method in the above embodiment.

[0056] The present invention also discloses another signal pin layout system, which includes one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the signal pin layout method as described above. The processor may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, used to execute the relevant programs to implement the functions required by the modules in the signal pin layout system of the embodiments of this application, or to execute the signal pin layout method of the method embodiments of this application.

[0057] The present invention also discloses a computer-readable storage medium comprising a computer program executable by a processor to perform the signal pin layout method described above. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available medium can be read-only memory (ROM), random access memory (RAM), or magnetic media, such as floppy disks, hard disks, magnetic tapes, magnetic disks, or optical media, such as digital versatile discs (DVDs), or semiconductor media, such as solid-state disks (SSDs).

[0058] This application also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the aforementioned signal pin layout method.

[0059] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for arranging signal pins of adjacent functional modules in a chip, characterized in that, include: Obtain the physical layout diagram of two adjacent and connected functional modules in the chip; For either of the two functional modules, the physical layout diagram is divided based on different segmentation methods to form at least two segmentation transformation diagrams, wherein any sub-region in each segmentation transformation diagram is a regular unit diagram. Any segmentation transformation diagram belonging to one of the functional modules is combined with any segmentation transformation diagram belonging to another functional module to form multiple combined diagrams; In each composite diagram, the straight-line distance between any unit diagram to which one of the functional modules belongs and any unit diagram to which another functional module belongs is calculated to obtain multiple distance values; Select the line segment corresponding to the smallest distance value calculated in all the combined graphs as the reference line; The pin point for placing the signal pin between the two functional modules is determined based on the area to which the reference line belongs.

2. The signal pin layout method according to claim 1, characterized in that, The method for determining the pin point based on the region to which the reference line belongs includes: In the combined diagram corresponding to the reference line, a reference diagram with the same shape as the unit diagram is constructed based on the reference line; Find the common subgraph of the unit graph to which the two endpoints of the reference graph and the reference line belong; The center of the common subgraph is used as the pin point.

3. The signal pin layout method according to claim 2, characterized in that, The method for determining the pin point based on the region to which the reference line belongs further includes: The unit diagrams to which the two endpoints of the reference line belong are enlarged proportionally, and then the common sub-diagram of the two enlarged unit diagrams and the reference diagram is obtained.

4. The signal pin layout method according to claim 3, characterized in that, Increase the side length of the unit graph to which the two endpoints of the reference line belong by 100-500 μm.

5. The signal pin layout method according to claim 2, characterized in that, When the common area between the reference map and the unit map to which the two endpoints of the reference line belong is empty, the distance value corresponding to the current reference line is discarded, and according to the sorting of the distance values, the largest one is selected from the remaining distance values ​​to obtain a new reference line.

6. The signal pin layout method according to claim 1, characterized in that, The unit diagram is a rectangular diagram.

7. The signal pin layout method according to claim 1, characterized in that, The distance between the unit diagrams is determined based on the center point position of each unit diagram.

8. A signal pin layout system, characterized in that, The system includes a data server, which generates pin points in the chip to serve as signal pins between two functional modules based on the signal pin layout method according to any one of claims 1 to 7.

9. A signal pin layout system, characterized in that, include: One or more processors; Memory; And one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the signal pin layout method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Includes a computer program that can be executed by a processor to perform the signal pin layout method as described in any one of claims 1 to 7.

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