Loop power driver of fire safety system

Abstract

A loop power driver for communication and power supply is described herein. The driver includes a first transistor and a second transistor configured in a push-pull configuration, a high power electronic switch configured in parallel with the first transistor, an operational amplifier (OpAmp) connected to the first transistor and the second transistor, a controller connected to the switch and the OpAmp, where the controller includes a processor capable of accessing a memory storing instructions, the instructions are executable by the processor, which causes the controller to issue a first actuation signal to operate the driver in a first mode that enables a power signal above a predefined voltage level to be supplied via the line, and to issue a second actuation signal to operate the driver in a second mode that enables a power signal above a predefined voltage level to be supplied via the line. The second mode enables power and communication signals to be supplied below a predefined voltage level and at a predefined speed via the line.

Description

Technical Field

[0001] The embodiments described herein relate to the field of loop drives, and more specifically, to high-power and high-speed loop power drives for fire safety systems that can be powered and communicated using a common line. Summary of the Invention

[0002] This document describes a loop power driver for communication and power supply. The loop power driver includes a first and second transistor configured in a push-pull configuration, a high-power electronic switch configured in parallel with the first transistor, and an operational amplifier (OpAmp) including an input terminal connected to a digital-to-analog converter (DAC) and an output terminal connected to the bases associated with the first and second transistors. The driver is adapted to be configured in a power and communication line associated with a field device loop such that the switch and the first transistor remain configured in series with the line, and the second transistor remains configured at the driver output between the line and ground. A controller is connected to the switch and the DAC, wherein the controller includes a processor capable of accessing a memory storing instructions executable by the processor. This causes the controller to issue a first actuation signal to operate the driver in a first mode, which enables the supply of a power signal above a predefined voltage level via the line, and to issue a second actuation signal to operate the driver in a second mode, which enables the supply of power and communication signals below the predefined voltage level via the line at a predefined speed.

[0003] In one or more embodiments, a driver is configured in a line such that the collector of a first transistor remains connected to the line at the input of the driver, the emitters of the first and second transistors remain connected to the line at the output of the driver, a switch remains connected in parallel with the first transistor between the collector and emitter of the first transistor, and the collector of the second transistor remains grounded at the output of the driver.

[0004] In one or more embodiments, the driver includes a shunt bypass circuit configured to be connected in parallel across the second transistor at the output of the driver, between the line and ground, wherein the controller is configured to issue a third actuation signal to activate the shunt bypass circuit, which in turn deactivates the second transistor and further enables voltage or current to flow from the output of the line to or discharge to ground via the shunt bypass circuit.

[0005] In one or more embodiments, the driver includes a first current limiter circuit configured in the line at a driver input, wherein the controller is configured to issue a first control signal that enables the first current limiter circuit to limit the flow of current through the line to a predefined current range based on a mode selected from a first mode and a second mode.

[0006] In one or more embodiments, during a first mode, a predefined current range of the first current limiter is selected based on the voltage level of the power signal to be supplied via the line, at either a first current level or a second current level, wherein the first current level is less than the second current level.

[0007] In one or more embodiments, during the second mode, a predefined current range of the first current limiter is selected at the first current level.

[0008] In one or more embodiments, the driver includes a second current limiter circuit configured between the line and ground, wherein the controller is configured to issue a second control signal that enables the second current limiter circuit to limit the current flow or discharge from the output of the line to ground at one or more predefined current levels.

[0009] In one or more embodiments, during the second mode, one or more predefined current levels are selected based on a predefined speed of the power and communication signals to be transmitted via the line.

[0010] In one or more embodiments, during the second mode, one or more predefined current levels are selected as a first current level for low-speed operation and a second current level for high-speed operation, wherein the second current level is greater than the first current level.

[0011] In one or more embodiments, the input of the line is connected to a configurable power supply, and the output of the line is connected to one or more loads associated with a field device loop, wherein the controller is configured to issue a third control signal to adjust the properties of the power signal supplied by the power supply to the one or more loads via the line during a first mode.

[0012] In one or more embodiments, the line is configured between a configurable power supply, control panel, and one or more loads associated with a field device loop, wherein the controller is configured to issue a fourth control signal to adjust the properties of power and communication signals transmitted via the line between the power supply, control panel, and / or one or more loads during a second mode.

[0013] In one or more embodiments, during the first mode, when the first actuation signal is issued, the controller is configured to activate the switch and further enable the DAC and OpAmp to deactivate the first transistor and the second transistor.

[0014] In one or more embodiments, during the second mode, when the second actuation signal is issued, the controller is configured to deactivate the switch and further actuate the DAC so that OpAmp can activate the first transistor and / or the second transistor.

[0015] In one or more embodiments, during the second mode, the controller is configured to deactivate the switch and further activate the DAC to supply a reference voltage of a predefined voltage level at the input of OpAmp, thereby activating the first transistor and / or the second transistor.

[0016] In one or more embodiments, when the predefined voltage level of the selected reference voltage is higher than the voltage level at the line output, OpAmp is configured to deactivate the second transistor and activate the first transistor, which accordingly sets the predefined voltage level at the line output.

[0017] In one or more embodiments, in order to increase the voltage level at the line output from a first level to a second level, the driver enables the DAC to supply a reference voltage equal to the second level to OpAmp, which deactivates the second transistor and activates the first transistor, and accordingly supplies the second level voltage at the line output.

[0018] In one or more embodiments, when the predefined voltage level of the selected reference voltage is lower than the voltage level at the line output, OpAmp is configured to deactivate the first transistor and activate the second transistor, which accordingly sets the predefined voltage level at the line output.

[0019] In one or more embodiments, in order to reduce the voltage level at the line output from a second level to a first level, the driver enables the DAC to supply a reference voltage equal to the first level to the OpAmp, which deactivates the first transistor and activates the second transistor, and accordingly supplies the first level voltage at the line output.

[0020] In one or more embodiments, the controller is configured to periodically generate a trigger signal at a predefined time interval, monitor the generated trigger signal accordingly, and actuate a first current limiter circuit to disable the operation of the driver when no generated trigger signal is detected within the predefined time interval.

[0021] In one or more embodiments, the high-power power electronic switch is selected from any one of a P-channel metal-oxide-semiconductor (PMOS) transistor, an N-channel metal-oxide-semiconductor (NMOS) transistor, and a relay, wherein the first transistor and the second transistor are bipolar junction transistors (BJTs).

[0022] The foregoing overview is illustrative only and is not intended to be limiting in any way. Other aspects, embodiments, features, and techniques of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in addition to the illustrative aspects, embodiments, features, and techniques described above. Attached Figure Description

[0023] The accompanying drawings are included to provide a further understanding of the subject matter disclosure, and these drawings are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the subject matter disclosure and, together with the description, serve to explain the principles of the subject matter disclosure.

[0024] In the accompanying drawings, similar components and / or features may have the same reference numerals. Additionally, components of the same type may be distinguished by a second reference numeral following the reference numeral, which distinguishes similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0025] Figure 1 An exemplary block diagram of a system according to one or more embodiments disclosed in this subject matter is shown, the system including a loop power driver configured in electrical and communication lines associated with a fire safety system.

[0026] Figure 2 Descriptions of one or more embodiments disclosed in this subject matter are shown. Figure 1 An exemplary representation of the functional module of a loop power driver.

[0027] Figure 3 An exemplary flowchart describing the operation of a driver during a first (high power) mode, according to one or more embodiments disclosed in this subject matter, is shown.

[0028] Figure 4 An exemplary flowchart depicting the operation of the driver during a second (low-power high-speed) mode is shown, according to one or more embodiments disclosed in this subject matter.

[0029] Figure 5 An exemplary flowchart depicting the switching operation of a driver between a first mode and a second mode, according to one or more embodiments disclosed in this subject matter, is shown. Detailed Implementation

[0030] The following is a detailed description of embodiments of the subject matter disclosed, as depicted in the accompanying drawings. These embodiments achieve a level of clarity in conveying the subject matter disclosure. However, the amount of detail provided is not intended to limit the contemplation of the embodiments; rather, it is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the subject matter disclosure as defined by the appended claims.

[0031] Various terms are used herein. Where a term used in the claims is not within the scope defined below, it shall be given the broadest definition that has been given to a person skilled in the art.

[0032] In this specification, reference may be made to the spatial relationships between the various components and the spatial orientation of various aspects of the components, as the device is depicted in the accompanying drawings. However, as those skilled in the art will recognize upon fully reading this disclosure, the components of the invention described herein can be positioned in any desired orientation. Therefore, the use of terms such as “above,” “below,” “upper,” “lower,” “first,” “second,” or other similar terms to describe the spatial relationships between the various components or to describe the spatial orientation of various aspects of such components should be understood as describing the relative relationships between the components or the spatial orientation of various aspects of such components, which can be oriented in any desired direction.

[0033] Fire safety systems are used to ensure the safety of buildings and their occupants. These systems typically rely on an extensive wiring infrastructure to connect various sensors, alarm devices, and control panels. Traditional fire safety installations may involve the use of two separate pairs of wires: one pair for communication signals and the other for power.

[0034] While this traditional cabling approach is effective, it can present several challenges that may increase the overall complexity and cost of the installation. Using two pairs of wires may require longer cables, which can be both time-consuming and labor-intensive to install. Furthermore, the increased amount of cabling material can raise the total cost. The physical complexity of managing multiple wire pairs can also complicate maintenance and troubleshooting tasks, potentially leading to increased downtime and higher service costs.

[0035] Alternative approaches may involve using common lines (single-pair wires) for both power transmission and communication. This approach simplifies cabling infrastructure, reduces material and labor costs, and makes the system easier to install and maintain. However, implementing such a solution can present significant technical challenges.

[0036] A major challenge may lie in the need for a single pair of wires to handle the high power levels required by fire protection system components while simultaneously supporting high-speed data communication. High-power transmission can lead to issues such as increased circuit losses, higher power consumption, and thermal management problems. Another important consideration is minimizing electromagnetic interference (EMI), which can disrupt communication signals or cause malfunctions in fire protection system components. Achieving robust EMC performance may be crucial to ensuring the reliability and safety of the system.

[0037] Therefore, an innovative solution is needed that enables the use of common lines (single-wire pairs) for both power and communication in fire protection facilities. This invention provides a loop power driver that overcomes the aforementioned limitations and drawbacks associated with high power handling, fast data transmission, circuit losses, power dissipation, and EMI issues, thereby achieving efficient, economical, and reliable operation of fire safety systems.

[0038] refer to Figure 1 and Figure 2 A loop power driver 200 (also referred to herein as a loop card driver or driver or SLC driver) for enabling communication and power supply functions within a fire safety system 100 is disclosed. The driver 200 may include a first transistor 202 (also referred herein as through transistor 202) and a second transistor 204 (also referred herein as shunt transistor 204) arranged in a push-pull configuration. Furthermore, a high-power electronic switch 206 may be configured to be connected in parallel with the first transistor 202. The driver 200 may further include an operational amplifier (OpAmp) 208 having an input terminal connected to a digital-to-analog converter (DAC) and an output terminal connected to the base associated with the first transistor 202 and the second transistor 204, wherein the first transistor 202, the second transistor 204, and the OpAmp 208 may form a gain amplifier (Class AB) with a gain of ~13.5, which can operate based on DAC commands.

[0039] In one or more embodiments, the high-power power electronic switch 206 may be a P-channel metal-oxide-semiconductor (PMOS) transistor; however, the switch 206 may also be selected from any of an N-channel metal-oxide-semiconductor (NMOS) transistor and a relay, but is not limited thereto. Furthermore, in one or more embodiments, the first transistor 202 and the second transistor 204 may be bipolar junction transistors (BJTs), but are not limited thereto.

[0040] The driver 200 is adapted to be installed into or integrated into a power and communication line (also referred to herein as a source line or line) associated with the fire safety system 100 or a field device loop of the fire safety system 100. In this configuration, the switch 206 and the first transistor 202 may remain in series with the line, while the second transistor 204 may be located between the line and ground at the output (also referred to as the load end) of the driver 200. As shown, the driver 200 may be configured in the line such that the collector of the first transistor 202 remains connected to the line at the input (also referred to as the source end) of the driver 200, the emitters of the first transistor 202 and the second transistor 204 remain connected to the line at the output of the driver 200, the switch remains in parallel with the first transistor 202 between the collector and emitter, and the collector of the second transistor 204 remains grounded via a current-limiting circuit 214 at the output of the driver 200.

[0041] Furthermore, driver 200 may include controller 106 that can be connected to switch 206 and DAC. In one or more embodiments, controller 106 may be connected to the gate associated with PMOS switch 206, wherein the source of PMOS switch 206 is connected to the input of the line or power supply 102, and the drain of PMOS switch 206 is connected to the output of the line. Controller 106 may include a processor capable of accessing a memory storing executable instructions. These instructions may enable controller 106 to issue specific actuation signals to control the operation of driver 200 in different modes.

[0042] It should be understood that the various ranges and levels of current and voltage mentioned herein are merely exemplary and are based on the ratings of power supply 102, connected load 104, and components associated with loop driver 200. These can be changed to higher or lower values ​​without any limitation, and all such implementations are within the scope of this subject matter.

[0043] In the first mode (also known as the high-power mode), the controller 106 can issue a first actuation signal to operate the driver 200, allowing a power signal supplied via the line at a voltage level higher than a predefined voltage level (the high-power level ranges from 24V to 40V, but is not limited to this). This mode facilitates the transmission of high-power signals from the power supply 102 to loads 104, such as sensors, alarms, indicators, and control panels associated with the fire safety system 100.

[0044] In the second mode (also known as the low-power, high-speed mode), the controller 106 can issue a second actuation signal to operate the driver 200, enabling the supply of power and communication signals via the line at a predefined voltage level (low-power level ranges from 24V to 0V, but is not limited to this) and at a predefined speed of up to 8kbps. This mode is optimized for efficient communication and low power consumption, making it ideal for applications that require both power supply and data transmission capabilities.

[0045] In one or more embodiments, the driver 200 may further include a shunt bypass circuit 210 configured to be connected in parallel across the second transistor 204 at the output of the driver 200, between the line and ground. In one or more embodiments, the controller 106 may be configured to issue a third actuation signal to activate the shunt bypass circuit 210, which may correspondingly deactivate the second (shunt) transistor 204 and further enable voltage or current to flow or discharge from the output of the line to ground via the shunt bypass circuit 210. This may facilitate the discharge operation of the load or reduce the voltage level at the line output to zero.

[0046] During the first mode, upon issuing the first actuation signal, the controller 106 can be configured to activate the PMOS switch 206 and further actuate the DAC, which can further command or force the OpAmp 208 into a tri-state (high impedance state), thereby deactivating the first transistor 202 and the second transistor 204. In such an embodiment, the controller 106 can generate a forward bias across the PMOS switch 206, causing the PMOS switch 206 to operate in the linear or saturation region. Furthermore, the OpAmp 208 can generate a reverse bias across the first transistor 202 and the second transistor 204 to keep them deactivated. Additionally, in some cases during the first mode, the first transistor 202 may remain or be kept active while the second transistor 204 is deactivated. However, when the PMOS switch 206 operates in the linear or saturation region, the PMOS switch 206 may be turned on, which may create a short-circuit path across the first transistor 202, allowing power to flow through the line via the PMOS switch 206, while essentially no power flows through the first transistor 202.

[0047] Furthermore, during the second mode, controller 106 can be configured to deactivate switch 206 and further actuate the DAC to supply a reference voltage of a predefined voltage level to OpAmp 208, thereby activating the first transistor 202 and / or the second transistor 204. This predetermined voltage level (DAC command) may correspond to a voltage level maintained or supplied at the output of the line. In such an embodiment, controller 106 may generate a reverse bias across PMOS switch 206, causing PMOS switch 206 to operate as an open circuit. Additionally, OpAmp 208 may generate a forward bias across the first transistor 202 and / or the second transistor 204 to keep them activated / on and operate in the linear or saturation region.

[0048] In one or more embodiments, the driver 200 may further include a first current limiter circuit 212 configured in the line at the input of the driver 200. The controller 106 may be configured to issue a first control signal that enables the first current limiter circuit 212 to limit the flow of current through the line to a predefined current range (~0.5A to ~4A) based on the operating mode of the driver 200 (a first mode and a second mode). During a first (high power) mode, the predefined current range of the first current limiter circuit 212 may be selected between a first current level (~0.5A) and a second current level (~4A) based on the voltage level (low or high) of the power signal to be supplied via the line. Furthermore, during a second (low power) mode, the predefined current range of the first current limiter circuit 212 may be selected at the first current level (~0.5A).

[0049] In one or more embodiments, the driver 200 may further include a second current limiter circuit 214 configured at the output of the line between the line and ground. The controller 106 may be configured to issue a second control signal that enables the second current limiter circuit 214 to limit the flow or discharge of current from the output of the line to ground at one or more predefined current levels. During the second mode, the predefined current level may be selected based on the speed of the power and communication signals to be supplied via the line. For example, the predefined current level may be selected as a first current level (~0.5A) for low-speed transmission of power and communication signals via the line. Alternatively, the predefined current level may be selected as a second current level (~4A) for high-speed transmission of power and communication signals via the line, wherein the second current level may be greater than the first current level.

[0050] In one or more embodiments, the power supply 102 at the line input may be a configurable or programmable power supply 102. The controller 106 may be configured to issue a third control signal to adjust the properties of the power signal supplied to the load 104 via the line by the programmable power supply 102 during the first (high power) mode.

[0051] In one or more embodiments, controller 106 may be a microcontroller that can be connected to the gate of PMOS switch 206, OpAmp 208, first current limiter circuit 212, second current limiter circuit 214 and programmable power supply 102 using general-purpose input / output pins or ports associated with microcontroller 106.

[0052] Furthermore, in one or more embodiments, the line may be configured between the programmable power supply 102, the control panel, and the load 104 associated with the field device loop. In such an embodiment, the controller 106 may be configured to issue a fourth control signal to adjust the properties of the power and communication signals transmitted via the line between the power supply 102, the control panel, and / or the load 104 during the second mode.

[0053] In one or more embodiments, during the second (low power high speed) mode, the controller 106 may be configured to deactivate the switch and further actuate the DAC to supply a reference voltage of a predefined voltage level at the input of OpAmp 208, thereby activating the first transistor 202 and / or the second transistor 204.

[0054] In one or more embodiments, during the second (low-power high-speed) mode, when a predefined voltage level higher than the real-time voltage level at the line output is selected, OpAmp 208 can deactivate the second transistor 204 and activate the first transistor 202, which can accordingly set the predefined voltage level at the line output. Therefore, during the second (low-power high-speed) mode, in order to increase the voltage level at the line output from the first level to the second level, driver 200 can enable the DAC to supply a reference voltage equal to the second level to OpAmp 208, which can deactivate the second transistor 204 and activate the first transistor 202, and accordingly supply the second level voltage at the line output. For example, if the output voltage level is 6V, and the DAC applies a 12V reference voltage at the input of OpAmp 208, then the first transistor 202 can be activated, and the second transistor 204 can be deactivated to change the output voltage level from 6V to 12V.

[0055] Furthermore, in one or more embodiments, during the second (low-power high-speed) mode, when a predefined voltage level lower than the real-time voltage level at the line output is selected, OpAmp 208 can deactivate the first transistor 202 and activate the second transistor 204, which can accordingly set the predefined voltage level at the line output. Therefore, during the second (low-power high-speed) mode, in order to reduce the voltage level at the line output from the second level to the first level, driver 200 can enable the DAC to supply a reference voltage equal to the first level to OpAmp 208, which can deactivate the first transistor 202 and activate the second transistor 204, and accordingly supply a voltage of the first level at the line output.

[0056] In one or more embodiments, in a non-limiting example, during a high-to-low voltage transition (e.g., a 20V to 0V transition), controller 106 may actuate the DAC to command the reference voltage to change from 1.48V to 0V (but not limited to this), such that the base of the first (through) transistor 202 remains at a lower potential compared to its emitter, thus becoming reverse-biased or open-circuited. However, the base of the second (shunt) transistor 204 remains at a lower potential compared to its emitter to activate and operate it in the linear or saturation region (forward-biased), which can turn on the second transistor 204, allowing it to bring the output voltage to the commanded lower potential; this is referred to as discharging. During the discharge condition, a discharge current can flow through the second transistor 204. Furthermore, the shunt circuit (second current limiter circuit) 214 may limit the current flow to 0.5A or 4A depending on the configuration. Therefore, the second current limiter circuit 214 can prevent EMI problems when a high current flows to ground. For example, if the output voltage level is 18V and a 12V reference voltage is applied to the input of the DAC at the OpAmp 208, the second transistor 204 can be activated and the first transistor 202 can be deactivated to change the output voltage level from 18V to 12V.

[0057] In one or more embodiments, taking into account the voltage drop across the first transistor 202 and other components associated with the driver 200, the controller 106 may command the programmable power supply 102 to provide a higher power or voltage level than is intended to be supplied at the output of the line. For example, in a non-limiting example, to have an output voltage of 20V at the output of the line, the controller 106 may operate the power supply 102 at 24V, taking into account the 4V voltage drop at the first transistor 202.

[0058] In one or more embodiments, power supply 102 may be programmable, allowing for variable voltage configurations based on output or load requirements, with additional increments to accommodate path losses. Initially, power supply 102 may provide default power at either a low-power (~24V) or high-power (~40V) level. However, during mode transitions, specific procedures can be implemented to ensure seamless adjustment or switching. For example, when transitioning from a low-power mode to a high-power mode, controller 106 may well ramp up the voltage of power supply 102 before the transition, ensuring a smooth transition from the low-power (~24V) level to the required higher-power (~40V) level. Conversely, when transitioning from a high-power mode to a low-power mode, controller 106 may well buckle the voltage of power supply 102 before the transition, ensuring a smooth transition from the higher-power (~40V) level to the low-power (~24V) level. This proactive buckling can minimize power consumption in the lines and drivers 200, compensate for the higher losses encountered in the low-power, high-speed mode, and thus optimize the efficiency of the overall system 100.

[0059] In one or more embodiments, driver 200 may be configured with resettable I / O firmware control to ensure fail-safe operation. This allows controller 106 to generate periodic trigger signals for normal operation at predetermined intervals (such as, but not limited to, 8 milliseconds, which may be adjustable) and monitor the generated trigger signals. If no trigger is generated within 8 milliseconds, controller 106 may actuate first current limiter circuit 212 to prevent current from flowing through the line, thereby preventing the output from operating in a safe state (off state).

[0060] refer to Figure 3 During the first (high-power mode), at block 302, power supply 102 can be configured to ~40V, and at blocks 304 and 306, the current levels of the first current limiter circuit 212 and the second current limiter circuit 214 can be set to ~4A, respectively. Furthermore, at block 308, PMOS switch 206 can be activated, simultaneously actuating the DAC, which can further command or force OpAmp 208 into a tri-state (high-impedance state), thereby deactivating the first transistor 202 and the second transistor 204. Therefore, a forward bias can be generated on PMOS switch 206, causing it to operate and be turned on in the linear or saturation region, and OpAmp 208 can generate a reverse bias on the first transistor 202 and the second transistor 204 to keep them deactivated or turned off. As a result, the PMOS switch 206 can operate in the linear or saturation region and create a short-circuit path on the first transistor, thereby allowing power to flow through the line via the PMOS switch 206 while essentially no power flows through the first transistor 202, and supplying ~40V at the output of the line.

[0061] refer to Figure 4 During the second (low-power high-speed mode), at block 402, power supply 102 can be configured to ~24V, and at block 404, the current level of the first current limiter circuit 212 can be set to ~0.5A. Furthermore, at block 406, PMOS 206 can be disabled. Additionally, the current level of the second current limiter circuit 214 can be selected to be ~0.5A for low-speed transmission of power and communication signals via the line, or selected to be ~4A for high-speed transmission of power and communication signals via the line. Furthermore, at block 408, controller 106 can command OpAmp 208 to activate the first transistor 202 and / or the second transistor 204, enabling low-power high-speed supply of power and communication signals via the line.

[0062] refer to Figure 5 When transitioning from the first (low-power high-speed) mode to the second (high-power) mode, at block 502, controller 106 can effectively ramp up the voltage of power supply 102 before the transition, and at block 504, change the first current limiter circuit 212 from 0.5A to 4A, thereby ensuring a smooth transition from the low-power (~24V) level to the required higher power (~40V) level. Conversely, when transitioning from the second (low-power high-speed) mode to the first (high-power) mode, at block 506, controller 106 can effectively ramp down the voltage of power supply 102 before the transition, and at block 508, change the first current limiter circuit 212 from 4A to 0.5A, thereby ensuring a smooth transition from the higher power (~40V) level to the low power (~24V) level. This proactive reduction minimizes power consumption in the lines and drivers, compensates for the higher losses encountered in the low-power high-speed mode, and thus optimizes overall system efficiency.

[0063] Therefore, this invention provides an improved solution in the form of a loop power driver that enables the use of a common line (single pair of wires) for power and communication in fire protection facilities. This loop driver overcomes technical hurdles related to high power handling, rapid switching, circuit losses, power consumption, and EMC issues, ultimately leading to a more streamlined, economical, and reliable fire safety system.

[0064] Although the invention has been explained with reference to the fact that the operation of the loop driver 200 is controlled by a controller 106 such as a microcontroller, it is understood that the operation of the loop driver 200 can also be controlled by various computing systems such as computers, servers, web servers, cloud-based environments, field-programmable gate arrays (FPGAs), etc. The controller 200 includes one or more processors operatively coupled to memory. The processor can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, logic circuits, and / or any device that manipulates data based on operating instructions. Among other capabilities, the processor is configured to fetch and execute computer-readable instructions stored in memory. Memory can store one or more computer-readable instructions or routines that can be fetched and executed to produce data units or to serve or share data units via a network. Memory can include any non-transitory storage device, including volatile memory such as RAM, or non-volatile memory such as EPROM, flash memory, etc. The controller 106, loop driver 200, power supply 102, load 104, and power line may include interfaces, which may include various interfaces for connecting the respective components and facilitating communication between them as well as the exchange of power and communication signals.

[0065] Although this disclosure has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes can be made and equivalents can be substituted for elements therein without departing from the scope of this disclosure as defined by the appended claims. Modifications can be made to employ particular situations or materials for the teachings of this disclosure without departing from its scope. Therefore, this disclosure is intended to be limited to the specific embodiments disclosed, but rather to include all embodiments falling within the scope of this disclosure as defined by the appended claims.

[0066] In interpreting the specification, all terms shall be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprising” and “including” shall be interpreted as referring to an element, component, or step in a non-exclusive manner, indicating that the mentioned element, component, or step may be present, utilized, or combined with other elements, components, or steps not expressly mentioned. When a claim in the specification refers to at least one thing selected from the group consisting of A, B, C, ... and N, the text shall be interpreted as requiring only one element from that group, rather than A plus N, or B plus N, etc.

Claims

1. A loop power driver for communication and power supply, the loop power driver comprising: The first and second transistors are configured in a push-pull configuration; A high-power electronic switch configured in parallel with the first transistor; An operational amplifier (OpAmp) includes an input terminal connected to a digital-to-analog converter (DAC) and an output terminal connected to the base of a first transistor and a second transistor. The driver is adapted to be configured in a power and communication line associated with a field device loop, such that the switch and the first transistor are configured to be connected in series with the line, and the second transistor is configured at the output of the driver between the line and ground. and A controller connected to the switch and the DAC, wherein the controller includes a processor capable of accessing a memory containing stored instructions that can be executed by the processor, enabling the controller to: A first actuation signal is issued to operate the driver in a first mode, which enables the supply of a power signal above a predefined voltage level via a line; and A second actuation signal is issued to operate the driver in a second mode, which enables the supply of power and communication signals via the line at a predefined voltage level and at a predefined speed.

2. The loop power driver of claim 1, wherein the driver is configured in the line such that the collector of the first transistor remains connected to the line at the input of the driver, the emitters of the first transistor and the second transistor remain connected to the line at the output of the driver, the switch remains connected in parallel with the first transistor between the collector and the emitter of the first transistor, and the collector of the second transistor remains grounded at the output of the driver.

3. The loop power driver of claim 1, wherein the driver includes a shunt bypass circuit configured to be connected in parallel across the second transistor at the output of the driver, between the line and ground, wherein the controller is configured to issue a third actuation signal to activate the shunt bypass circuit, which correspondingly deactivates the second transistor and further enables voltage or current to flow from the output of the line through the shunt bypass circuit to or discharge to ground.

4. The loop power driver of claim 1, wherein the driver includes a first current limiter circuit configured in the line at the input of the driver, wherein the controller is configured to issue a first control signal that enables the first current limiter circuit to limit the flow of current through the line to a predefined current range based on a mode selected from a first mode and a second mode.

5. The loop power driver of claim 4, wherein during a first mode, a predefined current range of the first current limiter is selected based on a first current level or a second current level, based on the voltage level of the power signal to be supplied via the line, wherein the first current level is less than the second current level.

6. The loop power driver of claim 5, wherein during the second mode, a predefined current range of the first current limiter is selected at the first current level.

7. The loop power driver of claim 1, wherein the driver includes a second current limiter circuit configured between the line and ground, wherein, The controller is configured to issue a second control signal that enables the second current limiter circuit to limit the current flow or discharge from the output of the line to ground at one or more predefined current levels.

8. The loop power driver of claim 7, wherein during the second mode, one or more predefined current levels are selected based on a predefined speed of the power and communication signals to be transmitted via the line.

9. The loop power driver of claim 8, wherein during the second mode, the one or more predefined current levels are selected as follows: The first current level for low-speed operation; and A second current level is used for high-speed operation, wherein the second current level is greater than the first current level.

10. The loop power driver of claim 1, wherein the input of the line is connected to a configurable power supply and the output of the line is connected to one or more loads associated with the field device loop, wherein the controller is configured to issue a third control signal to adjust the properties of the power signal supplied by the power supply to the one or more loads via the line during the first mode.

11. The loop power driver of claim 1, wherein the line is configured between a configurable power supply, a control panel, and one or more loads associated with the field device loop, wherein the controller is configured to issue a fourth control signal to adjust the properties of power and communication signals transmitted via the line between the power supply, the control panel, and / or the one or more loads during the second mode.

12. The loop power driver of claim 1, wherein during the first mode, when the first actuation signal is issued, the controller is configured to activate the switch, and further enables the DAC and OpAmp to deactivate the first transistor and the second transistor.

13. The loop power driver of claim 1, wherein during the second mode, when the second actuation signal is issued, the controller is configured to deactivate the switch and further actuate the DAC to enable OpAmp to activate the first transistor and / or the second transistor.

14. The loop power driver of claim 13, wherein during the second mode, the controller is configured to deactivate the switch and further actuate the DAC to supply a reference voltage of a predefined voltage level at the input of OpAmp, thereby activating the first transistor and / or the second transistor.

15. The loop power driver of claim 14, wherein when a predefined voltage level of the selected reference voltage is higher than the voltage level at the line output, OpAmp is configured to deactivate the second transistor and activate the first transistor, which accordingly sets the predefined voltage level at the line output.

16. The loop power driver of claim 15, wherein in order to increase the voltage level at the line output from a first level to a second level, the driver enables the DAC to supply a reference voltage equal to the second level to OpAmp, OpAm deactivates the second transistor and activates the first transistor, and accordingly supplies the second level voltage at the line output.

17. The loop power driver of claim 14, wherein when a predefined voltage level of the selected reference voltage is lower than the voltage level at the line output, OpAmp is configured to deactivate the first transistor and activate the second transistor, which accordingly sets the predefined voltage level at the line output.

18. The loop power driver of claim 17, wherein in order to reduce the voltage level at the line output from the second level to the first level, the driver enables the DAC to supply a reference voltage equal to the first level to OpAmp, OpAmp deactivates the first transistor and activates the second transistor, and accordingly supplies the first level voltage at the line output.

19. The loop power driver of claim 4, wherein the controller is configured to: Periodically generate trigger signals at predefined time intervals and monitor the generated trigger signals; and If no trigger signal is detected within the predefined time interval, the first current limiter circuit is actuated to disable the operation of the driver.

20. The loop power driver of claim 1, wherein the high-power power electronic switch is selected from any one of a P-channel metal-oxide-semiconductor (PMOS) transistor, an N-channel metal-oxide-semiconductor (NMOS) transistor, and a relay, and wherein the first transistor and the second transistor are bipolar junction transistors (BJTs).

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