Digital logic control circuit and charging chip

Abstract

The invention provides a digital logic control circuit and a charging chip. The circuit comprises a state conversion circuit, a power conversion circuit and an analog circuit, the power conversion circuit comprises a first transistor, a voltage conversion circuit and a second transistor. The state conversion circuit outputs the working state of the charging chip according to the access condition of the power supply, and the power conversion circuit controls the power conversion circuit to start according to a forward charging path or a reverse discharging path according to the working state; the forward charging path comprises a first-stage power circuit, a second-stage power circuit and a third-stage power circuit which are sequentially connected in series, and the reverse discharging path comprises a fourth-stage power circuit, a fifth-stage power circuit, a sixth-stage power circuit and an analog circuit which are sequentially connected in series. And the ending mark generation module is used for generating a corresponding ending mark after the previous-stage power circuit is started, so that the next-stage power circuit is started based on the ending mark. And the complexity of the control logic can be reduced through hierarchical step-by-step control.

Description

Technical Field

[0001] This application relates to the field of power management chip technology, and in particular to a digital logic control circuit and a charging chip. Background Technology

[0002] See Figure 1 , Figure 1 A schematic diagram of the internal structure of a portable electronic device is provided for related technologies, such as... Figure 1 As shown, in portable electronic devices (e.g., smartphones, smartwatches, etc.), charging chips are used to step down the voltage on the adapter side (approximately 5V~20V) to the voltage range required by the battery and system load (approximately 2.2V~4.5V), thereby enabling battery charging and discharging management. In addition to providing current to the battery, the charging chip's built-in DC-DC converter can also directly provide current to the system load.

[0003] In addition to managing battery charging and discharging and supplying power to the system load, charging chips also need multiple overvoltage protections, overcurrent protections, and short-circuit protections to prevent abnormal damage to various circuits in the charging process. Therefore, charging chips require multi-level logic control and protection mechanisms to ensure the safe operation of the charging system.

[0004] In related technologies, the logic control of charging chips is usually implemented using a main state machine and some delay and combinational logic circuits. The control logic has fewer layers. As the scale of the charging system increases and the relationship between various circuits becomes more complex, it is not convenient to control each circuit individually, which increases the difficulty of implementation. In addition, the charging chip includes multiple protection mechanisms, which require separate control of the circuit state on the corresponding path of the protection mechanism, making the control logic more complex. Summary of the Invention

[0005] This application provides a digital logic control circuit and a charging chip to reduce the complexity of the control logic.

[0006] In a first aspect, this application provides a digital logic control circuit applied in a charging chip, the digital logic control circuit comprising: a state transition circuit, a power conversion circuit, and an analog circuit; the power conversion circuit comprising: a first transistor, a voltage conversion circuit, and a second transistor; The state transition circuit is used to output the working state of the charging chip according to the access status of the power supply, wherein the power supply includes: bus voltage power supply and battery power supply; the bus voltage power supply indicates that the charging chip is powered by the bus voltage, and the battery power supply type indicates that the charging chip is powered by the battery. The power conversion circuit is used to control itself to start according to either a forward charging path or a reverse discharging path based on the operating state; wherein, the forward charging path includes: a first-stage power circuit, a second-stage power circuit, and a third-stage power circuit connected in series, the first-stage power circuit including the first transistor, the second-stage power circuit including the voltage conversion circuit, and the third-stage power circuit including the second transistor; the reverse discharging path includes: a fourth-stage power circuit, a fifth-stage power circuit, and a sixth-stage power circuit connected in series, the fourth-stage power circuit including the second transistor, the fifth-stage power circuit including the voltage conversion circuit, and the sixth-stage power circuit including the first transistor; The analog circuit is used to generate a corresponding end flag after the power circuit of the previous stage has been started, so that the power circuit of the next stage can be started based on the end flag.

[0007] In one possible design, the state transition circuit includes: a main state machine; the main state machine includes a first idle state, a forward charging state, and a battery-only state; The main state machine is used to output the target working state of the charging chip according to the access status of the power supply. The target working state is any one of the first idle state, the forward charging state, and the battery-only state. The forward charging state controls the power conversion circuit to start according to the forward charging path, the battery-only state controls the power conversion circuit to start according to the reverse discharge path, and the first idle state indicates that the main state machine is in an idle state.

[0008] In one possible design, the state transition circuit further includes: a VBUS detection sub-state machine; The VBUS detection sub-state machine is used to detect whether the bus voltage is higher than the bus voltage threshold when the bus voltage is connected. If yes, it outputs a VBUS detection pass state so that the main state machine outputs the forward charging state; if no, it outputs a VBUS detection idle state so that the VBUS detection sub-state machine is in an idle state.

[0009] In one possible design, the state transition circuit further includes: a forward sub-state machine; the forward sub-state machine includes: a forward idle state and a forward buck state; The forward sub-state machine is used to control the first transistor to start when the target working state is the forward charging state, and to output a forward buck state after the first transistor has started, so that the voltage conversion circuit switches to buck mode; it is also used to output a forward idle state when the main state machine outputs the battery-only state or the first transistor is off, so that the forward sub-state machine is in an idle state.

[0010] In one possible design, the state transition circuit further includes a BUCKCHG sub-state machine for controlling the on or off of the second transistor on the forward charging path, so that the bus voltage charges the battery through the forward charging path; It is also used to control the charging stage of the battery according to the current voltage of the battery, and adjust the corresponding charging current based on the charging stage; wherein the charging stage includes: trickle charging stage, pre-charging stage, constant current charging stage and constant voltage charging stage.

[0011] In one possible design, the state transition circuit further includes a BATONLY sub-state machine; the BATONLY sub-state machine includes a battery idle state, a battery powered state, and a battery reverse powered state. The BATONLY sub-state machine is used to determine whether the voltage conversion circuit has switched to boost mode when the target operating state is the battery-only state. If yes, it outputs the battery reverse power supply state; if no, it outputs the battery power supply state. The battery power supply state indicates that the system load is powered by the battery, the battery reverse power supply state indicates that the system load and the bus voltage terminal are powered by the battery, and the battery idle state indicates that the BATONLY sub-state machine is in an idle state.

[0012] In one possible design, the state transition circuit further includes: a BOOST sub-state machine; The BOOST sub-state machine is used to control the startup of the first transistor, the voltage conversion circuit, and the second transistor on the reverse discharge path when the BATONLY sub-state machine outputs the reverse battery power supply state; it is also used to perform a hiccup mode restart when the voltage conversion circuit fails in boost mode when the voltage conversion circuit is in boost mode.

[0013] In one possible design, the target state machine is also used to receive a protection signal and, in response to the protection signal, control itself to return to an idle state; wherein the target state machine is any one of the VBUS detection sub-state machine, the forward sub-state machine, the BUCKCHG sub-state machine, the BATONLY sub-state machine, and the BOOST sub-state machine.

[0014] In one possible design, the power conversion circuit further includes a power switch and a voltage regulator circuit, the second stage power circuit includes the power switch and the voltage regulator circuit, or the fourth stage power circuit includes the voltage regulator circuit and the sixth stage power circuit includes the power switch; The power switch is used to control itself to turn on after the intermediate power supply and the first software enable signal are connected. The voltage regulator circuit is used to control itself to turn on after being connected to an intermediate power source or battery voltage and receiving a second software enable signal.

[0015] In a second aspect, this application provides a charging chip, including: the digital logic control circuit as described in the first aspect.

[0016] The beneficial effects of the embodiments of this application are as follows: In this embodiment, the components in the power conversion circuit are layered according to their turn-on sequence, i.e., each power circuit is a different level. Based on the enable sequence of each power circuit, a state transition circuit controls each power circuit to start up according to either a forward charging path or a reverse discharging path. After the previous power circuit starts up, an analog circuit generates a corresponding end flag, which enables the next power circuit to start up based on the end flag. In other words, the end flag of the previous power circuit is used as the enable signal for the next power circuit, thus realizing the logic control for starting each power circuit. Layered control reduces the complexity of the control logic. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0018] Figure 1 A schematic diagram of the internal structure of a portable electronic device provided for related technologies; Figure 2 A schematic diagram of the circuit structure of a charging chip provided for related technologies; Figure 3 A logic control diagram of a charging chip provided for related technologies; Figure 4 A schematic diagram illustrating the changes in battery voltage and charging current during the charging process, provided for related technologies; Figure 5 A schematic diagram of the structure of a digital logic control circuit provided in an embodiment of this application; Figure 6 A schematic diagram of the hierarchical structure of different paths in a power conversion circuit provided in an embodiment of this application; Figure 7 This is a functional schematic diagram of a charging chip provided in an embodiment of this application; Figure 8 A schematic diagram of the working process of a master state machine provided in an embodiment of this application; Figure 9 This is a schematic diagram illustrating the working process of a VBUS detection sub-state machine provided in an embodiment of this application. Figure 10 A schematic diagram illustrating the working process of a forward sub-state machine provided in this application embodiment; Figure 11 A schematic diagram illustrating the working process of a BUCKCHG sub-state machine provided in this application embodiment; Figure 12 A schematic diagram illustrating the working process of a BATONLY sub-state machine provided in this application embodiment; Figure 13 This is a schematic diagram illustrating the working process of a BOOST sub-state machine provided in an embodiment of this application. Detailed Implementation

[0019] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0022] See Figure 2 , Figure 2 A circuit structure diagram of a charging chip provided for related technologies, such as... Figure 2 As shown, the charging chip acts as a DC-DC converter through a conversion circuit and is connected between the battery and the system load, i.e., between the system load terminal SYS and the battery terminal BAT, through a power transistor M4, to regulate the amount of energy exchange between the battery and the system load.

[0023] See Figure 2 The bus port BUS is connected to the power supply voltage Vbus output by the adapter. The reverse blocking transistor M1 is used to block the reverse current path from the battery or system load to the bus port BUS. Without the reverse blocking transistor M1, the voltage Vsys on the system load will be directly connected to the bus port BUS through the inductor L and then through the body diode of the upper transistor M2. When the adapter is not plugged in, leakage will occur at the bus port BUS.

[0024] The conversion circuit includes upper transistor M2, lower transistor M3, and inductor L. The intermediate node SW between upper transistor M2 and lower transistor M3 is connected to inductor L, and then connected to the system load to achieve voltage reduction from the bus port BUS to the system load SYS. Power transistor M4 can operate in the linear region to regulate the charging current to the battery; it can also operate in the nonlinear region as a switch to control the current flowing from the battery to the system load.

[0025] See Figure 2 The charging chip's workflow is as follows: First, after the adapter is connected, the power supply voltage Vbus output by the adapter is detected to determine whether the power supply voltage Vbus has reached the set threshold voltage Vbus_min. After the detection is successful, the reverse blocking transistor M1 is turned on.

[0026] Next, the voltage Vpmid at the second voltage terminal PMID is detected to determine if it meets the condition for enabling the subsequent circuit. Once Vpmid meets the condition, or after waiting for a preset time (e.g., 10ms) for the reverse blocking transistor M1 to activate, the conversion circuit is activated. The conversion circuit directly generates the voltage Vsys for the subsequent system load, allowing the system load to operate normally without requiring battery power.

[0027] Finally, after the system load is powered on, the main control circuit will send instructions to the charging chip through the communication bus protocol, such as the IIC (Inter-Integrated Circuit) communication bus protocol. When the sent instruction is to start charging, the power transistor M4 will gradually switch from the off state to the on state to gradually charge the battery.

[0028] In related technologies, the workflow control of a charging chip is typically implemented using a master state machine and some delay and combinational logic circuits. For its logic control, please refer to [link to relevant documentation]. Figure 3 , Figure 3 A logic control diagram of a charging chip provided for related technologies, such as... Figure 3 As shown, after the power supply voltage Vbus is powered on, the power supply voltage Vbus is detected. Upon successful detection, the main state machine generates a state signal indicating the on / off state to control the corresponding circuit's operating state. For example, this could involve turning on the reverse blocking transistor M1, turning on the conversion circuit, or turning on the power transistor M4. Different operating states result in different operating modes. For instance, different degrees of activation of the power transistor M4 will result in different charging currents and different DAC (Digital-to-Analog Converter) code values. Similarly, when the conversion circuit is activated, it can be either a boost converter or a buck converter.

[0029] Taking the power transistor M4 as an example, when the charging path is enabled, the current flows from the power supply voltage Vbus through the power transistor M4 to the battery. Only during the charging state, based on the battery's current voltage, the charging state can be divided into four different charging sub-states: Trickle Charge, Pre Charge, Constant-Current (CC), and Constant-Voltage (CV). These charging sub-states are controlled by the upper-level main state machine and determine the specific charging strategies of the DC-DC converter circuit and the power transistor M4.

[0030] See Figure 4 , Figure 4A schematic diagram illustrating the changes in battery voltage and charging current during the charging process is provided for related technologies, such as... Figure 4 As shown, when the battery is completely depleted (i.e., a dead battery), its internal resistance is very high. Charging with a large current would cause the battery to overheat severely. Therefore, a trickle charge is first used to raise the battery voltage to 2.25V using a small current. Then, a pre-charge is used to quickly raise the battery voltage to 3V using a small current. After the battery voltage reaches 3V, a constant current charge with a larger current is used to raise the battery voltage quickly. When the battery is close to being fully charged, a constant voltage charge is used, and the charging current gradually decreases to ensure that the battery is fully charged.

[0031] Because the control of the charging chip's workflow in related technologies is usually implemented by a main state machine and some delay and combinational logic circuits, the control logic has fewer layers when the main state machine is directly controlled. As the scale of the charging system increases and the relationship between various circuits becomes more complex, it is not convenient to control each circuit individually, which increases the difficulty of implementation. In addition, the charging chip includes multiple protection mechanisms, which require separate control of the circuit state on the corresponding path of the protection mechanism, making the control logic more complex.

[0032] To reduce the complexity of the control logic, this application proposes a digital logic control circuit, see [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of the structure of a digital logic control circuit provided in an embodiment of this application, such as... Figure 5 As shown, the digital logic control circuit 1000 may include: a state transition circuit 100, a power conversion circuit 200, and an analog circuit 300; the power conversion circuit 200 includes: a first transistor QB, a voltage conversion circuit DC-DC, and a second transistor BATFET.

[0033] The state transition circuit 100 is used to output the working state of the charging chip according to the access status of the power supply. The power supply includes: bus voltage power supply and battery power supply. Bus voltage power supply indicates that the charging chip is powered by the bus voltage VBUS, and battery power supply indicates that the charging chip is powered by the battery VBAT.

[0034] The power conversion circuit 200 is used to control itself to start according to the forward charging path or the reverse discharging path according to the working state. The forward charging path includes a first-stage power circuit, a second-stage power circuit, and a third-stage power circuit connected in series. The first-stage power circuit includes a first transistor, the second-stage power circuit includes a voltage conversion circuit, and the third-stage power circuit includes a second transistor. The reverse discharging path includes a fourth-stage power circuit, a fifth-stage power circuit, and a sixth-stage power circuit connected in series. The fourth-stage power circuit includes a second transistor, the fifth-stage power circuit includes a voltage conversion circuit, and the sixth-stage power circuit includes a first transistor.

[0035] Analog circuit 300 is used to generate a corresponding end flag after the previous stage power circuit has started up, so that the next stage power circuit can start up based on the end flag.

[0036] The digital logic control circuit in this application is applied to a charging chip, which can be a wired charging chip. A wired charging chip is a special-purpose integrated circuit installed inside a mobile electronic device. It controls the charging of the battery according to the characteristics of the battery, realizes the energy priority allocation between the system load and the battery, and is responsible for coordinating the conversion, transmission and protection of electrical energy during the charging process. It realizes the charging of the device through a physical connection (e.g., a Type-C interface). Its main tasks include regulating the magnitude of voltage and current, implementing multiple protections, and supporting communication protocols to optimize charging efficiency and safety.

[0037] Based on the circuit structure and operation of the charging chip described above, the power conversion circuit 200 in this application includes: a first transistor QB, a voltage conversion circuit DC-CDC, and a second transistor BATFET. The first transistor QB is used to block reverse current on the path from battery VBAT to bus voltage VBUS. The voltage conversion circuit DC-CDC is used to perform level conversion on bus voltage VBUS to power subsequent circuits. The second transistor BATFET can be used as a switch connecting the battery to other circuits, or as a current regulating device on the path from bus voltage VBUS to battery VBAT.

[0038] For the charging chip, the power supply includes two methods: bus voltage (VBUS) power supply and battery VBAT power supply. VBUS power supply provides charging from the adapter side. Depending on the power supply, the DC-DC converter operates in different modes. When powered by VBUS, the DC-DC converter operates in buck mode. Additionally, the DC-DC converter can also function as a charge pump, which is more efficient than the buck mode. When powered by battery VBAT, the DC-DC converter operates in boost mode.

[0039] This application implements logic control of the power conversion circuit 200 through a state transition circuit 100. To reduce the complexity of the control logic and simplify the control process, the components included in the power conversion circuit 200 need to be layered to facilitate layer-by-layer logic control by the state transition circuit 100. Based on the order in which the components in the power conversion circuit 200 are turned on, each component is layered, and the components included in each layer are defined. Enable signals are passed layer by layer from the top to the bottom to control the turning on of each layer's components, ultimately achieving control over the enable of all circuits. At the same time, corresponding sub-mode control is performed for each layer.

[0040] Depending on the power supply, charging chips can be broadly categorized into forward charging paths and reverse discharging paths. For details, see [link to documentation]. Figure 6 , Figure 6 This application provides a schematic diagram of the hierarchical structure of different paths in a power conversion circuit, as shown in the embodiments below. Figure 6 As shown, the forward charging path includes: a first-stage power circuit 201, a second-stage power circuit 202, and a third-stage power circuit 203 connected in series. The first-stage power circuit 201 includes a first transistor QB, the second-stage power circuit 202 includes a voltage conversion circuit DC-DC, and the third-stage power circuit 203 includes a second transistor BATFET. The reverse discharging path includes: a fourth-stage power circuit 204, a fifth-stage power circuit 205, and a sixth-stage power circuit 206 connected in series. The fourth-stage power circuit 204 includes a second transistor BATFET, the fifth-stage power circuit 205 includes a voltage conversion circuit DC-DC, and the sixth-stage power circuit 206 includes a first transistor QB.

[0041] Based on the turn-on sequence of each component in the power conversion circuit 200, the components are divided into layers, namely, power circuits at each level. Based on the enable sequence of each power circuit, the analog circuit generates a corresponding end flag after the previous power circuit is started, so that the next power circuit starts based on the end flag. That is, the end flag of the previous power circuit is used as the enable signal of the next power circuit, thereby realizing the start-up or turn-off sequence of each power circuit.

[0042] In one example, taking the forward charging path as an example, when the bus voltage VBUS is connected, the bus voltage VBUS is detected. After the detection is passed, the first-stage power circuit 201 (i.e., the first transistor QB) is allowed to be turned on. After the first-stage power circuit 201 (i.e., the first transistor QB) is turned on, the analog circuit generates a soft-start end flag QB_SS_DONE for the first transistor QB. After generating the end flag QB_SS_DONE, an enable signal corresponding to the second-stage power circuit 202 (i.e., the voltage conversion circuit DCCDC) is generated. After the second-stage power circuit 202 (i.e., the voltage conversion circuit DCCDC) is turned on, the analog circuit will return an end flag DCCDC_SS_DONE, and then allow the third-stage power circuit 203 (i.e., the second transistor BATFET) to be turned on for charging enable control.

[0043] See Figure 6 In the forward charging path, the bus voltage VBUS is used as the power source. After passing through the first-stage power circuit 201, the bus voltage VBUS becomes the intermediate power source VPMID. The intermediate power source VPMID is used as the power source for the second-stage power circuit 202. After passing through the second-stage power circuit 202, the intermediate power source VPMID becomes the system load power source VSYS. After passing through the third-stage power circuit 203, the system load power source VSYS becomes the battery voltage VBAT.

[0044] See Figure 6 In the reverse charging path, the battery voltage VBAT is used as the power source. After passing through the fourth power circuit 204, the battery VBAT becomes the system load power source VSYS. After passing through the fifth power circuit 205, the system load power source VSYS becomes the intermediate power source VPMID. After passing through the sixth power circuit 206, the intermediate power source VPMID becomes the bus voltage VBUS.

[0045] In this embodiment, the components in the power conversion circuit are layered according to their turn-on sequence, i.e., each power circuit is a different level. Based on the enable sequence of each power circuit, a state transition circuit controls each power circuit to start up according to either a forward charging path or a reverse discharging path. After the previous power circuit starts up, an analog circuit generates a corresponding end flag, which enables the next power circuit to start up based on the end flag. In other words, the end flag of the previous power circuit is used as the enable signal for the next power circuit, thus realizing the logic control for starting each power circuit. Layered control reduces the complexity of the control logic.

[0046] In one possible embodiment, the state transition circuit 100 includes a master state machine; the master state machine includes a first idle state, a forward charging state, and a battery-only state.

[0047] The main state machine is used to output the target operating state of the charging chip according to the power supply access status. The target operating state is any one of the following: first idle state, forward charging state, and battery-only state.

[0048] Among them, the forward charging state control power conversion circuit is started according to the forward charging path, the battery-only state control power conversion circuit is started according to the reverse discharge path, and the first idle state indicates that the main state machine is in an idle state.

[0049] This application uses a state transition circuit 100 to implement logical control of each level of power circuits in the power conversion circuit 200, as well as sub-state control for each level of power circuits, ultimately achieving logical control of all charging functions of the charging chip. The state transition circuit includes a main state machine and multiple sub-state machines to implement logical control of each level of power circuits. Each state machine performs hierarchical control according to the sequential dependency relationship of each level of power circuit in the corresponding path.

[0050] The master state machine is used to implement the top-level logic control of the charging chip. Depending on the power supply connection status, that is, the presence of the bus voltage VBUS and the battery VBAT, it outputs the working status of the charging chip to control the power conversion circuit to start according to the forward charging path or the reverse discharging path. In addition, when the bus voltage VBUS is connected, the bus voltage VBUS needs to be detected. After the detection is passed, it is allowed to start according to the forward charging path.

[0051] For details, see Figure 7 , Figure 7 This is a functional schematic diagram of a charging chip provided in an embodiment of this application, such as... Figure 7 As shown, the main state machine includes a first idle state (IDEL), a forward charging state (FORWARD), and a battery-only state (BATONLY). When neither the bus voltage (VBUS) nor the battery voltage (VBAT) is connected (i.e., neither the bus voltage (VBUS) nor the battery voltage (VBAT) is in place), the main state machine is in the first idle state (IDEL).

[0052] See Figure 7When the bus voltage VBUS is connected (i.e., VBUS is in place), the bus voltage VBUS needs to be detected, i.e., VBUS_QUAL. After the detection passes, the main state machine enters the forward charging state FORWARD, controlling the power conversion circuit to start according to the forward charging path (i.e., forward charging enable). At this time, the voltage conversion circuit DC-DC is in buck mode, i.e., BUCK mode. When only the battery VBAT is in place and VBUS is not in place, the main state machine enters the battery-only state BATONLY, controlling the power conversion circuit to start according to the reverse charging path (i.e., reverse discharging enable). At this time, the voltage conversion circuit DC-DC is in boost mode, i.e., BOOST mode. It can be understood that, depending on the power supply connection, the main state machine can switch between the forward charging state FORWARD and the battery-only state BATONLY, and correspondingly, the power conversion circuit can also switch between forward charging and reverse charging.

[0053] See Figure 8 , Figure 8 This application provides a schematic diagram of the operation process of a master state machine, as shown in the embodiment of the present application. Figure 8 As shown, the working process of the main state machine is as follows: When the charging chip is initially in the PRO state (i.e., Power-On Reset), after the charging chip is powered on, the WARMUP process (i.e., the process of loading the preset configuration into the memory) will be performed first. After the loading is completed, the main state machine will output the target working state of the charging chip according to the presence of the bus voltage VBUS and the battery VBAT. The target working state is any one of the first idle state IDEL, the forward charging state FORWARD, and the battery-only state BATONLY.

[0054] It's important to understand that the main state machine determines the target operating state of the charging chip, while the functional control for each target operating state is determined by the sub-state machines. At any given time, the target operating state of the charging chip can only be one of the following: the first idle state (IDEL), the forward charging state (FORWARD), or the battery-only state (BATONLY).

[0055] In one possible embodiment, see Figure 9 , Figure 9 This is a schematic diagram illustrating the working process of a VBUS detection sub-state machine provided in an embodiment of this application, as shown below. Figure 9 As shown, the state transition circuit 100 also includes a VBUS detection sub-state machine.

[0056] The VBUS detection sub-state machine is used to detect whether the bus voltage is higher than the bus voltage threshold when the bus voltage is connected. If yes, it outputs a VBUS detection pass status so that the main state machine outputs a forward charging status; if no, it outputs a VBUS detection idle status so that the VBUS detection sub-state machine is in an idle state.

[0057] When the bus voltage VBUS is connected (i.e., VBUS is in place), the bus voltage VBUS needs to be detected, i.e., VBUS_QUAL detection. The VBUS detection sub-state machine is used to detect the adapter's capability based on the VBUS_PRESENT status indication. After the VBUS_QUAL detection passes, a global flag VBUS_GOOD is generated.

[0058] For details, see Figure 9 The working process of the VBUS detection sub-state machine is as follows: When the bus voltage VBUS is not connected, the VBUS detection sub-state machine outputs the second idle state VBUS_QUAL_IDEL; when the bus voltage VBUS is connected (i.e., the current VBUS state VBUS_PRESENT=1, which is high level) and the bus voltage VBUS has no overvoltage protection or undervoltage protection, the VBUS detection sub-state machine enters the VBUS detection waiting state VBUS_QUAL_WAIT, in which it needs to wait for 200ms and does not perform any operation.

[0059] See also Figure 9After 200ms of timing, the VBUS detection sub-state machine enters the VBUS detection pull-down state VBUS_QUAL_PD. In this state, the bus voltage VBUS is pulled down for 30ms. This process can be performed by connecting a current source. In this state, the bus voltage threshold VBUS_MIN is not detected (i.e., the bus voltage threshold VBUS_MIN detection is disabled). After 30ms of timing, the VBUS detection sub-state machine enters the VBUS detection authentication state VBUS_QUAL_CHECK. In this state, the bus voltage VBUS is pulled down for 1ms. During this period, the bus voltage threshold VBUS_MIN and the current VBUS state VBUS_PRESENT also need to be detected. If the bus voltage threshold VBUS_MIN=1 is not detected within 1ms of the pull-down operation, it means that the bus voltage threshold VBUS is higher than the bus voltage threshold VBUS_MIN during the 1ms pull-down operation. Then, the VBUS detection is considered to be successful, and the VBUS detection sub-state machine outputs the VBUS detection successful state VBUS_QUAL_GOOD. If the bus voltage threshold VBUS_MIN=1 is detected within 1ms of the pull-down operation, it means that the bus voltage threshold VBUS is lower than the bus voltage threshold during the 1ms pull-down operation. Therefore, it is considered that VBUS has not passed the detection, and the VBUS detection sub-state machine outputs the second idle state VBUS_QUAL_IDEL.

[0060] See also Figure 9 After a successful VBUS detection, the global flag VBUS_GOOD is retained. During this period, the current source for pulling down the bus voltage VBUS is turned off, and VBUS_GOOD is kept at 1. If the bus voltage threshold VBUS_MIN=1 is detected during this period, the VBUS detection sub-state machine returns to the second idle state VBUS_QUAL_IDEL. It should be noted that if the bus voltage VBUS is disconnected while the VBUS detection sub-state machine is in any of the following states: VBUS_QUAL_WAIT (waiting state), VBUS_QUAL_PD (pull-down state), VBUS_QUAL_CHECK (identification state), or VBUS_QUAL_GOOD (passed state), the VBUS detection sub-state machine will return to the second idle state VBUS_QUAL_IDEL, making the VBUS detection sub-state machine idle and waiting for re-detection.

[0061] In this embodiment of the application, when the bus voltage VBUS is connected (i.e., VBUS is in place), the bus voltage VBUS is detected through the VBUS detection sub-state machine. After two pull-down operations on the bus voltage VBUS, if the bus voltage threshold VBUS is still higher than the bus voltage threshold VBUS_MIN, it is considered that the load capacity of the adapter meets the requirements, the VBUS detection is determined to be passed, and the VBUS detection pass status VBUS_QUAL_GOOD is output, thus completing the detection of the bus voltage VBUS.

[0062] In one possible embodiment, see Figure 10 , Figure 10 This application provides a schematic diagram illustrating the working process of a forward sub-state machine, as shown in the embodiments below. Figure 10 As shown, the state transition circuit 100 further includes a forward sub-state machine; the forward sub-state machine includes a forward idle state FORWARD_IDEL and a forward buck state FORWARD_BUCK.

[0063] The forward sub-state machine is used to control the first transistor QB to start when the target operating state is the forward charging state, and to output the forward buck state FORWARD_BUCK after the first transistor QB starts up, so that the voltage conversion circuit DCDC switches to the buck mode BUCK; it is also used to output the forward idle state FORWARD_IDEL when the main state machine outputs the battery-only state BATONLY or the first transistor QB is off, so that the forward sub-state machine is in an idle state.

[0064] For details, see Figure 10 The forward sub-state machine operates as follows: When the bus voltage VBUS is connected (i.e., VBUS is in place) and the target operating state output by the main state machine is the forward charging state (i.e., forward charging), the forward sub-state machine will start. After starting, it will control the first transistor QB to start, and after the first transistor QB starts, it will output the forward buck state FORWARD_BUCK to switch the voltage conversion circuit DCDC to buck mode BUCK, enabling forward charging. When the main state machine outputs the battery-only state BATONLY (i.e., reverse discharge) or the first transistor QB is off, the forward sub-state machine does not need to control the operation on the reverse discharge path and outputs the forward idle state FORWARD_IDEL to put the forward sub-state machine in an idle state.

[0065] In this embodiment, the forward sub-state machine is only used to control the state control of the first transistor QB in the forward charging path of the voltage conversion circuit, and to switch itself to buck mode BUCK to realize the buck function of the voltage conversion circuit in the forward charging path.

[0066] In one possible embodiment, see Figure 11 , Figure 11 A schematic diagram illustrating the working process of a BUCKCHG sub-state machine provided in this application embodiment is shown below. Figure 11 As shown, the state transition circuit 100 further includes a BUCKCHG sub-state machine, used to control the conduction or cutoff of the second transistor BATFET on the forward charging path, so that the bus voltage VBUS charges the battery through the forward charging path.

[0067] It is also used to control the charging stage of the battery according to the current voltage of the battery, and adjust the corresponding charging current based on the charging stage; wherein the charging stage includes: trickle charging stage BUCKCHG_TRICKLE, pre-charge stage BUCKCHG_PRE, constant current charging stage BUCKCHG_FAST and constant voltage charging stage BUCKCHG_TAPER.

[0068] In the forward charging path, the current flows from the bus voltage VBUS through the second transistor BATFET to the battery. The second transistor BATFET acts as a current regulating device in the path from the bus voltage VBUS to the battery VBAT. By adjusting the second transistor BATFET from the off state to the fully on state, the magnitude of the current from the bus voltage VBUS to the battery in the charging path can be controlled.

[0069] In this application, the BUCKCHG sub-state machine controls the on / off state of the second transistor BATFET on the forward charging path, allowing the bus voltage VBUS to charge the battery through the forward charging path. Additionally, based on threshold voltages set for each charging stage, such as the battery short-circuit threshold voltage VBAT_SHORT or the battery pre-charge threshold voltage VBAT_VPRECHG, the current battery voltage is compared with the set threshold voltages to generate a corresponding charging stage identifier, thereby controlling the battery's charging stage. Furthermore, the lower-level control adjusts the corresponding charging current based on the charging stage.

[0070] When the target operating state output by the main state machine is the forward charging state (i.e., forward charging), and the forward sub-state machine controls the voltage conversion circuit to switch to buck mode BUCK to realize the buck function of the voltage conversion circuit in the forward charging path, it indicates that charging has been enabled. It is necessary to control the state of the second transistor BATFET in the forward charging path to realize control for different charging stages.

[0071] For details, see Figure 11The BUCKCHG sub-state machine operates as follows: In the charging idle state BUCKCHG__IDEL, the BUCKCHG sub-state machine compares the current battery voltage with the battery short-circuit threshold voltage VBAT_SHORT, the battery pre-charge threshold voltage VBAT_VPRECHG, and the battery fast-charge threshold voltage VBAT_VCHG, generating corresponding charging stage identifiers and thus entering different charging stages. For example, when the battery is completely depleted, to reduce battery heat generation, the BUCKCHG sub-state machine controls the battery to first enter the trickle charging stage BUCKCHG_TRICKLE, using a smaller current for charging; when the battery VBAT voltage is greater than the battery short-circuit threshold voltage VBAT_SHORT, it enters the pre-charge stage BUCKCHG_PRE; when the battery VBAT voltage is greater than the battery pre-charge threshold voltage VBAT_VPRECHG, it enters the constant current charging stage BUCKCHG_FAST; and when the battery VBAT voltage is greater than the battery fast-charge threshold voltage VBAT_VCHG, it enters the constant voltage charging stage BUCKCHG_TAPER. Understandably, by comparing the battery's current voltage with the set threshold voltage, the BUCKCHG substate machine can control the battery to jump from the charging idle state BUCKCHG__IDEL to any one of the following charging stages: trickle charging stage BUCKCHG_TRICKLE, pre-charge stage BUCKCHG_PRE, constant current charging stage BUCKCHG_FAST, and constant voltage charging stage BUCKCHG_TAPER.

[0072] After the constant voltage charging phase BUCKCHG_TAPER ends, the battery charging current IBAT will fall below a set current threshold ITERM, which serves as a signal for charging termination. When the battery charging current IBAT falls below the current threshold ITERM, the BUCKCHG sub-state machine controls the battery to enter the charging end state BUCKCHG_EOC (End Of Charge, EOC), where the charging function is disabled. Charging continues until the load draws current from the battery, causing the battery voltage VBAT to fall below the battery fast-charging threshold voltage VBAT_VCHG again, at which point the battery enters the constant current charging phase BUCKCHG_FAST and charging resumes.

[0073] Based on the above embodiments, when the main state machine outputs a forward charging state according to the power supply access status, this application controls the power conversion circuit to start according to the forward charging path through the VBUS detection sub-state machine, the forward sub-state machine, and the BUCKCHG sub-state machine. Specifically, the VBUS detection sub-state machine detects whether the bus voltage is higher than the bus voltage threshold. After the detection is passed, the forward sub-state machine controls the first transistor QB to start. After the first transistor QB starts, the forward buck state FORWARD_BUCK is output to switch the voltage conversion circuit DCDC to buck mode BUCK, enabling forward charging. Finally, the BUCKCHG sub-state machine controls the conduction or cutoff of the second transistor BATFET on the forward charging path, and controls the charging stage of the battery according to the current battery voltage, and adjusts the corresponding charging current based on the charging stage. All functions in the forward charging enabling process are realized through the above multiple sub-state machines.

[0074] In one possible embodiment, see Figure 12 , Figure 12 A schematic diagram of the working process of a BATONLY sub-state machine provided in an embodiment of this application is shown below. Figure 12 As shown, the state transition circuit 100 also includes a BATONLY sub-state machine; the BATONLY sub-state machine includes: battery idle state BATONLY_IDLE, battery powered state BATONLY_NORM, and battery reverse powered state BATONLY_BOOST.

[0075] The BATONLY sub-state machine is used to determine whether the voltage conversion circuit has switched to boost mode when the target operating state is BATONLY (battery only). If yes, it outputs the battery reverse power supply state BATONLY_BOOST; otherwise, it outputs the battery power supply state BATONLY_NORM. Among them, the battery power supply state BATONLY_NORM indicates that the system load is powered by the battery, the battery reverse power supply state BATONLY_BOOST indicates that the system load and the bus voltage terminal are powered by the battery, and the battery idle state BATONLY_IDLE indicates that the BATONLY sub-state machine is in an idle state.

[0076] Without the bus voltage VBUS connected, the target operating state of the charging chip output by the main state machine is the battery-only state BATONLY. At this time, the BATONLY sub-state machine will start.

[0077] When the voltage conversion circuit starts up in reverse path, it operates in boost mode. The BATONLY sub-state machine outputs the corresponding state depending on whether the voltage conversion circuit switches to boost mode.

[0078] For details, see Figure 12 If the voltage conversion circuit switches to boost mode (i.e., BOOST is enabled), the BATONLY sub-state machine outputs the battery reverse power supply state BATONLY_BOOST. In this state, the battery needs to supply power to the system load and the bus voltage terminal. When the battery supplies power to the bus voltage terminal, there will be power at the interface between the adapter and the portable electronic device. If a peripheral device such as a USB flash drive is inserted, data reading can be achieved. If the voltage conversion circuit does not switch to boost mode (i.e., BOOST is disabled), the BATONLY sub-state machine outputs the battery powered state BATONLY_NORM. In this case, the battery only needs to supply power to the system load. The battery idle state BATONLY_IDLE indicates that the BATONLY sub-state machine is in an idle state, waiting for new instructions.

[0079] In one possible embodiment, see Figure 13 , Figure 13 This application provides a schematic diagram of the working process of a BOOST sub-state machine, as shown in the embodiment. Figure 13 As shown, the BOOST sub-state machine is used to control the startup of the first transistor QB, the voltage conversion circuit DCCDC, and the second transistor BATFET on the reverse discharge path when the BATONLY sub-state machine outputs the battery reverse power supply state BATONLY_BOOST; it is also used to perform a hiccup mode restart when the voltage conversion circuit DCCDC is in boost mode BOOST and a fault occurs in the voltage conversion circuit DCCDC.

[0080] When the BATONLY sub-state machine outputs the battery reverse power supply state BATONLY_BOOST, it indicates that the battery needs to supply power to the system load and the bus voltage terminal. In the lower-level logic control of the BATONLY sub-state, a BOOST sub-state machine is set up to control the power circuits on the corresponding reverse discharge path under the battery reverse power supply state BATONLY_BOOST. Specifically, when the BATONLY sub-state machine outputs the battery reverse power supply state BATONLY_BOOST, the BOOST sub-state machine controls the activation of the first transistor QB, the voltage conversion circuit DC-DC, and the second transistor BATFET on the reverse discharge path.

[0081] See Figure 13When the reverse discharge path needs to be enabled, the DC-DC converter is controlled to be in boost mode (i.e., BOOST is enabled). The BOOST sub-state machine outputs the BOOST soft-start state BOOST_SS and waits for the BOOST soft-start to complete. After the BOOST soft-start is completed, the DC-DC_SS_OVER flag is received, and the BOOST sub-state machine outputs the BOOST normal operation state BOOST_NORM. In this state, the DC-DC converter operates in boost mode BOOST, providing normal power to the system load and the bus voltage terminal.

[0082] The BOOST sub-state machine in this application is also compatible with a hiccup mode restart function when a fault occurs in the DC-DC converter operating in boost mode. This hiccup mode restart function is also known as HICCUP. For details, see [link to details]. Figure 13 The hiccup mode restart function requires continuous HICCUP type protection detection under the normal BOOST_NORM state of BOOST in boost mode. If a hiccup mode restart HICCUP fault occurs in the DC-DC converter circuit of BOOST operating in boost mode, the DC-DC converter circuit of BOOST operating in boost mode will enter the following loop process: BOOST_RETRY_OFF state -> BOOST_RETRY_DCDC state -> BOOST_RETRY_QB state -> BOOST_NORM state of normal BOOST operation in boost mode, until the fault is eliminated and the restart attempt is successful.

[0083] For details, see Figure 13If the DC-DC converter circuit operating in boost mode experiences a hiccup mode restart (HICCUP) fault, the BOOST sub-state machine outputs the boost mode restart off state BOOST_RETRY_OFF. In this state, the boost mode BOOST of the DC-DC converter circuit is temporarily turned off. After waiting for 250ms, the BOOST sub-state machine outputs the boost mode BOOST restart DC-DC state BOOST_RETRY_DCDC. In this state, the DC-DC converter circuit is attempted to be turned on, and the HICCUP type protection detection is disabled. Upon receiving the DC-DC_SS_OVER flag, the boost mode BOOST soft start is considered complete. The BOOST sub-state machine then outputs the boost mode BOOST restart QB state BOOST_RETRY_QB. In this state, the first transistor QB is attempted to be turned on according to the register configuration, and the HICCUP type protection detection is also disabled. After waiting for 250ms, the BOOST sub-state machine outputs the boost mode BOOST normal operation state BOOST_NORM. In this state, the HICCUP type protection detection is continuously performed. This cyclic process implements the hiccup mode restart function.

[0084] In this application, the number of times the hiccup mode is restarted is set to 7, that is, the above loop process will be executed 7 times. If the fault recovery fails more than 7 times, the BOOST enable of the boost mode will be cleared and the BOOST sub-state machine will return to the boost mode idle state BOOST_IDEL.

[0085] Based on the above embodiments, when the main state machine outputs a battery-only state based on the power supply connection status, this application controls the power conversion circuit to start according to the reverse charging path through the BATONLY sub-state machine and the BOOST sub-state machine. Specifically, the BATONLY sub-state machine outputs the battery reverse power supply state BATONLY_BOOST and the battery power supply state BATONLY_NORM; then, the BOOST sub-state machine, under the battery reverse power supply state BATONLY_BOOST, controls the startup of the first transistor QB, the voltage conversion circuit DCCDC, and the second transistor BATFET on the reverse discharge path. It also supports a hiccup mode restart function when the voltage conversion circuit DCCDC is operating in boost mode BOOST and a fault occurs. All functions in the reverse charging enable process are realized through the above multiple sub-state machines.

[0086] In one possible embodiment, see Figure 6The power conversion circuit 200 further includes a power switch VBST and a voltage regulator circuit VLDO. The second-stage power circuit 202 includes a power switch VBST and a voltage regulator circuit VLDO. Alternatively, the fourth-stage power circuit 204 includes a voltage regulator circuit VLDO, and the sixth-stage power circuit 206 includes a power switch VBST.

[0087] The power switch VBST is used to control itself to turn on after the intermediate power supply VPMID and the first software enable signal are connected.

[0088] The voltage regulator circuit VLDO is used to control itself to turn on after the intermediate power supply VPMID or battery VBST voltage is connected and a second software enable signal is received.

[0089] In this application, the power conversion circuit 200 includes a first transistor QB, a voltage conversion circuit DC-DC, a second transistor BATFET, and typically also includes a power switch VBST and a voltage regulator circuit VLDO. The power switch VBST serves as a switch between the intermediate power supply VPMID and the subsequent circuits, and the voltage regulator circuit VLDO is used to provide power to other circuits within the charging chip, for example, to provide a 1.2V power supply.

[0090] See Figure 6 The power switch VBST and the voltage regulator circuit VLDO need to be placed in different power circuits depending on whether it is a forward charging path or a reverse discharging path. Specifically, in the forward charging path, the power switch VBST and the voltage regulator circuit VLDO are set in the second-stage power circuit 202; in the reverse charging path, the voltage regulator circuit VLDO is set in the fourth-stage power circuit 204, and the power switch VBST is set in the sixth-stage power circuit 206.

[0091] The control logic for the power switch VBST and the voltage regulator circuit VLDO is simpler than that for the power conversion circuit, specifically for the first transistor QB, the voltage conversion circuit DC-DC, and the second transistor BATFET, requiring no state machine for control. For the voltage regulator circuit VLDO, in the forward charging path, its power supply is the intermediate power supply VPMID, while in the reverse charging path, its power supply is the battery VBAT.

[0092] The voltage regulator circuit VLDO connects to the intermediate power supply VPMID in the forward charging path and turns itself on upon receiving the second software enable signal; it also connects to the battery VBAT in the forward charging path and turns itself on upon receiving the second software enable signal. The power switch VBST uses the intermediate power supply VPMID in both the forward and reverse charging paths; therefore, the power switch VBST turns itself on upon connecting to the intermediate power supply VPMID and receiving the first software enable signal.

[0093] To reduce the complexity of the control logic and simplify the control process, this application requires layering the components included in the power conversion circuit. This facilitates layer-by-layer logic control of the state transition circuit. For each layer, corresponding protection needs to be implemented. This reduces the implementation difficulty between power circuits at different levels, reduces the consumption of logic resources, makes the control logic more flexible and maintainable, and facilitates the adjustment and modification of protection behavior in the future.

[0094] For example, see Figure 6 When the intermediate power supply VPMID at the intermediate voltage node PMID is overvoltage (i.e., PMID_OVP=1), the power circuits of subsequent stages will be affected. Since the intermediate power supply VPMID is the power supply for the voltage conversion circuit DC-DC, PMID_OVP=0 (i.e., the intermediate power supply VPMID at the intermediate voltage node PMID is not overvoltage) can be used as the start-up condition for the voltage conversion circuit DC-DC, and it has no direct relationship with the second transistor BATFET in the subsequent stage. When the intermediate power supply VPMID is overvoltage, the voltage conversion circuit DC-DC is turned off. After the voltage conversion circuit DC-DC finishes turning on, the end flag DC-DC_SS_DONE returned by the analog circuit will be cleared to zero. The end flag SS_DONE of the previous stage will also be cleared to zero. That is, after SS_DONE=0, the second transistor BATFET will be turned off.

[0095] Based on the above embodiments, the corresponding protection in each level is set at the nodes of each power stage circuit. When a fault occurs at that node, the power stage circuits after that node will be shut down sequentially. This protection method facilitates the management and control of the power conversion circuit. In large-scale systems, it reduces the implementation difficulty between power circuits at different levels, reduces logic resource consumption, makes the control logic more flexible and maintainable, and facilitates the adjustment and modification of protection behavior in the later stages.

[0096] In one possible embodiment, the target state machine is further configured to receive a protection signal and, in response to the protection signal, control itself to return to an idle state; wherein, the target state machine is any one of the VBUS detection sub-state machine, forward sub-state machine, BUCKCHG sub-state machine, BATONLY sub-state machine, and BOOST sub-state machine.

[0097] In this embodiment, the protection signal is used as one of the conditions for enabling the sub-state machine. When the protection signal is not active, the power conversion circuit is started according to the forward charging path or the reverse discharging path. When the protection signal is active, the circuit returns to the idle state in response to the protection signal.

[0098] The following lists the possible protections that may occur with the charging chip, and explains the meaning of each protection: Among them, ~VBUS_MIN: When the bus voltage VBUS < VBUS_MIN, it is considered that the VBUS_QUAL detection fails, and the VBUS_GOOD flag is cleared; VBUS_OVP: When the bus voltage VBUS > VBUS_OVP, it is considered that the bus voltage VBUS is overvoltage; VBUS_SLEEP: When the bus voltage VBUS < VBUS_SLEEP, it is considered that the bus voltage VBUS is undervoltage; TSD: Thermal shutdown of the charging chip; TBAT_OTP: Over-temperature protection of the battery; HIZ: High-impedance mode. Through software configuration, the channel of the voltage conversion circuit DCDC provided for software use is disabled; ~VCC_OK: Power loss of the internal power supply VCC of the charging chip; [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​​When the target state machine is the VBUS detection sub-state machine, the protection signal is VBUS_QUAL protection, which returns the VBUS detection sub-state machine to the second idle state VBUS_QUAL_IDEL. The corresponding VBUS_GOOD flag will be cleared, which will turn off the first transistor QB, the voltage conversion circuit DC-DC (in buck mode BUCK in the forward charging path), and the second transistor BATFET. Among them, VBUS_QUAL protection can include: ~VBUS_MIN, TSD, VBUS_OVP, and VBUS_SLEEP.

[0101] See Figure 10 When the target state machine is a forward sub-state machine, the protection signal is FORWARD protection, which returns the forward sub-state machine to the forward idle state FORWARD_IDEL, and the corresponding voltage conversion circuit DC-DC and charging function are turned off. Among them, FORWARD protection can include: ~VBUS_MIN, TSD, VBUS_OVP, VBUS_SLEEP, HIZ, and ~VCC_OK.

[0102] See Figure 11 When the target state machine is the BUCKCHG sub-state machine, the protection signal is the BUCKCHG protection, which returns the BUCKCHG sub-state machine to the charging idle state BUCKCHG_IDEL and disables the charging function. The BUCKCHG protection can include: ~VBUS_MIN, TSD, VBUS_OVP, VBUS_SLEEP, HIZ, ~VCC_OK, and IBATFET_OCP.

[0103] For the reverse charging path: See Figure 12 When the target state machine is the BATONLY sub-state machine, the protection signal is the BATONLY protection, which returns the BATONLY sub-state machine to the battery idle state BATONLY_IDLE and turns off the second transistor BATFET; among them, BATONLY protection can include IBATFET_OCP and TBAT_OTP.

[0104] See Figure 13When the target state machine is the BOOST sub-state machine, the protection signal is BOOST protection, which returns the BOOST sub-state machine to the boost mode idle state BOOST_IDEL, clears the BOOST enable signal, and causes the BATONLY sub-state machine to return to the battery powered state BATONLY_NORM. Correspondingly, the boost mode BOOST of the voltage conversion circuit DC-DC and the first transistor QB are turned off. Among them, BOOST protection can include: IBATFET_OCP, TBAT_OTP, HIZ, TSD, TBAT_OTP, VBAT_LOW, PMID_OVP, BOOST HICCUP>7 times.

[0105] In addition, the BOOST sub-state machine is also compatible with the hiccup mode restart function, which enables the BOOST sub-state machine to enter the HICCUP loop process, and the corresponding restart of the voltage conversion circuit DC-DC and the first transistor QB of the boost mode BOOST. The hiccup mode restart protection can include: PMID_SCP, PMID_LT_VBAT, CONV_OCP.

[0106] Corresponding protections are also provided for the power switch VBST and the voltage regulator circuit VLDO. The protection signal for the power switch VBST is called VBST protection, which clears the first software enable signal of the power switch VBST to zero, thereby turning off the power switch VBST. The VBST protection can include: HIZ, TSD, TBAT_OTP, and VBST_OCP.

[0107] The VLDO protection signal of the voltage regulator circuit is the VLDO protection, which clears the second software enable signal of the VLDO voltage regulator circuit to zero, thereby turning off the VLDO voltage regulator circuit. The VLDO protection can include: HIZ, TSD, TBAT_OTP, and VLDO_OCP.

[0108] In this embodiment, the aforementioned protection signals are assigned to the control level of the corresponding sub-state machine, serving as the entry conditions for each sub-state machine. This facilitates the implementation of protection behaviors, making the control logic more flexible, more maintainable, and easier to adjust and modify the protection behaviors later.

[0109] This application also provides a charging chip, including: the digital logic control circuit as described above.

[0110] In one possible embodiment, the charging chip can be a wired charging chip.

[0111] This application also provides an electronic device, including: a charging chip as described above.

[0112] In one possible embodiment, the electronic device may include, but is not limited to, adapters, chargers, tablets, smart home devices, vehicles, and wearable devices.

[0113] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A digital logic control circuit, wherein the digital logic control circuit is applied in a charging chip, characterized in that, The digital logic control circuit includes: a state transition circuit, a power conversion circuit, and an analog circuit; the power conversion circuit includes: a first transistor, a voltage conversion circuit, and a second transistor. The state transition circuit is used to output the working state of the charging chip according to the access status of the power supply, wherein the power supply includes: bus voltage power supply and battery power supply; the bus voltage power supply indicates that the charging chip is powered by the bus voltage, and the battery power supply type indicates that the charging chip is powered by the battery. The power conversion circuit is used to control itself to start according to either a forward charging path or a reverse discharging path based on the operating state; wherein, the forward charging path includes: a first-stage power circuit, a second-stage power circuit, and a third-stage power circuit connected in series, the first-stage power circuit including the first transistor, the second-stage power circuit including the voltage conversion circuit, and the third-stage power circuit including the second transistor; the reverse discharging path includes: a fourth-stage power circuit, a fifth-stage power circuit, and a sixth-stage power circuit connected in series, the fourth-stage power circuit including the second transistor, the fifth-stage power circuit including the voltage conversion circuit, and the sixth-stage power circuit including the first transistor; The analog circuit is used to generate a corresponding end flag after the power circuit of the previous stage has been started, so that the power circuit of the next stage can be started based on the end flag.

2. The digital logic control circuit according to claim 1, characterized in that, The state transition circuit includes a main state machine; the main state machine includes a first idle state, a forward charging state, and a battery-only state. The main state machine is used to output the target working state of the charging chip according to the access status of the power supply. The target working state is any one of the first idle state, the forward charging state, and the battery-only state. The forward charging state controls the power conversion circuit to start according to the forward charging path, the battery-only state controls the power conversion circuit to start according to the reverse discharge path, and the first idle state indicates that the main state machine is in an idle state.

3. The digital logic control circuit according to claim 2, characterized in that, The state transition circuit further includes: a VBUS detection sub-state machine; The VBUS detection sub-state machine is used to detect whether the bus voltage is higher than the bus voltage threshold when the bus voltage is connected. If yes, it outputs a VBUS detection pass state so that the main state machine outputs the forward charging state; if no, it outputs a VBUS detection idle state so that the VBUS detection sub-state machine is in an idle state.

4. The digital logic control circuit according to claim 3, characterized in that, The state transition circuit further includes a forward sub-state machine; the forward sub-state machine includes a forward idle state and a forward buck state; The forward sub-state machine is used to control the first transistor to start when the target working state is the forward charging state, and to output a forward buck state after the first transistor has started, so that the voltage conversion circuit switches to buck mode; it is also used to output a forward idle state when the main state machine outputs the battery-only state or the first transistor is off, so that the forward sub-state machine is in an idle state.

5. The digital logic control circuit according to claim 4, characterized in that, The state transition circuit further includes a BUCKCHG sub-state machine, used to control the conduction or cutoff of the second transistor on the forward charging path, so that the bus voltage charges the battery through the forward charging path; It is also used to control the charging stage of the battery according to the current voltage of the battery, and adjust the corresponding charging current based on the charging stage; wherein the charging stage includes: trickle charging stage, pre-charging stage, constant current charging stage and constant voltage charging stage.

6. The digital logic control circuit according to claim 5, characterized in that, The state transition circuit further includes a BATONLY sub-state machine; the BATONLY sub-state machine includes: battery idle state, battery powered state, and battery reverse powered state; The BATONLY sub-state machine is used to determine whether the voltage conversion circuit has switched to boost mode when the target operating state is the battery-only state. If yes, it outputs the battery reverse power supply state; if no, it outputs the battery power supply state. The battery power supply state indicates that the system load is powered by the battery, the battery reverse power supply state indicates that the system load and the bus voltage terminal are powered by the battery, and the battery idle state indicates that the BATONLY sub-state machine is in an idle state.

7. The digital logic control circuit according to claim 6, characterized in that, The state transition circuit further includes: a BOOST sub-state machine; The BOOST sub-state machine is used to control the startup of the first transistor, the voltage conversion circuit, and the second transistor on the reverse discharge path when the BATONLY sub-state machine outputs the reverse battery power supply state; it is also used to perform a hiccup mode restart when the voltage conversion circuit fails in boost mode when the voltage conversion circuit is in boost mode.

8. The digital logic control circuit according to claim 7, characterized in that, The target state machine is also used to receive a protection signal and, in response to the protection signal, control itself to return to an idle state; wherein, the target state machine is any one of the VBUS detection sub-state machine, the forward sub-state machine, the BUCKCHG sub-state machine, the BATONLY sub-state machine, and the BOOST sub-state machine.

9. The digital logic control circuit according to claim 1, characterized in that, The power conversion circuit further includes a power switch and a voltage regulator circuit. The second-stage power circuit includes the power switch and the voltage regulator circuit. Alternatively, the fourth-stage power circuit includes the voltage regulator circuit, and the sixth-stage power circuit includes the power switch. The power switch is used to control itself to turn on after the intermediate power supply and the first software enable signal are connected. The voltage regulator circuit is used to control itself to turn on after being connected to an intermediate power source or battery voltage and receiving a second software enable signal.

10. A charging chip, characterized in that, include: The digital logic control circuit as described in any one of claims 1-9.

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