Adaptive digital predistortion device, electronic device and operating method of electronic device

Abstract

An adaptive digital pre-distortion apparatus, an electronic apparatus, and an operation method of the electronic apparatus are provided. The adaptive digital pre-distortion device comprises: a legacy digital pre-distortion (DPD) device; one or more processors including processing circuitry; and a memory storing instructions. The instructions, when executed individually or collectively by the one or more processors, cause the adaptive DPD device to: receive a plurality of system parameters; estimating one or more coefficients of the legacy DPD device using a neural network; and applying the one or more coefficients to the legacy DPD device. The neural network is configured to generate the one or more coefficients as an output based on the plurality of system parameters.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0105745, filed on August 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates generally to power amplifiers, and more particularly, to an adaptive digital pre-distortion apparatus, an electronic apparatus, and an operating method of an electronic apparatus. BACKGROUND

[0003] Digital pre-distortion (DPD) can refer to a technology that can potentially save power by reducing and / or minimizing a bias voltage of a power amplifier (PA) and / or can utilize an increased non-linearity for transmission. That is, a response of a PA can be pre-compensated to adjust the response to be substantially linear and / or close to linear. The adjustment can be performed by pre-distortion in a digital domain.

[0004] DPD can be applied to various power amplification scenarios. For example, DPD coefficients and / or DPD responses can be pre-generated according to several representative scenarios, and for similar power amplification scenarios, such as, but not limited to, adjacent frequencies and / or adjacent transmission powers, the DPD coefficients and / or DPD responses can be used as-is without modification. Alternatively or additionally, only a bias voltage of a PA can be adjusted based on, for example, but not limited to, an indicator of an adjacent channel leakage ratio (ACLR) at fixed DPD coefficients. That is, in a case where a linearity of a PA cannot be guaranteed due to, for example, being unable to respond to all possible power amplification scenarios based on only fixed DPD coefficients or by partially modifying a bias voltage of a PA, etc., a transmission capability and / or performance of the PA can be degraded. Therefore, since a need for transmission performance can be subject to constraints of being unable to respond to possible power amplification scenarios, there is a need for further improvement of power amplifier technology. Improvements are presented herein. These improvements can also be applicable to other technologies. SUMMARY

[0005] One or more example embodiments of the disclosure provide a digital pre-distortion coefficient estimation apparatus and an operating method of the apparatus, in which the apparatus learns and infers coefficients of digital pre-distortion based on a neural network that takes system parameters as input.

[0006] According to an aspect of the disclosure, an adaptive digital pre-distortion apparatus includes a legacy digital pre-distortion (DPD) apparatus, one or more processors including processing circuitry, and a memory storing instructions. The instructions, when executed by the one or more processors individually or collectively, cause the adaptive DPD apparatus to receive a plurality of system parameters, estimate one or more coefficients of the legacy DPD apparatus using a neural network, and apply the one or more coefficients to the legacy DPD apparatus. The neural network is configured to generate the one or more coefficients as an output based on the plurality of system parameters.

[0007] According to an aspect of the disclosure, an electronic apparatus includes communication circuitry including an adaptive DPD apparatus and a power amplifier, the adaptive DPD apparatus including a legacy DPD apparatus and a neural network apparatus, the power amplifier configured to amplify an output of the adaptive DPD apparatus, a processor configured to determine an operation mode of the neural network apparatus and provide a plurality of system parameters to the neural network apparatus, and a memory storing weights of the neural network apparatus. The neural network apparatus is configured to receive the plurality of system parameters as an input and generate coefficients of the legacy DPD apparatus as an output.

[0008] According to an aspect of the disclosure, an operation method of an electronic apparatus includes receiving a plurality of system parameters, generating coefficients of a legacy DPD apparatus of the electronic apparatus based on the plurality of system parameters using a neural network, applying the coefficients to the legacy DPD apparatus, receiving modulated transmission data using the legacy DPD apparatus, performing pre-distortion on the modulated transmission data using the legacy DPD apparatus, and amplifying a signal on which the pre-distortion is performed.

[0009] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or can be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0010] The foregoing and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description, as taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating an electronic apparatus according to an embodiment.

[0012] Figure 2 is a block diagram of communication circuitry according to an embodiment.

[0013] Figure 3 shows an example of a transmission path according to a comparative example.

[0014] Figure 4 shows an example of a transmission path according to an embodiment.

[0015] Figure 5is an example of a neural network according to an embodiment.

[0016] Figure 6 shows an example of an adaptive digital pre-distortion block according to an embodiment.

[0017] Figure 7 shows a transmission path corresponding to an online structure according to an embodiment.

[0018] Figure 8A shows an example of a neural network corresponding to an offline structure according to an embodiment.

[0019] Figure 8B shows another example of a neural network corresponding to an offline structure according to an embodiment.

[0020] Figure 9 is a block diagram of a wireless communication device according to an embodiment. DETAILED DESCRIPTION

[0021] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are to be considered in the context of the disclosure. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. In addition, descriptions of well-known functions and constructions can be omitted for clarity and conciseness.

[0022] With regard to the description of the drawings, like reference numerals can be used to refer to like or similar elements. It is to be understood that a singular form of a noun can include one or more things unless the relevant context clearly indicates otherwise. As used herein, each of such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C” can include any one of the items enumerated by the corresponding one of the phrases. As used herein, such as “1st” and “2nd,” or “first” and “second,” can be used to simply distinguish a corresponding component from another, and do not in other ways limit (e.g., in importance or order) the component. It will be understood that if an element (for example, a first element) is referred to as being “coupled with” or “connected with” or “joined with” or “connected to” another element (for example, a second element) without qualification, then the element can be directly coupled with or connected with or joined with or connected to the other element or coupled with or connected with or joined with or connected to the other element, without going through the other element.

[0023] Reference throughout this disclosure to "one embodiment," "an embodiment," "exemplary embodiment," or similar language can indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Thus, appearances of the phrases "in one embodiment," "in an embodiment," "in an exemplary embodiment," and similar language throughout this disclosure can, but not always, signify the same embodiment. The embodiments described herein are exemplary embodiments and, therefore, the disclosure is not limited to the embodiments described herein and can be implemented in various other forms.

[0024] It should be understood that the particular order or hierarchy of the blocks in the processes / flowcharts disclosed is an example. It should be appreciated that the particular order or hierarchy of the blocks in the processes / flowcharts can be rearranged based on design. Furthermore, some blocks can be combined or omitted. The attached claims present elements of the various blocks in a sample order, and are not meant to be limited to the particular order or hierarchy presented.

[0025] Embodiments herein can be described and in terms of blocks which perform one or more functions. These blocks can be referred to herein as blocks, units, modules, etc., or using names such as device, logic, circuit, controller, counter, comparator, generator, transformer, etc. These blocks can be physically implemented by analog and / or digital circuitry comprising one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0026] In this disclosure, the articles "a," "an," and "the" are intended to include one or more items, and can be used interchangeably with the definite article "the" unless otherwise indicated. For example, the term "a processor" can refer to a single processor or multiple processors. Where a processor is described as performing an operation, it will be understood that the processor can perform the operation in conjunction with one or more other processors.

[0027] In the following, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating an electronic device 100 according to an embodiment.

[0029] Referring to Figure 1 , the electronic device 100 can include a communication circuit 110, a memory 120, and a processor 130.

[0030] According to an embodiment, the communication circuit 110 can perform functions for transmitting signals to and / or receiving signals from external devices via wireless and / or wired channels. External devices may be, and / or include, but are not limited to, base stations and / or other electronic devices. For example, the communication circuit 110 can perform a conversion function between baseband signals and bitstreams according to the system's physical layer specifications. For example, when transmitting data to an external device, the communication circuit 110 can generate complex symbols by encoding and / or modulating the transmitted bitstream, and when receiving data from an external device, the communication circuit 110 can recover the received bitstream by demodulating and / or decoding the baseband signals.

[0031] Furthermore, the communication circuit 110 can up-convert a baseband signal to a radio frequency (RF) band signal and transmit the converted signal via an antenna, and / or down-convert an RF band signal received via the antenna to a baseband signal. For example, the communication circuit 110 may include a transmit filter, a receive filter, a power amplifier, a mixer, an oscillator, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), etc. The communication circuit 110 can perform beamforming. To impart directionality to the signal to be transmitted and / or received, the communication circuit 110 may apply beamforming weights to the signal.

[0032] The communication circuit 110 can send signals to and receive signals from external devices. For example, the communication circuit 110 can receive downlink signals from a base station. Downlink signals may include synchronization signals (SS), reference signals (RS), system information, configuration messages, control information, downlink data, etc.

[0033] According to an embodiment, the communication circuit 110 may include an adaptive digital predistortion block 115. The adaptive digital predistortion block 115 can adaptively change the digital predistortion coefficients according to the power amplification scenario. The power amplification scenario may represent a combination of factors that determine the characteristics of the power amplifier. For example, the power amplification scenario may represent a combination of at least one system parameter that can affect the linearity of the power amplifier. System parameters may include at least one of the following: power amplifier type, system bandwidth, modulation order, power amplifier bias voltage, power amplifier output voltage, power amplifier target voltage, power amplifier gain, power amplifier operating frequency, power amplifier center frequency, etc. That is, if at least one of the system parameters of the power amplification scenario is changed, the power amplification scenario can be understood as a different power amplification scenario from the previous one.

[0034] The adaptive digital predistortion block 115 can be based on a neural network that can take system parameters as input and output coefficients that will be used in conventional digital predistortion. For example, the neural network can take the bias voltage, gain, operating frequency, etc. of the power amplifier as input and output coefficients that maximize the linearity of the power amplifier's output.

[0035] Memory 120 may store data (such as, but not limited to, basic programs, applications, setup information, etc., that can be used in the operation of electronic device 100). Memory 120 may be and / or may include volatile memory, non-volatile memory, and / or a combination of volatile and non-volatile memory. Memory 120 may provide the stored data upon request from processor 130. According to an embodiment, memory 120 may store data for learning and / or inferring coefficients of adaptive digital predistortion block 115. For example, memory 120 may store weights of the neural network included in adaptive digital predistortion block 115. As another example, memory 120 may also include buffer memory. Buffer memory may be and / or may include memory for temporarily storing power amplifier output data for a specific period of time. Adaptive digital predistortion block 115 may update the weights of the neural network stored in buffer memory by performing training based on the power amplifier output data.

[0036] Processor 130 controls the overall operation of electronic device 100. For example, processor 130 can send signals to and / or receive signals from external devices via communication circuitry 110. Furthermore, processor 130 can write data to memory 120 and / or read data from memory 120. For this purpose, processor 130 can be and / or may include at least one processor or microprocessor, or can be a portion of a processor (e.g., a core). For example, processor 130 can be implemented using one or more general-purpose or special-purpose computers (such as, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device capable of responding to and executing instructions in a defined manner). When processor 130 is a portion of a processor, the portion of communication circuitry 110 and processor 130 can be referred to as a communication processor (CP). Adaptive digital predistortion block 115 can be implemented as digital circuitry and / or incorporated into processor 130. For simplicity, the description of processor 130 is used as singular; however, those skilled in the art will understand that processor 130 may include multiple processing elements and / or various types of processing elements. For example, processor 130 may include multiple processors or a processor and a controller. Furthermore, different processing configurations (such as parallel processors) may be feasible.

[0037] According to an embodiment, processor 130 may determine an operating mode for adaptive digital predistortion block 115. For example, processor 130 may determine one of the following operating modes: a first operating mode in which adaptive digital predistortion block 115 performs neural network training for each sample; a second operating mode in which adaptive digital predistortion block 115 stores power amplifier output data in a buffer memory and performs neural network training on each output data of a predetermined size based on the output data stored in the buffer memory; and a third operating mode in which the performance metrics of the power amplifier are monitored and neural network training is performed in response to a performance metric (e.g., adjacent channel leakage ratio (ACLR)) falling below a certain level. In an embodiment, processor 130 may provide system parameters to the neural network.

[0038] Figure 2 This is a block diagram of a communication circuit according to an embodiment.

[0039] Reference Figure 2 The communication circuit 200 may include an encoding and modulation unit 210, a digital beamforming unit 220, multiple transmission paths (e.g., a first transmission path 230-1 to the Nth transmission path 230-N, where N is a positive integer greater than 1) and an analog beamforming unit 240. Figure 2 The communication circuit 200 may include the above-mentioned reference Figure 1 The described communication circuit 110 and / or may be related in many respects to the above reference. Figure 1 The described communication circuit 110 is similar and may include additional features not mentioned above. Therefore, for the sake of brevity, the above references... Figure 1 The repeated description of the communication circuit 110 can be omitted.

[0040] The coding and modulation unit 210 can perform channel coding. For example, the coding and modulation unit 210 can perform channel coding based on at least one of low-density parity-check (LDPC) codes, convolutional codes, polar codes, etc. The coding and modulation unit 210 can generate modulation symbols by performing constellation mapping.

[0041] Digital beamforming unit 220 can perform beamforming on digital signals (e.g., modulation symbols). For example, digital beamforming unit 220 can multiply beamforming weights by modulation symbols. That is, beamforming weights can be used to change the amplitude and / or phase of the signal, and / or may be referred to as a precoding matrix, precoder, etc. Digital beamforming unit 220 can output digitally beamformed modulation symbols to multiple transmission paths (e.g., first transmission path 230-1 to Nth transmission path 230-N). In embodiments, according to a multiple-input multiple-output (MIMO) transmission scheme, modulation symbols can be multiplexed, and / or the same modulation symbols can be provided to first transmission path 230-1 to Nth transmission path 230-N.

[0042] The first transmission paths 230-1 to the Nth transmission paths 230-N can convert digital beamforming signals into analog signals. That is, each of the first transmission paths 230-1 to the Nth transmission paths 230-N may include an inverse fast Fourier transform (IFFT) operation unit, a cyclic prefix (CP) insertion unit, a DAC, an up-conversion unit, etc. The CP insertion unit can be used to perform orthogonal frequency division multiplexing (OFDM), and therefore, the CP insertion unit can be omitted when another physical layer method (e.g., filter bank multicarrier (FBMC)) is applied. In embodiments, the first transmission paths 230-1 to the Nth transmission paths 230-N can provide independent signal processing for multiple streams generated by digital beamforming. However, depending on the implementation method, some components of the first transmission paths 230-1 to the Nth transmission paths 230-N may be shared.

[0043] The analog beamforming unit 240 can perform beamforming on an analog signal. For example, the analog beamforming unit 240 can multiply the analog signal by beamforming weights. That is, the beamforming weights can be used to change the amplitude and / or phase of the signal.

[0044] Figure 3 An example of a transmission path is shown based on the comparison example.

[0045] Reference Figure 3 The transmission path 300 may include a modulator / crest factor reduction (CFR) block 310, a conventional digital predistortion (DPD) block 320, and a DAC / power amplifier (PA) block 330. Figure 3 The transmission path 300 may include the above reference Figure 2 At least one of the first transmission path 230-1 to the Nth transmission path 230-N described above and / or may be related to the above reference in many respects. Figure 2 At least one of the first transmission paths 230-1 to the Nth transmission path 230-N described is similar and may include additional features not mentioned above. Therefore, for the sake of brevity, the above refers toFigure 2 Repeated descriptions of the transmission path can be omitted.

[0046] Modulator / CFR block 310 can receive transmission data TX data from digital baseband and modulate the received transmission data TX data. For example, modulator / CFR block 310 can modulate the transmission data TX data based on various modulation techniques, such as, but not limited to, binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), quadrature amplitude modulation (16-QAM), and 64-QAM. However, the modulation performed in modulator / CFR block 310 is not limited to the above-mentioned techniques and may include other modulation techniques.

[0047] Modulator / CFR block 310 performs crest factor reduction on the modulated transmitted data TX data. CFR indicates clipping of the modulated transmitted data TX data. That is, after passing through the power amplifier, peak components can be removed to reduce and / or prevent peak-to-average power ratio (PAPR). The transmitted data TX data modulated and clipped by modulator / CFR block 310 can be input to conventional DPD block 320.

[0048] The conventional DPD block 320 can receive modulated and clipped transmitted data (TX data) and perform predistortion on the modulated and clipped transmitted data (TX data). Predistortion can be described as adjusting the data in such a way that, taking into account the nonlinear output of the next-stage DAC / PA block 330, the signal input to the DAC / PA block 330 can be provided after predistortion of the signal, so that a linear output of the DAC / PA block 330 can be generated. The conventional DPD block 320 can correspond to any circuit and / or functional block capable of performing the relevant DPD function.

[0049] The DAC / PA block 330 can generate inputs for the front-end module. For example, the DAC / PA block 330 can perform digital-to-analog conversion on pre-distorted transmitted data (TX data) from the conventional DPD block 320. Optionally or additionally, the DAC / PA block 330 can amplify the signal strength of the analog-to-analog converted signal through a power amplifier and output the amplified analog-to-analog converted signal to the front-end module.

[0050] As a comparative example, a conventional DPD block 320 can perform predistortion on the modulated and clipped transmitted data (TX data) based on at least one fixed coefficient (e.g., DPD coefficients). For example, according to the comparative example, the electronic device can store the DPD coefficients for each power amplification scenario as a lookup table (LUT). For example, the LUT can pre-store, for instance, first DPD coefficients for making the power amplifier output linear in a first power amplification scenario (e.g., the center frequency can be a first frequency, and the bias voltage can be a first voltage value), and second DPD coefficients for making the power amplifier output linear in a second power amplification scenario (e.g., the center frequency can be a second frequency, and the bias voltage can be a second voltage value). The conventional DPD block 320 can perform predistortion by loading DPD coefficients that match the power amplification scenario. For a new power amplification scenario that may not be stored in the LUT, there may not be DPD coefficients that match the new power amplification scenario. Therefore, the conventional DPD block 320 can perform predistortion either by using the DPD coefficients corresponding to the power amplification scenario most similar to the new power amplification scenario, or by changing a portion of the power amplifier settings (e.g., bias voltage, etc.). However, in such cases, the linearity of the power amplifier can be reduced.

[0051] Figure 4 An example of a transmission path according to an embodiment is shown.

[0052] Reference Figure 4 The transmission path 400 may include a modulator / CFR block 410, a conventional DPD block 420, a DAC / PA block 430, a neural network (NN) control block 440, and a coefficient estimator 450. Figure 4 The transmission path 400 may include the above reference Figure 2 At least one of the first transmission path 230-1 to the Nth transmission path 230-N described above and / or may be related to the above reference in many respects. Figure 2 At least one of the described first transmission paths 230-1 to the Nth transmission path 230-N is similar and may include additional features not mentioned above. Furthermore, Figure 4 The modulator / CFR block 410, conventional DPD block 420, and DAC / PA block 430 may respectively include the above-mentioned references. Figure 3 The modulator / CFR block 310, conventional DPD block 320, and DAC / PA block 330 described herein are and / or may be related to the above references in many respects. Figure 3 The modulator / CFR block 310, conventional DPD block 320, and DAC / PA block 330 are described similarly and may include additional features not mentioned above. Therefore, for the sake of brevity, the above references... Figure 2 and Figure 3 Repeated descriptions of the transmission path can be omitted.

[0053] According to an embodiment, the NN control block 440 can control the overall operation of the neural network of the coefficient estimator 450. The NN control block 440 can determine the operating mode of the neural network and can provide inputs for training the neural network. In one embodiment, the NN control block 440 can provide system parameters as inputs for training the neural network. System parameters may include all factors affecting the linearity of the power amplifier's output. For example, system parameters may include at least one of the following: power amplifier type, system bandwidth, modulation order, power amplifier bias voltage, power amplifier output voltage, power amplifier target voltage, power amplifier gain, power amplifier operating frequency, power amplifier center frequency, etc.

[0054] In an embodiment, the NN control block 440 can determine the operating mode of the neural network. When the electronic device 100 operates in a low-power mode, the NN control block 440 can deactivate a first operating mode that performs training on each sample of transmitted data to reduce the resources and power consumed for learning and inference of the neural network. Optionally, the NN control block 440 can temporarily store the transmitted data in a buffer memory, and when the buffer memory is full, it can activate a second operating mode to train the neural network based on the stored transmitted data. However, if the electronic device 100 does not operate in a low-power mode and / or may have sufficient resources and power for learning and inference of the neural network, the NN control block 440 can set the neural network to the first operating mode.

[0055] Optionally, the NN control block 440 may select a third operating mode to guide the training of the neural network based on monitoring the performance of the power amplifier, rather than performing learning on each sample and / or a fixed amount of transmission data. The NN control block 440 may monitor metrics representing the performance of the power amplifier. For example, the NN control block 440 may monitor metrics such as the adjacent channel leakage ratio (ACLR) to determine if the performance of the power amplifier has degraded. ACLR is just one example of metrics that can represent the performance of the power amplifier, and the NN control block 440 may monitor all metrics that can represent the performance of the power amplifier. The NN control block 440 may determine that the ACLR has dropped below a threshold. An ACLR dropping below a threshold may indicate that the performance metric of the power amplifier has degraded because the DPD coefficients inferred by the neural network and provided to the conventional DPD block 420 may not be optimal. Therefore, the NN control block 440 may perform neural network training in response to the performance metric of the power amplifier (which has dropped below a threshold). The training of the neural network may be performed on each sample of transmission data, and / or may be performed based on transmission data temporarily stored in a buffer memory.

[0056] According to an embodiment, the coefficient estimator 450 may output DPD coefficients based on a neural network. The output DPD coefficients may be the optimal coefficients for the output of the power amplifier to exhibit the best linearity in a given power amplification scenario. The input to the coefficient estimator 450 may be a combination of system parameters. The combination of system parameters may be referred to as the power amplification scenario.

[0057] Figure 5 This is an example of a neural network according to an embodiment.

[0058] Reference Figure 5 A neural network NN may include multiple layers (e.g., a first layer L1, a second layer L2, and a third layer L3). Figure 5 The neural network NN can include the above reference Figure 4 The coefficient estimator 450 described above and / or may be related to the above reference in many ways. Figure 4 The coefficient estimator 450 is described similarly and may include additional features not mentioned above. Therefore, for the sake of brevity, the above references... Figure 4 Repeated descriptions of the neural network can be omitted.

[0059] Each of the multiple layers L1 to L3 may be and / or may include linear layers and / or nonlinear layers, and in some embodiments, at least one linear layer and at least one nonlinear layer may be combined and referred to as a single layer. For example, linear layers may include convolutional layers and fully connected layers, and nonlinear layers may include sampling layers, pooling layers, and activation layers.

[0060] For example, the first layer L1 can be a convolutional layer, and the second layer L2 can be a sampling layer. The neural network NN may also include activation layers, and may also include layers that can perform different types of computations.

[0061] Each of the multiple layers L1 to L3 can receive input data and / or feature maps generated from the previous layer as input feature maps, and can generate output feature maps by computing the input feature maps. Feature maps can represent data expressing various features of the input data. Feature maps (e.g., first feature map FM1, second feature map FM2, and third feature map FM3) can have, for example, the form of a two-dimensional (2D) matrix or a three-dimensional (3D) matrix. First feature maps FM1 to third feature maps FM3 have a width W (or column), height H (or row), and depth D that correspond to the x-axis, y-axis, and z-axis in a coordinate system, respectively. The depth D can be referred to as the number of channels.

[0062] The first layer L1 generates the second feature map FM2 by convolving the first feature map FM1 with the weight map WM. The weight map WM can filter the first feature map FM1 and can be referred to as a filter or kernel. For example, the depth (e.g., the number of channels) of the weight map WM can be the same as the depth (e.g., the number of channels) of the first feature map FM1, and the same channels of the weight map WM and the first feature map FM1 can be convolved. The weight map WM can be shifted by traversing the first feature map FM1 using a sliding window. The amount of shift can be referred to as the stride length or stride. During each shift, each of the weights included in the weight map WM can be multiplied by all the feature values ​​in the region overlapping with the first feature map FM1, and the multiplication results are summed. Since the first feature map FM1 and the weight map WM can be convolved with each other, one channel of the second feature map FM2 can be generated. Although in Figure 2 The diagram shows a single weight map WM, but in practice, multiple weight maps can be convolved with a first feature map FM1 to generate multiple channels of a second feature map FM2. That is, the number of channels in the second feature map FM2 can correspond to the number of weight maps.

[0063] The second layer L2 can generate a third feature map FM3 by changing the spatial size of the second feature map FM2. For example, the second layer L2 can be a sampling layer. The second layer L2 can perform upsampling and / or downsampling, and it can select portions of the data included in the second feature map FM2. For example, a two-dimensional (2D) window WD can be shifted on the second feature map FM2 in units of the size of the window WD (e.g., a 4×4 matrix), and values ​​at specific locations (e.g., 1 row and 1 column) can be selected in the region overlapping with the window WD. The second layer L2 can output the selected data as the data for the third feature map FM3. As another example, the second layer L2 can be a pooling layer. In this case, the maximum value (or average value) of the eigenvalues ​​in the region overlapping with the window WD in the second feature map FM2 can be selected in the second layer L2. The second layer L2 can output the selected data as the data for the third feature map FM3. Thus, a third feature map FM3 with a changed spatial size can be generated from the second feature map FM2. The number of channels in the third feature map FM3 can be the same as the number of channels in the second feature map FM2.

[0064] In some embodiments, the second layer L2 may not be limited to a sampling layer or a pooling layer. That is, the second layer L2 may be a convolutional layer, similar to the first layer L1. In such an embodiment, the second layer L2 can generate a third feature map FM3 by convolving the second feature map FM2 with the weight map. In this case, the weight map to which the convolution operation is performed in the second layer L2 may be different from the weight map WM to which the convolution operation is performed in the first layer L1.

[0065] The Nth feature map can be generated from the Nth layer through multiple layers including a first layer L1 and a second layer L2. The Nth feature map can be input to a reconstruction layer located at the back end of the neural network, from which output data is output. The reconstruction layer can generate output data based on the Nth feature map. The output data can be DPD coefficients that will be provided to the conventional DPD block 420. Furthermore, in addition to the Nth feature map, the reconstruction layer receives multiple feature maps (e.g., a first feature map FM1 and a second feature map FM2) and generates output data based on these multiple feature maps.

[0066] The third layer (L3) can generate output data for the input data by combining features from the third feature map (FM3). For example, the input data can be a combination of system parameters. In this case, the third layer (L3) can generate output data corresponding to the DPD coefficients based on the third feature map (FM3) provided from the second layer (L2).

[0067] Figure 6 An example of an adaptive digital predistortion block 600 according to an embodiment is shown.

[0068] Figure 6 The adaptive digital predistortion block 600 may include the above reference. Figure 1 The described adaptive digital predistortion block 115 and / or may be related to the above reference in many ways. Figure 1 The adaptive digital predistortion block 115 described is similar and may include additional features not mentioned above. Therefore, for the sake of brevity, the above references... Figure 1 The repeated description of the adaptive digital predistortion block can be omitted. (See reference...) Figure 6 The adaptive digital predistortion block 600 may include a neural network 610 for estimating DPD coefficients and a conventional DPD block 620. The neural network 610 may be a pre-trained neural network. In embodiments, the adaptive digital predistortion block 600 may also include one or more processors containing processing circuitry and memory for storing instructions.

[0069] According to an embodiment, the neural network 610 can receive M system parameters (e.g., system parameter 1, system parameter 2, ..., system parameter M) as input, where M is a positive integer greater than 0. For example, the M system parameters may include all factors affecting the linearity of the power amplifier's output. For example, system parameters may include at least one of the following: power amplifier type, system bandwidth, modulation order, power amplifier bias voltage, power amplifier output voltage, power amplifier target voltage, power amplifier gain, power amplifier operating frequency, power amplifier center frequency, etc. The neural network 610 can be described as described above. Figure 5 The description describes the generation of output data across multiple layers.

[0070] According to an embodiment, the neural network 610 can provide multiple DPD coefficients as output data to the conventional DPD block 620. The multiple DPD coefficients can be DPD coefficients that are inferred to ensure that the output of the power amplifier exhibits optimal linearity under new power amplification scenarios (e.g., combinations of system parameters input to the neural network 610).

[0071] Therefore, according to this disclosure, when a new power amplification scenario is experienced while using a conventional DPD block 620, the electronic device 100 can achieve relatively high power amplifier performance without having to learn new DPD coefficients, but by inferring them via the neural network 610.

[0072] Figure 7 The transmission path corresponding to the online structure according to the embodiment is shown.

[0073] Reference Figure 7 The transmission path 700 may include a neural network 710, a conventional DPD block 720, a DAC / PA block 730, a feedback block 740, a scaling / phase compensation block 750, and an error calculation block 760. Figure 7 The neural network 710 and the traditional DPD block 720 can be respectively connected with Figure 6 The neural network 610 corresponds to the traditional DPD block 620, and for the sake of brevity, its repeated description can be omitted.

[0074] The transmission path corresponding to the online structure can represent a structure in which the learning and inference of the neural network 710 can be performed in parallel while transmitting data from the electronic device 100.

[0075] In some embodiments, the DAC / PA block 730 can perform analog conversion and power amplification on the output of the conventional DPD block 720. The DAC / PA block 730 can then provide the amplified signal to the front-end module.

[0076] According to an embodiment, feedback block 740 can receive a signal output from DAC / PA block 730 to the front-end module as feedback. Subsequently, feedback block 740 can provide the feedback signal to scaling / phase compensation block 750.

[0077] According to an embodiment, the scaling / phase compensation block 750 can perform a series of operations to compare the output signal of the power amplifier with the input signal of the conventional DPD block 720. For example, the scaling / phase compensation block 750 can perform scaling to bring the magnitude of the output signal, which has been amplified by the power amplifier's gain, back to the magnitude of the input signal of the conventional DPD block 720. Thereafter, the scaling / phase compensation block 750 can perform phase and delay compensation on the scaled signal. For example, when the signal passes through various signal processing blocks (such as, but not limited to, the conventional DPD block 720, DAC / PA block 730, mixer, down-converter, etc.), the scaled signal may experience phase changes and delays. Therefore, the scaling / phase compensation block 750 can perform phase and delay compensation on the scaled signal.

[0078] According to an embodiment, the error calculation block 760 can calculate the error by comparing the input signal of the conventional DPD block 720 with the output signal of the scaling / phase compensation block 750. The error calculation block 760 can also calculate the error by subtracting the output signal of the scaling / phase compensation block 750 from the input signal of the conventional DPD block 720, where the output signal of the scaling / phase compensation block 750 may be a feedback signal from the output signal of the conventional DPD block 720. The error calculation block 760 can provide the calculated error to the neural network 710. The neural network 710 can perform learning by updating its weights through backpropagation based on the error received from the error calculation block 760.

[0079] Figure 8A An example of a neural network corresponding to an offline structure is shown according to an embodiment. Figure 8B Another example of a neural network corresponding to an offline structure according to an embodiment is shown.

[0080] Reference Figure 8A The transmission path 800 may include a neural network 810, a conventional DPD block 820, and an error calculation block 840. The neural network 810 and the conventional DPD block 820 can be respectively connected to… Figure 6 The neural network 610 corresponds to the traditional DPD block 620, and for the sake of brevity, its repeated description can be omitted.

[0081] The transmission path corresponding to the offline structure can represent a structure in which the electronic device 100 does not send transmission data to an external device and can have a conventional DPD block 820 for the learning and inference of the neural network 810.

[0082] According to an embodiment, the conventional DPD block 820 can receive the output signal of the DAC / PA block 830 as an input signal. The conventional DPD block 820 can perform predistortion on the output signal of the DAC / PA block 830 and output the predistorted output signal to the DAC / PA block 830. Furthermore, the conventional DPD block 820 can provide the predistorted output signal to the error calculation block 840.

[0083] In some embodiments, the DAC / PA block 830 can receive the predistorted output signal via the conventional DPD block 820 and perform analog-to-analog conversion and power amplification on the received predistorted output signal. The DAC / PA block 830 can provide the amplified signal back to the conventional DPD block 820 as an input signal. Furthermore, the DAC / PA block 830 can provide the amplified signal to the error calculation block 840.

[0084] According to an embodiment, the error calculation block 840 can receive the input signal and the output signal of the DAC / PA block 830 respectively, and calculate the difference between the input signal and the output signal as the error. The error calculation block 840 can provide the calculated error to the neural network 810. The neural network 810 can perform learning by updating its weights through backpropagation based on the error received from the error calculation block 840.

[0085] Reference Figure 8B N adders can be arranged between the neural network 810 and the conventional DPD block 820. N may correspond to the number of DPD coefficients and may be a positive integer greater than 0. In some embodiments, the neural network 810 may have already learned the DPD coefficients, which may be a combination of system parameters that are inputs to the neural network. In this case, the NN control block 440 may provide preset DPD coefficients to the N adders. By adding the values ​​of the preset DPD coefficients to the output of the neural network 810 and providing the result to the conventional DPD block 820, learning can be performed only on the residuals.

[0086] Figure 9 This is a block diagram of a wireless communication device 900 according to an embodiment.

[0087] Reference Figure 9 The wireless communication device 900 may include a modem and a radio frequency integrated circuit (RFIC) 960. The modem may include an application-specific integrated circuit (ASIC) 910, an application-specific instruction set processor (ASIP) 930, a memory 950, a main processor 970, and a main memory 990. Figure 9 The wireless communication device 900 may include the above-mentioned reference Figure 1 The described electronic device 100 and / or may be related in many respects to the above reference. Figure 1The described electronic device 100 is similar and may include additional features not mentioned above. Therefore, for the sake of brevity, the above references... Figure 1 Repeated descriptions of the wireless communication device may be omitted.

[0088] RFIC 960 can be connected to antenna Ant and can receive and / or transmit signals to the outside using a wireless communication network. ASIP 930 can be and / or may include a purpose-specific integrated circuit and can support a dedicated instruction set for a specific application and execute instructions included in the instruction set. Memory 950 can communicate with ASIP 930 and, as a non-transitory storage device, can store multiple instructions executed by ASIP 930. For example, memory 950 may include any type of memory accessible by ASIP 930 (such as, but not limited to, random access memory (RAM), read-only memory (ROM), magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof).

[0089] The main processor 970 can control the wireless communication device 900 by executing multiple instructions. For example, the main processor 970 can control the ASIC 910 and ASIP 930 to process data received through the wireless communication network or to process user input for the wireless communication device 900. The main memory 990 can communicate with the main processor 970 and, as a non-transitory storage device, can store multiple instructions executed by the main processor 970. For example, the main memory 990 can include any type of memory accessible by the main processor 970 (such as, but not limited to, RAM, ROM, magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof).

[0090] As described above, embodiments have been disclosed in the accompanying drawings and specification. Although specific terminology has been used to describe the embodiments in this specification, it is for illustrative purposes only and is not intended to limit the meaning or scope of the disclosure as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments are possible. Consequently, the true technical scope of this disclosure should be determined by the technical concept of the appended claims.

[0091] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An adaptive digital predistortion device, comprising: Traditional digital predistortion devices; One or more processors, including processing circuitry; and Memory, stored instructions Wherein, when the instructions are executed individually or jointly by the one or more processors, the adaptive digital predistortion device causes: Receive system parameters; One or more coefficients of a conventional digital predistortion device are estimated using a neural network, which is configured to generate the one or more coefficients as output based on system parameters; and The one or more coefficients are applied to a conventional digital predistortion device.

2. The adaptive digital predistortion device as described in claim 1, wherein, System parameters include at least one of the following: power amplifier type, system bandwidth, modulation order, power amplifier bias voltage, power amplifier output voltage, power amplifier target voltage, power amplifier gain, power amplifier operating frequency, and power amplifier center frequency.

3. The adaptive digital predistortion device as described in claim 1, wherein, When the instructions are executed individually or jointly by the one or more processors, the adaptive digital predistortion device also causes the neural network to determine its operating mode. The operating modes include at least one of a first operating mode, a second operating mode, and a third operating mode. In the first operating mode, the training of the neural network is performed based on the transmission data of each sample. In the second operating mode, the transmission data is temporarily stored in a buffer memory and the training of the neural network is performed based on the transmission data stored in the buffer memory. In the third operating mode, the training of the neural network is performed based on monitoring the performance index of the power amplifier of the adaptive digital predistortion device.

4. The adaptive digital predistortion device as described in claim 3, wherein, The performance metric corresponds to the leakage ratio of adjacent channels.

5. The adaptive digital predistortion device as described in claim 3, wherein, When the instructions are executed individually or jointly by the one or more processors, the adaptive digital predistortion device also causes the neural network to be trained based on the identification that the performance metric is below a threshold.

6. An electronic device comprising: A communication circuit includes an adaptive digital predistortion device and a power amplifier, wherein the adaptive digital predistortion device includes a conventional digital predistortion device and a neural network device, the power amplifier is configured to amplify the output of the adaptive digital predistortion device, and the neural network device is configured to receive system parameters as input and generate coefficients of the conventional digital predistortion device as output. The processor is configured to determine the operating mode of the neural network device and provide system parameters to the neural network device; and Memory stores the weights of the neural network device.

7. The electronic device as claimed in claim 6, wherein, The communication circuit also includes: The modulator circuit is configured as follows: Receive transmitted data, and Modulation is performed on the transmitted data; and The peak factor reduction circuit is configured as follows: Amplification limiting is applied to the modulated transmitted data, and The modulated and clipped transmission data is output to a conventional digital predistortion device. In this configuration, a conventional digital predistortion device is configured to perform predistortion on the modulated and limited transmitted data and generate a signal to which predistortion has been performed, and a power amplifier is configured to amplify the signal to which predistortion has been performed.

8. The electronic device as claimed in claim 7, wherein, Traditional digital predistortion devices are configured to perform predistortion on modulated and clipped transmitted data based on coefficients output by a neural network device.

9. The electronic device according to any one of claims 6 to 8, wherein, System parameters include at least one of the following: power amplifier type, system bandwidth, modulation order, power amplifier bias voltage, power amplifier output voltage, power amplifier target voltage, power amplifier gain, power amplifier operating frequency, and power amplifier center frequency.

10. The electronic device according to any one of claims 6 to 8, wherein, The operating modes include at least one of the following: In the first operating mode, the training of the neural network device is performed based on the transmitted data of each sample; In the second operating mode, the transmitted data is temporarily stored in a buffer memory, and the training of the neural network device is performed based on the transmitted data stored in the buffer memory. as well as In the third operating mode, the training of the neural network device is performed based on monitoring the performance metrics of the power amplifier.

11. The electronic device of claim 7, further comprising: The feedback device is configured to provide feedback on the amplified signal from the power amplifier; as well as The scaling / phase compensation device is configured as follows: The feedback signal is scaled to the same size as the modulated and clipped transmitted data, and Phase and delay compensation are performed on the scaled signal to match the modulated and clipped transmitted data.

12. The electronic device of claim 11, further comprising: The error calculation device is configured to calculate the error by subtracting the modulated and clipped transmitted data from the output of the scaling / phase compensation device.

13. The electronic device of claim 12, wherein, The error calculation device is also configured to provide the calculated error to the neural network device, and The neural network device is also configured to train the neural network by performing a backpropagation operation using the calculated error.

14. A method of operating an electronic device, the method comprising: Receive system parameters; The coefficients of the conventional digital predistortion device for the electronic device are generated using a neural network based on system parameters. The coefficients are applied to a traditional digital predistortion device; Using conventional digital predistortion devices to receive modulated and clipped transmission data; Predistorting the modulated and clipped transmitted data is performed using a conventional digital predistortion device to generate a signal to which predistortion has been performed; as well as The predistorted signal is amplified.

15. The operating method as described in claim 14, further comprising: Receive transmitted data; Modulation is performed on the transmitted data; Amplitude limiting is applied to the modulated transmitted data; as well as The limited transmission data is output to a traditional digital predistortion device.

16. The operating method as described in claim 14 or 15, wherein, System parameters include at least one of the following: power amplifier type, system bandwidth, modulation order, power amplifier bias voltage, power amplifier output voltage, power amplifier target voltage, power amplifier gain, power amplifier operating frequency, and power amplifier center frequency.

17. The operating method as described in claim 14 or 15, further comprising: Determine the operating mode of the neural network. The operating modes include at least one of the following: In the first operating mode, the training of the neural network is performed based on the transmitted data of each sample; In the second operating mode, the transmitted data is temporarily stored in a buffer memory, and the training of the neural network is performed based on the transmitted data stored in the buffer memory; and In the third operating mode, the training of the neural network is performed based on monitoring the performance metrics of the power amplifier.

18. The operating method as described in claim 14, further comprising: Perform a feedback operation on the amplified signal; The feedback signal is scaled to the same size as the modulated and clipped transmitted data. as well as Phase and delay compensation are performed on the scaled signal to match the modulated and clipped transmitted data.

19. The operating method as described in claim 18, further comprising: The error is calculated by subtracting the modulated and clipped transmitted data from the signal that has already been scaled and compensated.

20. The operating method as described in claim 19, further comprising: The calculation error is fed into the neural network; as well as The neural network is trained by performing backpropagation using the calculated error.

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