Common mode voltage correction method of class d amplifier and class d
By introducing a common-mode voltage adjustment circuit into the Class D amplifier, the common-mode voltage of the preamplifier is dynamically adjusted, solving the common-mode voltage matching problem of traditional Class D amplifiers and improving signal linearity and overall performance.
Patent Information
- Application Number
- CN202411339213.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-08
- Filing Date
- 2024-09-25
- Publication Date
- 2026-02-10
AI Technical Summary
Traditional Class D amplifiers tend to exceed the common-mode input range of the operational amplifier when the common-mode voltage of the input signal approaches the boundary, leading to signal distortion and performance degradation.
A common-mode voltage adjustment circuit is adopted, which feeds back the logic voltage status of the output signal of the subsequent driver circuit to the input of the preamplifier through a feedback circuit, and dynamically adjusts the common-mode voltage to match the difference in operating voltage between the preceding and following driver circuits.
It effectively eliminates common-mode voltage offset of input signals, ensures that the circuit operates at the optimal point, reduces signal distortion and noise, and improves signal-to-noise ratio and sound quality.
Smart Images
Figure CN121508472A_ABST
Abstract
Description
Technical Field
[0001] This application relates to a technique for analog amplifiers, and more particularly to a common-mode voltage correction method for a Class D amplifier and a Class D amplifier using the same. Background Technology
[0002] In high-wattage and low-power audio signal processing applications, Class D amplifiers are a common choice. However, traditional Class D amplifier circuits have some inherent design challenges and limitations. The operating principle of a Class D amplifier is to first convert the input analog signal into a digital pulse sequence using pulse width modulation (PWM), and then reconstruct it into an amplified analog signal through a high-efficiency output stage. To achieve high output power, the output stage typically requires a high supply voltage, such as 30V. However, to save power, the operating voltage of the pre-processing circuitry is kept at a lower level, such as 5V.
[0003] In this design, the input signal first enters an operational amplifier for amplification and adjustment. The problem with traditional circuits is that when the common-mode voltage of the input signal approaches its limit, it may exceed the operational amplifier's input common-mode range, causing signal distortion and performance degradation. For example, suppose the output stage voltage is 30V, the amplification factor is 10V / V, the pre-amplifier operating voltage is 5V, and the input common-mode voltage is 2.5V. In this case, after amplification, the common-mode voltage will rise to 3.6V, exceeding the operational amplifier's ±2.5V input common-mode range, resulting in severe signal distortion and reducing the overall efficiency of the Class D amplifier. Summary of the Invention
[0004] Embodiments of this application provide a common-mode voltage correction method for a Class D amplifier and a Class D amplifier using the same, for compensating the common-mode voltage of the preamplifier when the operating voltages of the preamplifier and the postamplifier drive circuits are different, thereby avoiding signal distortion.
[0005] Embodiments of this application provide a Class D amplifier, which includes a preamplifier, a pulse width modulation circuit, a power stage driver circuit, a feedback circuit, and a common-mode voltage adjustment circuit. The preamplifier includes a first input terminal, a first output terminal, a second input terminal, and a second output terminal. A first differential input signal is input to the first input terminal of the preamplifier, a second differential input signal is input to the second input terminal, a first differential output signal is output to the first output terminal, and a second differential output signal is output to the second output terminal.
[0006] The pulse width modulation (PWM) circuit includes a first input terminal, a second input terminal, a sawtooth input terminal, a first output terminal, and a second output terminal. The first input terminal of the PWM circuit is coupled to the first output terminal of a preamplifier, and the second input terminal is coupled to the second output terminal of the preamplifier. The sawtooth input terminal of the PWM circuit receives a sawtooth wave signal. The PWM circuit compares a first differential output signal with the sawtooth wave signal to output a first PWM signal from the first output terminal. The PWM circuit compares a second differential output signal with the sawtooth wave signal to output a second PWM signal from the second output terminal.
[0007] The power amplifier stage includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the power amplifier stage is coupled to the first output terminal of the pulse width modulation (PWM) circuit, and the second input terminal of the power amplifier stage is coupled to the second output terminal of the PWM circuit. The power amplifier stage uses a first operating voltage, which is different from the operating voltage of the preamplifier. The first output terminal of the power amplifier stage outputs a first drive signal based on the magnitude of the first operating voltage and the first PWM signal. The second output terminal of the power amplifier stage outputs a second drive signal based on the magnitude of the first operating voltage and the second PWM signal.
[0008] The feedback circuit is coupled between the first output terminal of the subsequent driver circuit and the first input terminal of the preamplifier, and also coupled between the second output terminal of the subsequent driver circuit and the second input terminal of the preamplifier, to feed back the first drive signal to the first input terminal of the preamplifier and the second drive signal to the second input terminal of the preamplifier. The common-mode voltage adjustment circuit is coupled between the first and second input terminals of the preamplifier, and adjusts the common-mode voltage between the first and second input terminals of the preamplifier based on the logic voltages of the first drive signal output from the first output terminal of the subsequent driver circuit and the second drive signal output from the second output terminal of the subsequent driver circuit.
[0009] Another embodiment of this application provides a common-mode voltage correction method for a Class D amplifier. This method includes: providing a Class D amplifier, wherein the pre-stage driver circuit and the post-stage driver circuit of the Class D amplifier use different operating voltages; configuring a feedback circuit between the input terminal of the pre-stage driver circuit and the output terminal of the post-stage driver circuit of the Class D amplifier; and adjusting a common-mode voltage at the input terminal of the pre-stage driver circuit according to a logic voltage state of the pulse width voltage output at the output terminal of the post-stage driver circuit of the Class D amplifier.
[0010] A preferred embodiment of this application proposes a common-mode voltage correction method for Class D amplifiers. The common-mode voltage adjustment circuit is coupled to the input of the preamplifier and dynamically adjusts the common-mode voltage at the input of the preamplifier based on the logic voltage state of the drive signal output from the subsequent drive circuit. This design effectively eliminates input signal common-mode voltage offset. In traditional Class D amplifiers, the preamplifier and post-amplifier drive circuits typically use different operating voltages, which can lead to a mismatch between the common-mode voltage at the input of the preamplifier and the output of the subsequent stage, resulting in signal distortion. The common-mode voltage adjustment circuit of this invention can actively correct the common-mode voltage offset at the input of the preamplifier based on the real-time output, ensuring that the entire circuit operates at its optimal operating point and significantly improving linearity. Furthermore, in traditional amplifiers, common-mode voltage offset introduces severe distortion at large signal amplitudes. The common-mode voltage adjustment circuit dynamically tracks and adjusts the common-mode voltage, ensuring the preamplifier operates in its optimal region, reducing crossover distortion and noise, and improving the overall signal-to-noise ratio and sound quality.
[0011] To further understand the techniques, methods, and effects of this application, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of this application. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit this application. Attached Figure Description
[0012] The accompanying drawings are provided to enable those skilled in the art to further understand this application and are incorporated in and constitute a part of the specification of this application. The drawings illustrate exemplary embodiments of this application and are used, together with the specification of this application, to explain the principles of this application.
[0013] Figure 1 The diagram shows a circuit block diagram of a Class D amplifier according to a preferred embodiment of this application.
[0014] Figure 2The diagram illustrates the waveforms of the first drive signal OUTP, the second drive signal OUTN, and the common-mode voltage VICM formed by the two of these signals in a Class D amplifier according to a preferred embodiment of this application.
[0015] Figure 3 The flowchart illustrates a common-mode voltage correction method for a Class D amplifier according to a preferred embodiment of this application.
[0016] Symbol Explanation
[0017] 101: Preamplifier; 102: Pulse Width Modulation Circuit; 103: Power Stage Driver Circuit; 104: Feedback Circuit; 105: Common Mode Voltage Adjustment Circuit; R1: First Resistor; R2: Second Resistor; R3: Third Resistor; R4: Fourth Resistor; C1: First Capacitor; C2: Second Capacitor; OP1: First Amplifier; C3: Third Capacitor; C4: Fourth Capacitor; OP2: Second Amplifier; CZ1: First Zero-Point Compensation Capacitor; CZ2: Second Zero-Point Compensation Capacitor; CP1: First Comparator; CP2: Second Comparator; VDF1: First Differential Output Signal; VDF2: Second Differential Output Signal; VSAW: Sawtooth Wave Signal; VOP: First Pulse Width Modulation Signal; VON: Second Pulse Width Modulation Signal Modulation signal; OUTP: First drive signal; OUTN: Second drive signal; Vin+, Vin-: Input signals; VICM: Common-mode voltage; S1: First switch; S2: Second switch; S3: Third switch; S4: Fourth switch; S5: Fifth switch; S6: Sixth switch; RCM1: First common-mode adjustment resistor; RCM2: Second common-mode adjustment resistor; RCM3: Third common-mode adjustment resistor; RCM4: Fourth common-mode adjustment resistor; RCM5: Fifth common-mode adjustment resistor; RCM6: Sixth common-mode adjustment resistor; Vrefp: High common-mode voltage; Vrefn: Low common-mode voltage; S301-S304: Flow steps of a common-mode voltage correction method for a Class D amplifier according to a preferred embodiment of this application. Detailed Implementation
[0018] Reference will now be made in detail to exemplary embodiments of this application, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and description to refer to the same or similar parts. Furthermore, the practices of these exemplary embodiments are merely one way of implementing the design concept of this application, and the following examples are not intended to limit this application.
[0019] Figure 1 The diagram illustrates a circuit block diagram of a Class D amplifier according to a preferred embodiment of this application. Please refer to... Figure 1This Class D amplifier includes a preamplifier 101, a pulse width modulation circuit 102, a post-amplifier drive circuit 103, a feedback circuit 104, and a common-mode voltage adjustment circuit 105. The preamplifier 101 consists of two stages of integrating circuits. The first integrating circuit consists of a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a first amplifier OP1. The second integrating circuit consists of a third resistor R3, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, and a second amplifier OP2. These first and second integrating circuits are primarily used for low-pass filtering. Additionally, two capacitors are coupled between the first and second integrating circuits: a first zero-point compensation capacitor CZ1 and a second zero-point compensation capacitor CZ2, used to compensate for the zero points of the first and second integrating circuits.
[0020] In this embodiment, the pulse width modulation circuit 102 is implemented using two comparators. The first input of the first comparator CP1 receives the first differential output signal VDF1 from the preamplifier, and the second input receives the sawtooth wave signal VSAW. The first comparator CP1 compares the first differential output signal VDF1 with the sawtooth wave signal VSAW to output the first pulse width modulation signal VOP. The first input of the second comparator CP2 receives the second differential output signal VDF2 from the preamplifier, and the second input receives the sawtooth wave signal VSAW. The second comparator CP2 compares the first differential output signal VDF1 with the sawtooth wave signal VSAW to output the second pulse width modulation signal VON.
[0021] The post-stage drive circuit 103 consists of two drivers. Since the post-stage drive circuit 103 is used to drive the load, its operating voltage will differ from that of the preamplifier 101 and the pulse width modulation circuit 102. For example, the preamplifier 101 and the pulse width modulation circuit 102 will use 5V as their operating voltage VDD1, while the post-stage drive circuit 103 may use 30V as its operating voltage VDD2. The post-stage drive circuit 103 converts the first pulse width modulation signal VOP into a first drive signal OUTP to drive the load, and converts the second pulse width modulation signal VON into a second drive signal OUTN to drive the load.
[0022] Feedback circuit 104 is coupled between the two outputs of the subsequent drive circuit 103 and the preamplifier 101, and is used to feed back the first drive signal OUTP and the second drive signal OUTN to the positive and negative inputs of the preamplifier, respectively. In this embodiment, since the amplitudes of the first drive signal OUTP and the second drive signal OUTN are around 30V, the fed-back signals will have a significant impact on the common-mode voltage at the input of the preamplifier, and will also affect the dynamic range of the input signals Vin+ and Vin-, causing input distortion. However, if this feedback is not performed, the power supply rejection ratio (PSRR) and signal-to-noise distortion ratio (SNDR) will decrease, and the noise in the subsequent operating voltage VDD2 will not be able to suppress the impact on the output.
[0023] In this embodiment, an additional common-mode voltage adjustment circuit 105 is added. This common-mode voltage adjustment circuit 105 is coupled to the first and second input terminals of the preamplifier and is used to adaptively adjust the common-mode voltage at the two input terminals.
[0024] Figure 2 The diagram illustrates the waveforms of the first drive signal OUTP, the second drive signal OUTN, and the common-mode voltage VICM formed by the two signals of a Class D amplifier according to a preferred embodiment of this application. Please refer to... Figure 2 As shown in this diagram, when both the first drive signal OUTP and the second drive signal OUTN are logic low, the common-mode voltage VICM will remain at a low voltage; when one of the first drive signal OUTP and the second drive signal OUTN is logic high and the other is logic low, the common-mode voltage VICM will remain at a medium voltage; when both the first drive signal OUTP and the second drive signal OUTN are logic high, the common-mode voltage VICM will remain at a high voltage.
[0025] Please refer back to this. Figure 1In this embodiment, the common-mode voltage adjustment circuit 105 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a first common-mode adjustment resistor RCM1, a second common-mode adjustment resistor RCM2, a third common-mode adjustment resistor RCM3, a fourth common-mode adjustment resistor RCM4, a fifth common-mode adjustment resistor RCM5, and a sixth common-mode adjustment resistor RCM6. The first terminals of the first switch S1 and the fourth switch S4 are both coupled to a high common-mode voltage Vrefp, and the first terminals of the second switch S2, the third switch S3, the fifth switch S5, and the sixth switch S6 are all coupled to a low common-mode voltage Vrefn. The first common-mode adjustment resistor RCM1, the second common-mode adjustment resistor RCM2, and the third common-mode adjustment resistor RCM3 are respectively coupled between the second terminals of the first switch S1, the second switch S2, and the third switch S3 and the positive input terminal of the first amplifier OP1. The fourth common-mode adjustment resistor RCM4, the fifth common-mode adjustment resistor RCM5, and the sixth common-mode adjustment resistor RCM6 are respectively coupled between the second terminals of the fourth switch S4, the fifth switch S5, and the sixth switch S6 and the negative input terminal of the first amplifier OP1.
[0026]
[0027] Table 1
[0028] Table 1 above represents the truth table for the switch operation, where 1 indicates the switch is on and 0 indicates the switch is off. It can be seen that when both the first pulse width modulation signal VOP and the second pulse width modulation signal VON are logic low, it means that both the first drive signal OUTP and the second drive signal OUTN are low. This will result in an excessively low common-mode voltage VICM. Therefore, a high common-mode voltage Vrefp is used to compensate for the voltage at the positive and negative input terminals of the first amplifier OP1.
[0029] When the first pulse width modulation signal VOP and the second pulse width modulation signal VON are one logic low voltage and the other logic high voltage, it means that one of the first drive signal OUTP and the second drive signal OUTN is low voltage. At this time, since there is only one 30V feedback, the positive input terminal of the first amplifier OP1 is only electrically connected to the low common-mode voltage Vrefn through the second switch S2 and the second common-mode adjustment resistor RCM2. Similarly, the negative input terminal of the first amplifier OP1 is only electrically connected to the low common-mode voltage Vrefn through the fifth switch S5 and the fifth common-mode adjustment resistor RCM5.
[0030] When both the first pulse width modulation signal VOP and the second pulse width modulation signal VON are logic high, it indicates that both the first drive signal OUTP and the second drive signal OUTN are high. At this time, since there are two 30V feedbacks, the positive input terminal of the first amplifier OP1 is electrically connected to the low common-mode voltage Vrefn in parallel through the second switch S2, the third switch S3, and the second common-mode adjustment resistor RCM2 and the third common-mode adjustment resistor RCM3. Similarly, the negative input terminal of the first amplifier OP1 is electrically connected to the low common-mode voltage Vrefn in parallel through the fifth switch S5, the sixth switch S6, and the fifth common-mode adjustment resistor RCM5 and the sixth common-mode adjustment resistor RCM6.
[0031] In the above embodiments, although the common-mode voltage adjustment circuit 105 is implemented using the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the first common-mode adjustment resistor RCM1, the second common-mode adjustment resistor RCM2, the third common-mode adjustment resistor RCM3, the fourth common-mode adjustment resistor RCM4, the fifth common-mode adjustment resistor RCM5, and the sixth common-mode adjustment resistor RCM6, those skilled in the art should understand that other methods for adjusting the common-mode voltage, such as adjustable voltage sources, adjustable current sources, and resistors, can also be used as embodiments, and this application is not limited thereto. Furthermore, zero-point compensation between integrators can be implemented in other ways or without compensation, and this application is not limited thereto. Other implementations of the preamplifier, pulse width modulation circuit, etc., are available to those skilled in the art and will not be described in detail here. Modifications are possible without departing from the spirit of this application, therefore this application is not limited thereto.
[0032] Based on the above embodiments, a common-mode voltage correction method for a Class D amplifier can be summarized. Figure 3 The flowchart illustrates a common-mode voltage correction method for a Class D amplifier according to a preferred embodiment of this application. Please refer to... Figure 3 The common-mode voltage correction method for this Class D amplifier includes the following steps:
[0033] Step S301: Begin.
[0034] Step S302: Provide a Class D amplifier, wherein the pre-stage drive circuit and the post-stage drive circuit of the Class D amplifier use different operating voltages.
[0035] Step S303: Configure a feedback circuit between the input terminal of the pre-stage driver circuit of the Class D amplifier and the output terminal of the post-stage driver circuit of the Class D amplifier.
[0036] Step S304: Based on a logic voltage state of the pulse width voltage output by the output terminal of the Class D amplifier's subsequent driver circuit, adjust the common-mode voltage at the input terminal of the preceding driver circuit. As in the above embodiment, when both the first and second output terminals of the Class D amplifier's subsequent driver circuit are logic high, adjust the common-mode voltage at the first and second input terminals of the preceding driver circuit to a minimum common-mode voltage; when one output terminal and the other output terminal of the Class D amplifier's subsequent driver circuit are logic high and the other logic low, adjust the common-mode voltage at the first and second input terminals of the preceding driver circuit to a median common-mode voltage; when both the first and second output terminals of the Class D amplifier's subsequent driver circuit are logic low, adjust the common-mode voltage at the first and second input terminals of the preceding driver circuit to a maximum common-mode voltage.
[0037] In summary, a preferred embodiment of this application proposes a common-mode voltage correction method for Class D amplifiers. The common-mode voltage adjustment circuit is coupled to the input of the preamplifier and dynamically adjusts the common-mode voltage at the input of the preamplifier based on the logic voltage state of the drive signal output from the subsequent drive circuit. This design effectively eliminates input signal common-mode voltage offset. In traditional Class D amplifiers, the preamplifier and post-amplifier drive circuits typically use different operating voltages, which can lead to a mismatch between the common-mode voltage at the input of the preamplifier and the output of the post-amplifier, resulting in signal distortion. The common-mode voltage adjustment circuit of this invention can actively correct the common-mode voltage offset at the input of the preamplifier based on real-time output conditions, ensuring the entire circuit operates at its optimal operating point and significantly improving linearity. Furthermore, in traditional amplifiers, common-mode voltage offset introduces severe distortion at large signal amplitudes. The common-mode voltage adjustment circuit dynamically tracks and adjusts the common-mode voltage, ensuring the preamplifier operates in its optimal region, reducing crossover distortion and noise, and improving the overall signal-to-noise ratio and sound quality.
[0038] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.
Claims
1. A Class D amplifier, characterized in that, include: A preamplifier includes a first input terminal, a first output terminal, a second input terminal, and a second output terminal. The first input terminal of the preamplifier receives a first differential input signal, the second input terminal of the preamplifier receives a second differential input signal, the first output terminal of the preamplifier outputs a first differential output signal, and the second output terminal of the preamplifier outputs a second differential output signal. A pulse width modulation (PWM) circuit includes a first input terminal, a second input terminal, a sawtooth input terminal, a first output terminal, and a second output terminal. The first input terminal of the PWM circuit is coupled to the first output terminal of a preamplifier, and the second input terminal of the PWM circuit is coupled to the second output terminal of the preamplifier. The sawtooth input terminal of the PWM circuit receives a sawtooth wave signal. The PWM circuit compares the first differential output signal with the sawtooth wave signal to output a first PWM signal from the first output terminal. The PWM circuit compares the second differential output signal with the sawtooth wave signal to output a second PWM signal from the second output terminal. A power amplifier stage includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the power amplifier stage is coupled to the first output terminal of the pulse width modulation (PWM) circuit, and the second input terminal of the power amplifier stage is coupled to the second output terminal of the PWM circuit. The power amplifier stage employs a first operating voltage, which is different from the operating voltage of the preamplifier. The first output terminal of the power amplifier stage outputs a first drive signal based on the magnitude of the first operating voltage and the first PWM signal. The second output terminal of the power amplifier stage outputs a second drive signal based on the magnitude of the first operating voltage and the second PWM signal. A feedback circuit, coupled between the first output terminal of the subsequent drive circuit and the first input terminal of the preamplifier, and coupled between the second output terminal of the subsequent drive circuit and the second input terminal of the preamplifier, is used to feed back the first drive signal to the first input terminal of the preamplifier and to feed back the second drive signal to the second input terminal of the preamplifier; and A common-mode voltage adjustment circuit is coupled to the first input terminal and the second input terminal of the preamplifier. The common-mode voltage of the first input terminal and the second input terminal of the preamplifier is adjusted according to the logic voltage of the first drive signal output from the first output terminal and the second drive signal output from the second output terminal of the post-stage drive circuit.
2. The Class D amplifier as described in claim 1, characterized in that, The preamplifier includes: A first integrating circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal of the first integrating circuit receives a first differential input signal, and the second input terminal of the first integrating circuit receives a second differential input signal; and A second integrator circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the second integrator circuit is coupled to the second output terminal of the first integrator circuit, the second input terminal of the second integrator circuit is coupled to the first output terminal of the first integrator circuit, the first output terminal of the second integrator circuit is coupled to the first output terminal of the pulse width modulation circuit, and the second input terminal of the second integrator circuit is coupled to the second output terminal of the pulse width modulation circuit.
3. The Class D amplifier as described in claim 2, characterized in that, The preamplifier also includes: A first zero-point compensation capacitor includes a first terminal and a second terminal, wherein the first terminal of the first zero-point compensation capacitor is coupled to the second output terminal of the first integrator circuit, and the second terminal of the first zero-point compensation capacitor is coupled to the first input terminal of the second integrator circuit; and A second zero-point compensation capacitor includes a first terminal and a second terminal, wherein the first terminal of the second zero-point compensation capacitor is coupled to the first output terminal of the first integrator circuit, and the second terminal of the first zero-point compensation capacitor is coupled to the second input terminal of the second integrator circuit.
4. The Class D amplifier as described in claim 2, characterized in that, The first integrating circuit further includes: A first resistor includes a first terminal and a second terminal, wherein the first terminal of the first resistor receives the first differential input signal, and the second terminal of the first resistor is coupled to the first input terminal of the preamplifier. A second resistor includes a first terminal and a second terminal, wherein the first terminal of the second resistor receives the second differential input signal, and the second terminal of the second resistor is coupled to the second input terminal of the preamplifier; A first amplifier includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal of the first amplifier is coupled to the second terminal of the first resistor, and the second input terminal of the first amplifier is coupled to the second terminal of the second resistor. A first capacitor includes a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to a first input terminal of the first amplifier, and the second terminal of the first capacitor is coupled to a second output terminal of the first amplifier; and A second capacitor includes a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the second input terminal of the first amplifier, and the second terminal of the first capacitor is coupled to the first output terminal of the first amplifier.
5. The Class D amplifier as described in claim 2, characterized in that, The second integrating circuit also includes: A third resistor includes a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the second output terminal of the first integrator circuit; A fourth resistor includes a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the first output terminal of the first integrating circuit; A second amplifier includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal of the second amplifier is coupled to the second terminal of the third resistor, and the second input terminal of the second amplifier is coupled to the second terminal of the fourth resistor. A third capacitor includes a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to a first input terminal of the second amplifier, and the second terminal of the third capacitor is coupled to a second output terminal of the second amplifier; and A fourth capacitor includes a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the second input terminal of the second amplifier, and the second terminal of the fourth capacitor is coupled to the first output terminal of the second amplifier.
6. The Class D amplifier as described in claim 1, characterized in that, The pulse width modulation circuit includes: A first comparator includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first comparator is coupled to the first output terminal of the preamplifier, the second input terminal of the first comparator receives the sawtooth wave signal, and the output terminal of the first comparator outputs the first pulse width modulation signal; and A second comparator includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second comparator is coupled to the second output terminal of the preamplifier, the second input terminal of the second comparator receives the sawtooth wave signal, and the output terminal of the second comparator outputs the second pulse width modulation signal.
7. The Class D amplifier as described in claim 1, characterized in that, The common-mode voltage adjustment circuit includes: A first switch includes a first terminal and a second terminal, wherein the first terminal of the first switch is coupled to a high common-mode voltage; A second switch includes a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to a low common-mode voltage; A third switch includes a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the low common-mode voltage; A fourth switch includes a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the high common-mode voltage; A fifth switch includes a first terminal and a second terminal, wherein the first terminal of the fifth switch is coupled to the low common-mode voltage; A sixth switch includes a first terminal and a second terminal, wherein the first terminal of the sixth switch is coupled to the low common-mode voltage; A first common-mode adjustment resistor includes a first terminal and a second terminal, wherein the first terminal of the first common-mode adjustment resistor is coupled to the second terminal of the first switch, and the second terminal of the first common-mode adjustment resistor is coupled to the first input terminal of the preamplifier. A second common-mode adjustment resistor includes a first terminal and a second terminal, wherein the first terminal of the second common-mode adjustment resistor is coupled to the second terminal of the second switch, and the second terminal of the second common-mode adjustment resistor is coupled to the first input terminal of the preamplifier. A third common-mode adjustment resistor includes a first terminal and a second terminal, wherein the first terminal of the third common-mode adjustment resistor is coupled to the second terminal of the third switch, and the second terminal of the third common-mode adjustment resistor is coupled to the first input terminal of the preamplifier. A fourth common-mode adjustment resistor includes a first terminal and a second terminal, wherein the first terminal of the fourth common-mode adjustment resistor is coupled to the second terminal of the fourth switch, and the second terminal of the fourth common-mode adjustment resistor is coupled to the second input terminal of the preamplifier. A fifth common-mode adjustment resistor includes a first terminal and a second terminal, wherein the first terminal of the fifth common-mode adjustment resistor is coupled to the second terminal of the fifth switch, and the second terminal of the fifth common-mode adjustment resistor is coupled to the second input terminal of the preamplifier; and A sixth common-mode adjustment resistor includes a first terminal and a second terminal, wherein the first terminal of the sixth common-mode adjustment resistor is coupled to the second terminal of the sixth switch, and the second terminal of the sixth common-mode adjustment resistor is coupled to the second input terminal of the preamplifier. Specifically, when the voltages at the first and second output terminals of the Class D amplifier's subsequent drive circuit are both logic high, the second switch, the third switch, the fifth switch, and the sixth switch are turned on. When the voltage at the first output terminal of the Class D amplifier's subsequent drive circuit is logic high and the voltage at the second output terminal of the Class D amplifier's subsequent drive circuit is logic low, the second switch and the fifth switch are turned on. When the voltage at the first output terminal of the Class D amplifier's subsequent drive circuit is logic low and the voltage at the second output terminal of the Class D amplifier's subsequent drive circuit is logic high, the second switch and the fifth switch are turned on; and When the voltages at the first and second output terminals of the Class D amplifier's subsequent drive circuit are both logic low, the first and third switches are turned on.
8. A common-mode voltage correction method for a Class D amplifier, characterized in that, include: A Class D amplifier is provided, wherein the pre-stage drive circuit and the post-stage drive circuit of the Class D amplifier use different operating voltages; A feedback circuit is configured between the input terminal of the pre-stage driver circuit of the Class D amplifier and the output terminal of the post-stage driver circuit of the Class D amplifier; and Based on a logic voltage state of the pulse width voltage output by the output terminal of the Class D amplifier's subsequent driver circuit, adjust a common-mode voltage at the input terminal of the preceding driver circuit.
9. The common-mode voltage correction method for a Class D amplifier as described in claim 8, characterized in that, The Class D amplifier is a differential amplifier, and the pre-stage driver circuit of the Class D amplifier includes a first input terminal and a second input terminal, and the post-stage driver circuit of the Class D amplifier includes a first output terminal and a second output terminal. The adjustment of the common-mode voltage at the input of the preceding drive circuit, based on the logic voltage state of the pulse width voltage output from the output of the subsequent drive circuit of the Class D amplifier, includes: When the voltages at both the first and second output terminals of the Class D amplifier's subsequent drive circuit are logic high, the common-mode voltage at the first and second input terminals of the preceding drive circuit is adjusted to a minimum common-mode voltage. When the voltage at the first output terminal of the Class D amplifier's subsequent drive circuit is logic high and the voltage at the second output terminal of the Class D amplifier's subsequent drive circuit is logic low, the common-mode voltage at the first and second input terminals of the preceding drive circuit is adjusted to a median common-mode voltage. When the voltage at the first output terminal of the Class D amplifier's subsequent driver circuit is logic low and the voltage at the second output terminal of the Class D amplifier's subsequent driver circuit is logic high, the common-mode voltage at the first and second input terminals of the preceding driver circuit is adjusted to the median common-mode voltage; and When the voltages at both the first and second output terminals of the Class D amplifier's subsequent drive circuit are logic low, the common-mode voltage at the first and second input terminals of the preceding drive circuit is adjusted to a maximum common-mode voltage.