Epitaxial wafer and preparation method thereof
By adding a capping layer process step and optimizing process parameters during epitaxial wafer fabrication, the problem of excessively wide SRP transition region in epitaxial layers under normal pressure was solved, achieving high-quality fabrication of epitaxial wafers and improving the electrical and mechanical properties of devices.
Patent Information
- Application Number
- CN202511687258.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-17
- Publication Date
- 2026-02-13
AI Technical Summary
When epitaxial wafers are fabricated under normal pressure, the SRP transition region of the epitaxial layer is too wide, resulting in unsatisfactory electrical performance of the device.
By adding a deposition capping layer process step during the epitaxial wafer fabrication process, and combining it with the previous baking process, controlling the temperature difference between the baking and deposition processes, using specific flow rates of hydrogen, silicon source, and doping source, and optimizing process parameters such as time and temperature, the self-doping effect can be suppressed.
It effectively suppresses the self-doping effect of the epitaxial layer, keeps the SRP transition region at an ideal width, improves device performance, and enhances the electrical and mechanical properties of the epitaxial wafer.
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Figure CN121519174A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor manufacturing technology, specifically relating to an epitaxial wafer and its preparation method. Background Technology
[0002] In the semiconductor industry, BCD (Bipolar Discrete Coaxial) technology is a monolithic integration technology that allows the fabrication of Bipolar Transistors (BPTs), CMOS (Complementary Metal-Oxide-Semiconductor), and DMOS (Double-Diffused Metal-Oxide-Semiconductor) devices on the same chip. The core of this technology lies in combining devices with different performance characteristics, leveraging their respective strengths to improve efficiency, reduce power consumption, save costs, and enhance reliability. It is one of the mainstream processes for analog integrated circuits.
[0003] In some BCD semiconductor fabrication processes, elements such as Sb or P are implanted into the lightly doped substrate surface. To avoid the influence of self-doping on the epitaxial layer, production is generally carried out in a reduced-pressure epitaxial furnace. However, epitaxial wafer fabrication under low-pressure conditions is less efficient and more expensive, and its production capacity can no longer meet industry demands. On the other hand, epitaxial wafer fabrication under ambient pressure conditions results in a wider SRP (spreading resistance profile) transition region due to substrate self-doping, leading to a decrease in epitaxial wafer quality.
[0004] Therefore, how to improve the process of preparing epitaxial wafers under normal pressure, thereby improving the SRP performance of the epitaxial layer, is a problem that needs to be solved. Summary of the Invention
[0005] This application provides an epitaxial wafer and its preparation method, aiming to solve the problem that the existing method of preparing epitaxial wafers under normal pressure conditions results in an excessively wide SRP transition region in the epitaxial layer, leading to unsatisfactory electrical performance of the device.
[0006] On the one hand, this application provides a method for preparing an epitaxial wafer, comprising the following steps: A substrate is provided, the substrate is placed in an epitaxial furnace, hydrogen gas is introduced, and the substrate is baked. The first cooling process involves introducing a silicon source and a doping source to deposit a capping layer on the substrate surface. A second cooling process is performed to grow an epitaxial layer on the surface of the capping layer.
[0007] In some embodiments, the baking time is t1, the deposition time of the capping layer is t2, and the growth time of the epitaxial layer is t3, satisfying: 190s≤t1≤210s.
[0008] In some embodiments, 26s≤t2≤30s.
[0009] In some embodiments, 170s≤t3≤200s.
[0010] In some embodiments, during the step of baking the substrate, the hydrogen gas has a first flow rate Q1; In the step of depositing a capping layer on the substrate surface, the hydrogen gas has a second flow rate Q2; In the step of growing an epitaxial layer on the surface of the capping layer, the hydrogen gas has a third flow rate Q3; It satisfies: Q1≥Q2 and Q1≥Q3.
[0011] In some embodiments, the first flow rate Q1 satisfies: 80000sccm≤Q1≤100000sccm.
[0012] In some embodiments, the second flow rate Q2 satisfies: 40000sccm≤Q2≤60000sccm.
[0013] In some embodiments, the third flow rate Q3 satisfies: 40000sccm≤Q3≤60000sccm.
[0014] In some embodiments, during the step of depositing a capping layer on the substrate surface, the silicon source has a fourth flow rate Q4, and the doping source has a fifth flow rate Q5; In the step of growing an epitaxial layer on the surface of the capping layer, the silicon source has a sixth flow rate Q6, and the doping source has a seventh flow rate Q7; It satisfies: Q4≤Q6 and Q5≥Q7.
[0015] In some embodiments, the fourth flow Q4 and the fifth flow Q5 satisfy Q4:Q5=2:5.
[0016] In some embodiments, the fourth flow rate Q4 satisfies: 1000sccm≤Q4≤3000sccm.
[0017] In some embodiments, the fifth flow rate Q5 satisfies: 270sccm≤Q5≤330sccm.
[0018] In some embodiments, the sixth flow rate Q6 satisfies: 4000sccm≤Q6≤6000sccm.
[0019] In some embodiments, the seventh flow rate Q7 satisfies: 225sccm≤Q7≤275sccm.
[0020] In some embodiments, the baking temperature is 1150~1180℃.
[0021] In some embodiments, the temperature of the deposited capping layer is 1100~1120°C.
[0022] In some embodiments, the temperature at which the epitaxial layer is grown is 1100~1120°C.
[0023] In some embodiments, the silicon source is trichlorosilane, and the doping source is borane.
[0024] This application also provides an epitaxial wafer, which is prepared using the above-described method for preparing an epitaxial wafer.
[0025] In some embodiments, the epitaxial wafer includes a substrate layer, a capping layer, and an epitaxial layer, wherein the capping layer and the epitaxial layer are arranged sequentially in a direction away from the substrate layer; the total thickness of the capping layer and the epitaxial layer is 4.6~5.4 μm.
[0026] In some embodiments, the thickness of the cover layer is 0.325~0.375μm.
[0027] In some embodiments, the thickness of the epitaxial layer is 4.273~5.027 μm.
[0028] In some embodiments, the resistivity of the cover layer is 1.0~1.5 Ohm·cm.
[0029] In some embodiments, the width of the SRP transition region of the epitaxial wafer is 1.4~2.4 μm.
[0030] The epitaxial wafer fabrication method provided in this application includes the following steps: providing a substrate, placing the substrate in an epitaxial furnace, introducing hydrogen gas, and baking the substrate; performing a first cooling process, introducing a silicon source and a dopant source, and depositing a capping layer on the substrate surface; performing a second cooling process, and growing an epitaxial layer on the capping layer surface. The epitaxial wafer fabrication method provided in this application, by adding a capping layer deposition step combined with the preceding baking process, can effectively suppress the self-doping effect of the epitaxial layer; simultaneously, controlling the temperature difference between the baking and deposition processes can further suppress the self-doping effect, thereby maintaining the SRP transition region of the epitaxial wafer at an ideal width and improving device performance. Attached Figure Description
[0031] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0032] Figure 1 The diagram shows the SRP test results of the epitaxial wafers provided in Examples 1-3 and Comparative Example 1 of this application; Figure 2 These are the SRP test results of the epitaxial wafers provided in Examples 4-5 of this application; Figure 3 The diagram shows the SRP test results of the epitaxial wafers provided in Embodiment 1 and Comparative Examples 3-4 of this application. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for mutual communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. In the description of this application, "multiple" means two or more, unless otherwise expressly and specifically limited. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features.
[0035] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure of this application, the components and arrangements of specific examples are described below. Of course, these are merely examples and are not intended to limit this application.
[0036] The first embodiment of this application discloses a method for preparing an epitaxial wafer, comprising the following steps: A substrate is provided, which is placed in an epitaxial furnace and hydrogen gas is introduced to bake the substrate. The first cooling process involves introducing a silicon source and a doping source to deposit a capping layer on the substrate surface. A second cooling process is performed to grow an epitaxial layer on the surface of the capping layer.
[0037] It is understandable that by adding a deposition capping layer process step, combined with the previous baking process, the self-doping effect of the epitaxial layer can be effectively suppressed. At the same time, controlling the temperature difference between the baking process and the deposition process can also further suppress the self-doping effect, thereby keeping the SRP transition region of the epitaxial wafer at an ideal width and improving device performance.
[0038] In some embodiments, the baking time is t1, the deposition time of the capping layer is t2, and the growth time of the epitaxial layer is t3, satisfying: 190s≤t1≤210s.
[0039] It is understandable that the baking time t1 (in seconds) can be any value from 190, 195, 200, 205, 210, or any value within a range of two. When t1 meets the above range, it can ensure that the introduced hydrogen gas can fully remove contaminants and oxides from the substrate surface, while avoiding excessive diffusion of substrate impurities due to excessive baking time.
[0040] In some embodiments, 26s≤t2≤30s.
[0041] It is understandable that the deposition time t2 (in seconds) can be any value from 26, 27, 28, 29, and 30, or any value within a range of any two values. When t2 meets the above range, it can ensure that the capping layer has an ideal thickness, thereby effectively suppressing the self-doping effect of the epitaxial layer.
[0042] In some embodiments, 170s≤t3≤200s.
[0043] It is understandable that the value of the epitaxial layer growth time t3 (in seconds) can be any value from 170, 175, 180, 185, 190, 195, 200, or a value within any two of these ranges. When t3 meets the above value range, it can ensure that the epitaxial layer grows sufficiently, while avoiding performance defects caused by excessive epitaxial layer growth time.
[0044] In some embodiments, during the substrate baking step, hydrogen gas has a first flow rate Q1; In the step of depositing a capping layer on the substrate surface, hydrogen gas has a second flow rate Q2; In the step of growing an epitaxial layer on the surface of the capping layer, hydrogen has a third flow rate Q3; It satisfies: Q1≥Q2 and Q1≥Q3.
[0045] Understandably, during the baking stage, a higher flow rate of hydrogen can quickly remove impurities and reaction byproducts desorbed from the substrate surface, reducing impurity residue and thus reducing the self-doping effect during subsequent epitaxial layer growth, ensuring that the SRP transition region of the epitaxial wafer remains at the ideal width. On the other hand, reducing the hydrogen flow rate during the deposition of the capping layer and the growth of the epitaxial layer can stabilize the reaction atmosphere, avoid uneven film deposition caused by high flow rate airflow, and ensure the structural integrity of the capping layer and the epitaxial layer.
[0046] In some embodiments, the first flow rate Q1, the second flow rate Q2, and the third flow rate Q3 further satisfy: 80000sccm≤Q1≤100000sccm.
[0047] It is understandable that the value of Q1 (unit: sccm) can be any value among 80000, 85000, 90000, 95000, 100000 or any value within the range of any two values.
[0048] In some embodiments, 40000sccm≤Q2≤60000sccm.
[0049] It is understandable that the value of Q2 (unit: sccm) can be any value among 40000, 45000, 50000, 55000, and 60000, or a value within the range of any two values.
[0050] In some embodiments, 40000sccm≤Q3≤60000sccm.
[0051] It is understood that the value of Q3 (unit: sccm) can be any value among 40000, 45000, 50000, 55000, and 60000, or a value within any range of two values. When the first flow rate Q1, the second flow rate Q2, and the third flow rate Q3 meet the above value range, it can further reduce the impurity retention on the substrate surface, ensure the structural integrity of the capping layer and the epitaxial layer, and ensure that the SRP transition region of the epitaxial wafer is maintained at the ideal width.
[0052] Based on the above embodiments, it is further preferred that Q2=Q3. When Q2=Q3, the hydrogen flow rate during the deposition of the capping layer and the growth of the epitaxial layer remains constant, which can further stabilize the reaction atmosphere, ensure the thickness uniformity of the capping layer and the epitaxial layer, and reduce the width of the SRP transition region of the epitaxial wafer.
[0053] In some embodiments, during the step of depositing a capping layer on the substrate surface, the silicon source has a fourth flow rate Q4 and the doping source has a fifth flow rate Q5; In the step of growing an epitaxial layer on the surface of the capping layer, the silicon source has a sixth flow rate Q6 and the doping source has a seventh flow rate Q7. It satisfies: Q4≤Q6 and Q5≥Q7.
[0054] Understandably, during the capping layer deposition stage, the silicon source flow rate is relatively low, which allows for precise control of the capping layer growth rate, while the doping source flow rate is relatively high, which enables the formation of a highly doped capping layer and enhances the impurity blocking effect. During the epitaxial layer growth stage, the proportion of the doping source flow rate is reduced, which allows for more effective matching of the doping concentration required by the device, achieving precise doping and improving the quality of the epitaxial wafer.
[0055] In some embodiments, the fourth flow Q4 and the fifth flow Q5 satisfy Q4:Q5=2:5.
[0056] It is understandable that when the fourth flow rate Q4 and the fifth flow rate Q5 satisfy the above ratio, the doping concentration and crystal quality of the capping layer can be effectively controlled, so that the capping layer has both a good physical barrier structure and can optimize the interfacial bonding force with the substrate and epitaxial layer through a specific doping ratio, reduce interfacial defects, and further suppress impurity diffusion across the interface.
[0057] In some embodiments, 1000sccm≤Q4≤3000sccm.
[0058] It is understandable that the value of Q4 (unit: sccm) can be any value among 1000, 1500, 2000, 2500, and 3000, or a value within the range of any two values.
[0059] In some embodiments, 270sccm≤Q5≤330sccm.
[0060] It is understandable that the value of Q5 (unit: sccm) can be any value among 270, 280, 290, 300, 310, 320, and 330, or a value within a range of any two values.
[0061] In some embodiments, 4000sccm≤Q6≤6000sccm.
[0062] It is understandable that the value of Q6 (unit: sccm) can be any value among 4000, 4500, 5000, 5500, and 6000, or a value within the range of any two values.
[0063] In some embodiments, 225sccm≤Q7≤275sccm.
[0064] It is understandable that the value of Q7 (unit: sccm) can be any value among 225, 240, 250, 260, and 275, or a value within any two of these ranges. When the fourth flow rate Q4, the fifth flow rate Q5, the sixth flow rate Q6, and the seventh flow rate Q7 meet the above value range, it can further ensure the formation of a highly doped capping layer, enhance the impurity blocking effect, and simultaneously achieve precise doping of the epitaxial layer, keeping the SRP transition region of the epitaxial wafer at an ideal width.
[0065] In some embodiments, the baking temperature is 1150~1180℃.
[0066] It is understood that the baking temperature (unit: °C) can be any value from 1150, 1155, 1160, 1165, 1170, 1175, 1180, or any value within a range of two. When the baking temperature meets the above range, it can effectively remove contaminants and the natural oxide layer on the substrate surface, while activating the active sites on the substrate surface.
[0067] In some embodiments, the temperature of the deposited capping layer is 1100~1120°C.
[0068] It is understandable that the temperature of the deposited overburden layer (unit: °C) can be any value among 1100, 1104, 1108, 1112, 1116, and 1120, or a value within a range of any two values.
[0069] In some embodiments, the temperature for growing the epitaxial layer is 1100~1120°C.
[0070] It is understandable that the temperature for growing the epitaxial layer (unit: °C) can be any value from 1100, 1104, 1108, 1112, 1116, 1120, or any value within a range of any two. When the temperatures of the deposited capping layer and the grown epitaxial layer meet the above-mentioned ranges, it can ensure that the capping layer and the epitaxial layer have reasonable thickness uniformity, while reducing interfacial stress and defects caused by temperature fluctuations in an ideal temperature field.
[0071] In some embodiments, the silicon source is trichlorosilane and the doping source is borane.
[0072] This application also provides an epitaxial wafer, which is prepared using the above-described method for preparing an epitaxial wafer.
[0073] In some embodiments, the epitaxial wafer includes a substrate layer, a capping layer, and an epitaxial layer, wherein the capping layer and the epitaxial layer are arranged sequentially in a direction away from the substrate layer; the total thickness of the capping layer and the epitaxial layer is 4.6~5.4μm.
[0074] It is understood that the total thickness (in μm) of the capping layer and epitaxial layer can be any value from 4.6, 4.7, 4.8, 4.9, 5.0, 5.1, 5.2, 5.3, and 5.4, or a value within any two of these ranges. By controlling the total thickness of the capping layer and epitaxial layer to meet the above-mentioned range, it is possible to ensure that the epitaxial wafer has a relatively ideal thickness to achieve device functionality, while avoiding stress accumulation and warping caused by overgrowth with a reasonable total thickness.
[0075] In some embodiments, the thickness of the cover layer is 0.325~0.375μm.
[0076] It is understood that the thickness of the capping layer (in μm) can be any value from 0.325, 0.335, 0.345, 0.355, 0.365, 0.375, or any value within a range of any two values. By controlling the thickness of the capping layer to meet the above-mentioned range, it is possible to further ensure that the self-doping effect of the epitaxial layer is suppressed during the growth of the epitaxial layer, thereby maintaining the SRP transition region of the epitaxial wafer at an ideal width and improving device performance.
[0077] In some embodiments, the thickness of the epitaxial layer is 4.273~5.027 μm.
[0078] It is understood that the thickness of the epitaxial layer (unit: μm) can be any value from 4.273, 4.410, 4.547, 4.684, 4.821, 4.958, 5.027, or a value within a range of any two values. By controlling the thickness of the epitaxial layer to meet the above-mentioned range, it is possible to further ensure that the epitaxial wafer has good electrical and mechanical properties, while avoiding stress accumulation and warping caused by excessive epitaxial layer thickness, thus ensuring good quality of the epitaxial wafer.
[0079] In some embodiments, the resistivity of the cover layer is 1.0~1.5 Ohm·cm.
[0080] It is understood that the resistivity of the capping layer (unit: Ohm·cm) can be any value from 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, or any value within a range of any two. By controlling the resistivity of the capping layer to meet the above range, the capping layer can possess both good conductivity compatibility and suppress impurity migration through appropriate resistance characteristics. Simultaneously, it can match the resistivity difference between the substrate and the epitaxial layer, reducing interface charge accumulation and thus improving device performance.
[0081] In some embodiments, the width of the SRP transition region of the epitaxial wafer is 1.4~2.4 μm, preferably 1.4~2.0 μm, and more preferably 1.5~1.7 μm.
[0082] It is understandable that the width of the SRP transition region (in μm) can be any value from 1.5, 1.55, 1.6, 1.65, 1.7, or any value within a range of two values. This width range is the preferred range for the ideal operating state of the device, which can avoid problems such as increased on-resistance and slower response speed caused by an excessively wide transition region, significantly improving the device's switching speed, breakdown voltage, and other key electrical performance, and meeting the high-performance requirements of analog integrated circuits.
[0083] The epitaxial wafer and its preparation method provided in this application are described below with reference to specific embodiments: Example 1 This embodiment provides an epitaxial wafer, which is prepared through the following steps: Provide a substrate, place the substrate in an epitaxial furnace, heat it to T1=1160℃, introduce hydrogen gas, control the first flow rate of hydrogen Q1=90000sccm, bake the substrate, and bake the substrate for t1=200s. The temperature was lowered to T2 = 1110℃. The second flow rate of hydrogen was adjusted to Q2 = 50000 sccm. Trichlorosilane and borane were introduced, and the fourth flow rate of trichlorosilane was controlled to Q4 = 2000 sccm and the fifth flow rate of borane to Q5 = 300 sccm. A capping layer was deposited on the substrate surface at a time t2 = 28 s. The capping layer thickness was 0.35 μm. The resistivity of the capping layer was measured and found to be 1.1 Ohm·cm.
[0084] A second cooling process was performed, lowering the temperature to T3 = 1100℃. The third flow rate of hydrogen was adjusted to Q3 = 50000 sccm, the sixth flow rate of trichlorosilane to Q6 = 5000 sccm, and the seventh flow rate of borane to Q7 = 250 sccm. An epitaxial layer was grown on the surface of the capping layer for a growth time of t3 = 185 s, resulting in a thickness of 4.65 μm. SRP tests were performed on the epitaxial layer, and the results are as follows. Figure 1 As shown.
[0085] Examples 1-3 The preparation methods of the epitaxial wafers provided in Examples 1-3 are the same as those in Example 1, except that the baking temperature T1 in the process is adjusted.
[0086] Comparative Example 1 The preparation method of the epitaxial wafer provided in Comparative Example 1 is the same as that in Example 1, except that the baking temperature T1 in the process is adjusted.
[0087] Examples 4-5 The preparation methods of the epitaxial wafers provided in Examples 4 and 5 are the same as those in Example 1, except that the first flow rate Q1 of hydrogen in the baking stage of the process is adjusted.
[0088] Examples 6-7 The preparation methods of the epitaxial wafers provided in Examples 6 and 7 are the same as those in Example 1, except that the baking time t1 in the process is adjusted.
[0089] Comparative Example 2 The preparation method of the epitaxial wafer provided in Comparative Example 2 is the same as that in Example 1, except that the baking time t1 in the process is adjusted.
[0090] Comparative Examples 3-4 The preparation methods of the epitaxial wafers provided in Comparative Examples 3 and 4 are the same as those in Example 1, except that the deposition time t2 of the capping layer in the process is adjusted.
[0091] Example 8 The preparation method of the epitaxial wafer provided in Example 8 is the same as that in Example 1, except that the fifth flow rate Q5 of borane in the deposition capping layer stage of the process is adjusted.
[0092] Comparative Examples 5-6 The preparation methods of the epitaxial wafers provided in Comparative Examples 5 and 6 are the same as those in Example 1, except that the fifth flow rate Q5 of borane in the deposition capping layer stage of the process is adjusted.
[0093] The relevant parameters for Examples 1-8 and Comparative Examples 1-6 are shown in Table 1. SRP tests were performed on the epitaxial wafers obtained in Examples 1-8 and Comparative Examples 1-6, and the results are as follows: Figures 1-3 As shown in Table 1.
[0094] The comparison chart of the SRP test results of the epitaxial wafers provided in Examples 1-3 and Comparative Example 1 is shown below. Figure 1 As shown in the comparison chart of the SRP test results of the epitaxial wafers provided in Examples 4 and 5, the results are as follows: Figure 2 As shown in the figure, the comparison chart of the SRP test results of the epitaxial wafers provided in Example 1 and Comparative Examples 3-4 is as follows. Figure 3 As shown.
[0095] Table 1
[0096] According to Table 1 and Figures 1-3 As can be seen, the epitaxial wafers prepared by the method provided in this application all have relatively good SRP transition region width, and the capping layer has good electrical properties. According to Comparative Examples 1-6, when the baking temperature, baking time, capping layer deposition time, or borane flow rate during capping layer deposition exceeds the range provided in this application, it will cause the SRP transition region of the epitaxial wafer to be too wide or too narrow, and it will also cause the resistance of the capping layer to exceed the ideal range.
[0097] The epitaxial wafer and its preparation method provided in the embodiments of this application have been described in detail above. Specific examples have been used in this application to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for preparing an epitaxial wafer, characterized in that, Includes the following steps: A substrate is provided, the substrate is placed in an epitaxial furnace, hydrogen gas is introduced, and the substrate is baked. The first cooling process involves introducing a silicon source and a doping source to deposit a capping layer on the substrate surface. A second cooling process is performed to grow an epitaxial layer on the surface of the capping layer.
2. The method for preparing an epitaxial wafer according to claim 1, characterized in that, The baking time is t1, the deposition time of the capping layer is t2, and the growth time of the epitaxial layer is t3, satisfying the following: 190s≤t1≤210s; and / or, 26s≤t2≤30s; and / or, 170s≤t3≤200s.
3. The method for preparing an epitaxial wafer according to claim 1, characterized in that, In the step of baking the substrate, the hydrogen gas has a first flow rate Q1; In the step of depositing a capping layer on the substrate surface, the hydrogen gas has a second flow rate Q2; In the step of growing an epitaxial layer on the surface of the capping layer, the hydrogen gas has a third flow rate Q3; It satisfies: Q1≥Q2 and Q1≥Q3.
4. The method for preparing an epitaxial wafer according to claim 3, characterized in that, The first flow rate Q1 satisfies: 80000sccm ≤ Q1 ≤ 100000sccm; and / or, The second flow rate Q2 satisfies: 40000sccm ≤ Q2 ≤ 60000sccm; and / or, The third flow rate Q3 satisfies: 40000sccm≤Q3≤60000sccm.
5. The method for preparing an epitaxial wafer according to claim 1, characterized in that, In the step of depositing a capping layer on the substrate surface, the silicon source has a fourth flow rate Q4, and the doping source has a fifth flow rate Q5; In the step of growing an epitaxial layer on the surface of the capping layer, the silicon source has a sixth flow rate Q6, and the doping source has a seventh flow rate Q7; It satisfies: Q4≤Q6 and Q5≥Q7.
6. The method for preparing an epitaxial wafer according to claim 5, characterized in that, The fourth flow rate Q4 and the fifth flow rate Q5 satisfy Q4:Q5=2:
5.
7. The method for preparing an epitaxial wafer according to claim 5, characterized in that, The fourth flow rate Q4 satisfies: 1000sccm ≤ Q4 ≤ 3000sccm; and / or, The fifth flow rate Q5 satisfies: 270sccm ≤ Q5 ≤ 330sccm; and / or, The sixth flow rate Q6 satisfies: 4000sccm ≤ Q6 ≤ 6000sccm; and / or, The seventh flow rate Q7 satisfies: 225sccm≤Q7≤275sccm.
8. The method for preparing an epitaxial wafer according to claim 1, characterized in that, The baking temperature is 1150~1180℃; and / or, The temperature of the deposited capping layer is 1100~1120℃; and / or, The temperature at which the epitaxial layer is grown is 1100~1120℃.
9. The method for preparing an epitaxial wafer according to claim 1, characterized in that, The silicon source is trichlorosilane, and the doping source is borane.
10. An epitaxial wafer, characterized in that, The epitaxial wafer is prepared by the method described in any one of claims 1 to 9.
11. An epitaxial wafer according to claim 10, characterized in that, The epitaxial wafer includes a substrate layer, a capping layer, and an epitaxial layer, wherein the capping layer and the epitaxial layer are arranged sequentially in a direction away from the substrate layer; the total thickness of the capping layer and the epitaxial layer is 4.6~5.4μm.
12. An epitaxial wafer according to claim 11, characterized in that, The thickness of the covering layer is 0.325~0.375μm; and / or, The thickness of the epitaxial layer is 4.273~5.027μm.
13. An epitaxial wafer according to claim 11, characterized in that, The resistivity of the covering layer is 1.0~1.5 Ohm·cm.
14. An epitaxial wafer according to claim 10, characterized in that, The width of the diffusion resistance distribution transition region of the epitaxial wafer is 1.4~2.4μm.