Integrated circuit schematic diagram automatic generation method for electronic design automation tool chain error detection
By automatically generating diverse integrated circuit schematics and introducing redundant path optimization and input equivalence variant generation, combined with a multi-strategy verification framework, the problem of limited detection effectiveness and coverage caused by the simple circuit structure in the prior art is solved, and efficient defect detection of the EDA toolchain is achieved.
Patent Information
- Application Number
- CN202511693501.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-02-13
AI Technical Summary
In existing integrated circuit design, the circuit schematic structure is simple and cannot cover the boundary conditions of EDA toolchains in the process of analysis, modeling and simulation. Furthermore, the invariance of schematic structure masks the behavioral differences of toolchains under semantic equivalence conditions, which limits the effectiveness and coverage of defect detection.
By automatically generating integrated circuit schematics containing various components and complex topologies, redundant path optimization and input equivalence variant generation techniques are introduced. Combined with a multi-strategy verification framework that spans simulators, versions, and schematics, differential simulation is performed to detect potential errors.
It enables systematic defect detection of EDA toolchains, improves the efficiency of test data generation and the accuracy of defect discovery, and can identify potential problems in the toolchain during netlist conversion, simulation execution and symbol processing.
Smart Images
Figure CN121525599A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular, relates to an integrated circuit schematic diagram automatic generation method for electronic design automation tool chain error detection. BACKGROUND
[0002] Electronic design automation (EDA) tool chain is the cornerstone of modern integrated circuit (IC) design, which realizes the full-process automation from schematic design, simulation verification to physical layout generation through a series of complex software tools. Among them, the circuit schematic diagram as the logical starting point of the design, its correctness is crucial. EDA tool chain needs to be able to accurately parse the schematic diagram, generate the netlist for simulation, and maintain consistent simulation behavior between different tools and versions. Any small defect in any link may lead to design errors, causing huge time and economic cost. Therefore, rigorous testing of EDA tool chain itself to ensure its reliability and stability is an important research direction in the field of integrated circuit design.
[0003] There are rule-based integrated circuit schematic diagram automatic generation methods in the prior art. Such methods are usually based on a component template library, combined with pre-set connection logic and electrical rule checking, to realize simple circuit topology construction. The tool represented by PCBSmith can automatically select basic passive components (such as resistors, capacitors, inductors) and complete electrical connection according to the series rule, and generate a netlist compatible with the SPICE simulator for functional verification in the EDA tool chain. In the aspect of EDA testing, there have been attempts to introduce differential testing methods into high-level modeling and design tools. For example, at the Simulink model level, by constructing input variants and comparing the behavior results of the model under different versions or different tools, inconsistencies can be found. In the field of digital logic synthesis, there are methods based on syntax perturbation or logic equivalence transformation to explore the robustness and version difference of the synthesizer. However, the above differential testing methods are mainly applicable to the model layer or the logic layer, and there is still no structure perturbation mechanism for the circuit schematic diagram level.
[0004] The prior art has obvious limitations. First, the schematic structure is too simple, limiting the effectiveness of automated defect detection. Existing automatic schematic generation tools mainly use basic passive components (such as resistors, capacitors, and inductors) to construct simple series circuits, lacking support for IC components (such as operational amplifiers and logic gates) and complex topologies (such as feedback loops and branch paths). This type of test circuit structure has limited expressive ability and is difficult to cover the boundary conditions in the parsing, modeling, and simulation processes of the EDA tool chain, resulting in many potential errors that cannot be effectively triggered and detected. Second, the invariability of the schematic structure masks the behavior differences of the tool chain under semantic equivalence conditions. The input equivalence perturbation (EMI) technique has been proven effective in compiler and model testing and has achieved preliminary application in EDA subfields such as Simulink models. However, this technique has not been effectively promoted at the schematic level. On the one hand, the equivalence of circuit semantics is difficult to model formally; on the other hand, minor structural perturbations can lead to electrical rule violations or functional deviations, thus limiting the legal perturbation space. This results in most existing tools being able to generate simple schematic structures, making it difficult to discover minor differences and inconsistencies in the symbolic parsing, netlist generation, or simulation behavior of the EDA tool chain through functionally equivalent but structurally diverse variants. SUMMARY
[0005] Therefore, the present application aims to provide an integrated circuit schematic automatic generation method for electronic design automation tool chain error detection to solve the problem that the prior art does not cover the boundary conditions in the parsing, modeling, and simulation processes of the EDA tool chain.
[0006] The technical means adopted by the present application are as follows: An integrated circuit schematic automatic generation method for electronic design automation tool chain error detection, comprising the following steps: S1, automatically generating an initial integrated circuit schematic based on preset component parameters and electrical rules; S2, optimizing the initial integrated circuit schematic for redundant paths to obtain an optimized schematic; S3, introducing structural perturbations to the optimized schematic based on input equivalence principles to generate at least one functionally equivalent variant schematic.
[0007] Further, it further comprises: S4, inputting the optimized schematic and the variant schematic into different test environments for simulation based on a multi-strategy verification framework, and performing error detection of the electronic design automation tool chain by comparing the simulation results.
[0008] Further, S1 specifically comprises the following steps: S11, based on the input minimum component count The maximum number of components and the component type set , randomly determine the number of components of the interval, and based on the roulette algorithm, according to the preset selection probability and the corresponding cumulative probability , generate a random number to determine the component type ; in the selected type, uniformly randomly select specific components and repeat until the selected components are full ; S12, based on the preset pin connection constraint, automatically route the pins of the components selected in S11; S13, assign typical electrical parameters to passive components in the initial integrated circuit schematic diagram, specify simulation models for active components in the initial integrated circuit schematic diagram, and randomly configure simulation commands; S14, in at least one of the stages of S11, S12 and S13, perform ERC verification.
[0009] Further, the pin connection constraint is as follows: The input pin is configured to be driven by the output pin:
[0010] If the output pin is not connected, the unconnected output pin is configured to form a connection with at least one of the input pin, the passive pin or the bidirectional pin, and recursively build a signal link:
[0011] The ground pin is configured to be connected to the ground node, and no ground loop is formed:
[0012] Among the IC pins, the power pin VCC is connected to the positive power supply:
[0013] Wherein, , is a pin set, wherein and represent any pin in the set; is a pin type, is an input pin, is an output pin, is a ground pin, is a power input pin, represents a positive power component, represents the output voltage value of the power supply, , In a connected state; Pin indication Functionally drive pins ; Pin indication It can be used for further signal allocation; Indicates two pins There are direct connections between them; Indicates from pin It can initially form a signal link that is legal in type and correct in electrical meaning; Used to indicate that the ground wire or special pin has been connected according to the rules; Used to detect a certain pin Does the grounding network contain any loops?
[0014] Furthermore, S2 specifically includes the following steps: Define the set of feedback paths in the initial integrated circuit schematic. The set of feedback paths is divided into positive feedback loops. and negative feedback loop For each positive feedback loop, identify and delete it immediately; for negative feedback loops, insert a feedback resistor. Make adjustments; Scan the power and ground nodes in the schematic diagram to identify equivalent and repeating sets of power symbols. set of symbols The power symbol set and the ground symbol set are uniformly redirected to a single common power source or grounding node.
[0015] Furthermore, S3 specifically includes the following steps: S31. Connect a very small capacitor in parallel at the static pin node. and constant voltage source This stabilizes the node voltage and ensures that the capacitor is open-circuited under DC conditions. The DC conditions are as follows:
[0016] S32. Connect a ground capacitor in parallel at the dynamic pin. , This produces minimal parasitic effects. The generated variant schematic and the schematic are combined and converted into a netlist, which is then input into multiple simulation tools to perform simulations for subsequent differential testing.
[0017] Furthermore, in S4, the multi-strategy verification framework includes cross-simulator strategy, cross-version strategy, and cross-schematic strategy: The cross-emulator strategy simulates the same circuit netlist using different simulation tools under the same simulation mode, specifically including the following stages: Stage one: simulation and comparison of default mode output in six compatible modes of NGspice, to detect differences in mode implementation; Stage two: if NGspice modes are consistent, use KiCad built-in simulator for simulation and comparison with NGspice, to reveal differences in backend implementation; Stage three: use NGspice LTspice compatible mode and LTspice simulation to compare and judge compatibility and tool itself problems; The cross-version strategy compares the simulation results of the same netlist under different versions of the same simulation tool, to identify behavior regression and potential defects in the version evolution process; The cross-schematic strategy: simulate and compare the same simulation tool and mode for functionally equivalent but structurally different schematics and their variants, to detect defects in tool chain parsing, netlist generation and simulation execution based on consistency assumption.
[0018] The application also provides a storage medium comprising a stored program, wherein the program, when executed, performs any of the above-mentioned integrated circuit schematic automatic generation methods for electronic design automation tool chain error detection.
[0019] The application also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the above-mentioned integrated circuit schematic automatic generation method for electronic design automation tool chain error detection by running the computer program.
[0020] Compared with the prior art, the application has the following advantages: The application realizes automatic generation of large-scale integrated circuit schematics, supports generation of schematics with diverse structures from a variety of components according to probability, and significantly improves the generation efficiency of test data. The functional equivalent variant generation mechanism is introduced, the microstructure of the original circuit is adjusted to construct variants with different structures but equivalent functions, and the multi-dimensional differential simulation strategy is proposed, including simulation result comparison across simulators, across versions and across schematics, which can systematically identify potential errors or compatibility problems of EDA tool chain in netlist conversion, simulation execution and symbol processing stages. The application solves the problem of limiting the effectiveness of automatic defect detection in the prior art due to the simplicity of the circuit structure, and avoids the situation that tool chain defects are difficult to expose under semantic equivalence due to structural invariability. BRIEF DESCRIPTION OF DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.
[0022] Figure 1 Flow chart of the method of the present application.
[0023] Figure 2 Schematic diagram of the present application. DETAILED DESCRIPTION
[0024] In order to make the technical personnel of the present application better understand the present application, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.
[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0026] As Figure 1 and 2As shown, the present application provides an integrated circuit schematic diagram automatic generation method for electronic design automation tool chain error detection. The present application constructs a diversified and electrical rule compliant integrated circuit schematic diagram. First, based on pin connection constraints, probabilistic component selection and electrical rule checking, a test schematic diagram containing various integrated circuit (IC) components and complex circuit structures is automatically generated. Subsequently, the generated schematic diagram is corrected using a redundant path optimization component to identify and eliminate invalid feedback loops and redundant power or ground branches, thereby improving the engineering practicality of the schematic diagram. On this basis, input equivalence (EMI) variant generation technology is used to generate circuit variants that are structurally different but functionally equivalent by introducing minor structural perturbations (such as a small parallel capacitor or bypass branch), thereby enhancing the coverage and sensitivity of differential testing. In the differential testing stage, the present application combines a triple testing strategy across simulators, tool versions and schematic variants to systematically compare the simulation results of the same schematic diagram and its variants in multiple simulation tools and different version environments, analyze and locate potential defects, inconsistent behavior and stability issues of the EDA tool chain in the schematic diagram analysis, netlist conversion and simulation execution process. Finally, the present application realizes the automation integration of the entire process and constructs an extensible EDA tool chain defect detection platform, significantly improving the efficiency and accuracy of integrated circuit schematic level defect discovery. Specifically, the steps include: S1, based on the preset component parameters and electrical rules, an initial integrated circuit schematic diagram is automatically generated; this step aims to automatically generate an integrated circuit schematic diagram that meets the electrical rules and has structural diversity, and the specific process includes component selection, pin connection constraints, wiring and electrical rule checking. Specifically as follows: 1. Component selection: based on the minimum component number , the maximum component number , the component type set , first randomly determine the component number interval , using the roulette algorithm, according to the preset selection probability (meeting ) and the corresponding cumulative probability of the component type, generate a random number to determine the component type , wherein the conditions are met: . In the selected type, specific components are randomly selected. Repeat the process until components are selected.
[0027] 2. Pin connection constraints: define pin set , each pin has a type and a connection state , and belongs to the component symbol. The following typical constraints are met: (1) Input pins must be driven by output pins:
[0028] (2) If an output pin is not connected, it is connected to a suitable input, passive, or bidirectional pin, recursively building the signal link:
[0029] (3) Ground pins must be properly connected and avoid ground loops:
[0030] 3. IC pin-specific constraints: Define special connection rules for common IC pin types and naming, such as the power pin VCC must be connected to the positive power supply:
[0031] 4. Wiring and optimization: Automatically add wires according to the above pin connection rules to ensure circuit connectivity.
[0032] 5. Electrical parameter assignment and simulation configuration: Assign typical electrical parameters to passive components, specify simulation models for active components, and randomly configure simulation commands (such as DC, AC, transient analysis, etc.) to ensure the feasibility of the schematic for simulation.
[0033] 6. Electrical rule check (ERC): Perform ERC verification at each stage to prevent common problems such as unconnected pins, power and ground errors, etc., to ensure that the final schematic meets the KiCad electrical specifications.
[0034] S2, perform redundant path optimization on the initial integrated circuit schematic to obtain an optimized schematic; This step aims to identify and eliminate redundant connections in the schematic to improve the rationality and simulation stability of the circuit design. Specifically, it includes: 1. Redundant loop detection and processing: Define a set of feedback paths in the schematic , which can be divided into positive feedback loops and negative feedback loops . For each positive feedback loop , immediately identify and delete it to prevent circuit oscillation and simulation instability. For negative feedback loops , insert a feedback resistor for adjustment, maintaining circuit functionality while avoiding algebraic loop errors.
[0035] 2. Power and ground path simplification: Scan the power and ground nodes in the schematic to identify equivalent and repeated power symbol sets and ground symbol sets unified to a single common power supply or ground node, reducing symbol redundancy, and enhancing schematic clarity.
[0036] S3, based on the input equivalence principle, structural disturbance is introduced to the optimized schematic, and at least one functionally equivalent variant schematic is generated. This step aims to introduce minor disturbances to detect the sensitivity and consistency of the simulation tool for the circuit model by generating functionally equivalent but slightly different variant schematics. The specific methods include: 1. Static node disturbance: connecting a very small capacitor in parallel at the static pin node (such as the power pin VCC) and constant voltage source , ensuring that the node voltage is stable and the capacitor is open at DC, avoiding the introduction of additional current:
[0037] 2. Dynamic node disturbance: connecting a very small capacitor in parallel at the dynamic pin , generating a very small parasitic effect, ensuring that signal integrity is not affected at low frequencies. The generated variant schematic and the schematic are converted into a netlist together, which is input into multiple simulation tools for simulation for subsequent differential testing.
[0038] S4, input the optimized schematic and the variant schematic into different test environments based on the multi-strategy verification framework for simulation, and detect errors in the electronic design automation tool chain by comparing the simulation results.
[0039] Based on the principle of differential testing, a multi-strategy verification framework is designed to find potential defects in the tool chain by comparing different simulation results. The specific strategies include: 1. Cross-simulator strategy: Simulate the same circuit netlist using different simulation tools (NGspice, KiCad built-in simulator, LTspice, etc.) in the same simulation mode. Perform in stages: (1) Stage one: Simulate in six compatible modes of NGspice and compare the output with the default mode to detect mode implementation differences.
[0040] (2) Stage two: If NGspice is consistent in each mode, use the KiCad built-in simulator to simulate and compare with NGspice to reveal backend implementation differences.
[0041] (3) Stage three: Compare the NGspice LTspice compatible mode with the LTspice native simulation to judge compatibility and tool itself problems.
[0042] 2. Cross-version strategy: Compare the simulation results of the same netlist by different versions of the same simulation tool to identify behavior regression and potential defects in the version evolution process.
[0043] 3. Cross-schematic strategy: Simulate and compare functionally equivalent but slightly different schematics and their variants in the same simulation tool and mode, detect defects in tool chain analysis, netlist generation and simulation execution based on consistency assumptions.
[0044] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not limited to them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for automatically generating integrated circuit schematics for error detection in electronic design automation toolchains, characterized in that, Includes the following steps: S1. Based on preset component parameters and electrical rules, automatically generate the initial integrated circuit schematic; S2. Optimize the redundancy path of the initial integrated circuit schematic to obtain the optimized schematic. S3. Based on the principle of input equivalence, introduce structural perturbations into the optimized schematic diagram to generate at least one functionally equivalent variant schematic diagram.
2. The method for automatically generating integrated circuit schematics for error detection in electronic design automation toolchains according to claim 1, characterized in that, Also includes: S4. Input the optimized schematic and variant schematic into different test environments and perform simulations based on a multi-strategy verification framework. Then, compare the simulation results to detect errors in the electronic design automation toolchain.
3. The method for automatically generating integrated circuit schematics for error detection in electronic design automation toolchains according to claim 1, characterized in that, S1 specifically includes the following steps: S11, Minimum number of components based on input Maximum number of components and component type set The number of components is randomly determined. The range, and based on the roulette wheel algorithm, according to the preset selection probability of the component type. and the corresponding cumulative probability Generate random numbers Determine the component type Within the selected type, randomly select specific components evenly and repeat until all are selected. Individual components; S12. Based on preset pin connection constraints, automatically route and connect the pins of the components selected in S11. S13. Assign typical electrical parameters to passive components in the initial integrated circuit schematic, specify simulation models for active components in the initial integrated circuit schematic, and randomly configure simulation commands. S14. Perform ERC verification in at least one of the stages of S11, S12 and S13.
4. The method for automatically generating integrated circuit schematics for error detection in electronic design automation toolchains according to claim 3, characterized in that, The pin connection constraints are as follows: The input pin is configured to be driven by the output pin: If an output pin is not connected, the unconnected output pin is configured to connect to at least one of an input pin, a passive pin, or a bidirectional pin, recursively constructing the signal path: The ground pin is configured to connect to the ground node without forming a ground loop: In the IC pin configuration, the power supply pin VCC is connected to the positive power supply. in, , For the pin set, where and This represents any pin in the set; Pin type For input pins, For output pins, For ground pin, This is the power input pin. Indicates a positive power supply component. This indicates the output voltage value of the power supply. , In a connected state; Pin indication Functionally drive pins ; Pin indication It can be used for further signal allocation; Indicates two pins There are direct connections between them; Indicates from pin It can initially form a signal link that is legal in type and correct in electrical meaning; Used to indicate that the ground wire or special pin has been connected according to the rules; Used to detect a certain pin Does the grounding network contain any loops? 5. The method for automatically generating integrated circuit schematics for error detection in electronic design automation toolchains according to claim 1, characterized in that, S2 specifically includes the following steps: Define the set of feedback paths in the initial integrated circuit schematic. The set of feedback paths is divided into positive feedback loops. and negative feedback loop For each positive feedback loop, identify and delete it immediately; for negative feedback loops, insert a feedback resistor. Make adjustments; Scan the power and ground nodes in the schematic diagram to identify equivalent and repeating sets of power symbols. set of symbols The power symbol set and the ground symbol set are uniformly redirected to a single common power source or grounding node.
6. The method for automatically generating integrated circuit schematics for error detection in electronic design automation toolchains according to claim 1, characterized in that, S3 specifically includes the following steps: S31. Connect a very small capacitor in parallel at the static pin node. and constant voltage source This stabilizes the node voltage and ensures that the capacitor is open-circuited under DC conditions. The DC conditions are as follows: S32. Connect a ground capacitor in parallel at the dynamic pin. , This produces minimal parasitic effects. The generated variant schematic and the schematic are combined and converted into a netlist, which is then input into multiple simulation tools to perform simulations for subsequent differential testing.
7. The method for automatically generating integrated circuit schematics for error detection in electronic design automation toolchains according to claim 2, characterized in that, In S4, the multi-strategy verification framework includes cross-simulator strategy, cross-version strategy, and cross-schematic strategy: The cross-emulator strategy simulates the same circuit netlist using different simulation tools under the same simulation mode, specifically including the following stages: Phase 1: Simulate and compare the output of the default mode under the six compatibility modes of NGspice to detect differences in mode implementation; Phase Two: If all NGspice modes are consistent, use the KiCad built-in simulator to perform simulation and compare it with NGspice to reveal the differences in backend implementation; Phase 3: Compare the NGSpic and LTspice on-the-fly simulations using the NGSpic and LTspice compatibility modes to determine compatibility issues and tool-related problems. The cross-version strategy compares the simulation results of the same netlist under different versions of the same simulation tool, and identifies behavioral regression and potential defects in the version evolution process. The cross-schema strategy involves simulating and comparing functionally equivalent but structurally slightly different schematics and their variants using the same simulation tools and modes, and detecting defects in toolchain parsing, netlist generation, and simulation execution based on consistency assumptions.
8. A storage medium, characterized in that, The storage medium includes a stored program, wherein, when the program is executed, it performs the automatic generation method for integrated circuit schematics for error detection in electronic design automation toolchains as described in any one of claims 1 to 7.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the automatic generation method for integrated circuit schematics for error detection in electronic design automation toolchains as described in any one of claims 1 to 7 through the computer program.