Chip electrostatic protection circuit and protection method thereof

Abstract

The invention provides a chip electrostatic protection circuit and a protection method thereof.The chip electrostatic protection circuit comprises an electrostatic transmission module, a clamping module and a discharge protection module, electrostatic energy of an input port and an output port of a chip is transmitted through the electrostatic transmission module, and the clamping module is connected with the electrostatic transmission module and a power port; static energy is discharged through the clamping module, when chip control voltage is input into the chip input and output port, the clamping module is prevented from being mistakenly conducted through the discharging protection module, and on the basis of a reverse series connection structure of a diode in the static transmission module and a Schottky diode in the clamping module, the clamping module is prevented from being mistakenly conducted. And DC isolation between the input and output ports of the chip and the power port is realized. According to the protection circuit provided by the invention, the DC isolation of the chip input / output port and the power supply port is realized through the Schottky diode, the power-on time sequence requirement is avoided, and the voltage input range is expanded; in order to prevent the static discharge access from being opened mistakenly when the chip works normally, the discharge protection module controls the control voltage of the static discharge access.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a chip electrostatic protection circuit and a protection method thereof. BACKGROUND

[0002] With the vigorous development of integrated circuits, chips are the "brain" and "heart" of the electronic field, and are the cornerstone of the modern digital world. Static electricity is one of the key factors that can damage the function of the chip, therefore, to avoid damage to the internal devices of the chip by static electricity, it is essential to implement effective electrostatic protection.

[0003] In the prior art, the electrostatic protection circuit of the chip adopts a structure combining a diode and a power supply clamping circuit, which is applied in various chips due to its small area and strong electrostatic discharge capability. The use of the existing electrostatic discharge circuit requires that the control voltage of the chip cannot be higher than the power supply voltage of the chip; if the power supply port of the chip is not powered on, the input and output ports of the chip are powered on, the diode will be burned out due to excessive current, resulting in failure of the electrostatic protection circuit.

[0004] Therefore, how to provide a chip electrostatic protection circuit without power-on timing requirements and with a wide range of input voltages of the chip is a technical problem to be solved at present. SUMMARY

[0005] The present application provides a chip electrostatic protection circuit and a protection method thereof to solve the problem of the need for specific power-on timing and the limitation of the voltage range of the input and output ports of the chip in the above-mentioned electrostatic protection circuit.

[0006] In a first aspect, the present application provides a chip electrostatic protection circuit, comprising: an electrostatic transmission module connected to the input and output ports of the chip, which transmits the electrostatic energy of the input and output ports of the chip; a clamping module connected to the electrostatic transmission module and a power supply port, which discharges the electrostatic energy of the corresponding port when the electrostatic effect occurs in the power supply port or the input and output ports of the chip; a discharge protection module connected to the input and output ports of the chip and the clamping module, which prevents the clamping module from being misdirected when the chip control voltage is input into the input and output ports of the chip; wherein the reverse series structure composed of the diode in the electrostatic transmission module and the Schottky diode in the clamping module realizes the direct current isolation of the input and output ports of the chip and the power supply port.

[0007] In an embodiment of the present application, the static electricity transmission module comprises a first diode and a second diode, an anode of the first diode is connected to a cathode of the second diode, and an anode of the second diode is connected to ground, wherein an anode of the first diode is connected to the chip input / output port, and a cathode of the first diode is a first node.

[0008] In an embodiment of the present application, the clamping module comprises two clamping units and a first Schottky diode, a first clamping unit is connected to the first node, and discharges positive static electricity energy of the chip input / output port or positive static electricity energy of the power supply port; a cathode of the first Schottky diode is connected to the first clamping unit, and an anode of the first Schottky diode is connected to a second clamping unit; the second clamping unit is connected to the power supply port, and discharges positive static electricity energy or negative static electricity energy of the power supply port, wherein the static electricity energy comprises the positive static electricity energy and the negative static electricity energy.

[0009] In an embodiment of the present application, the clamping unit comprises a first resistor, a first capacitor, a first PMOS tube, a first NMOS tube and a second NMOS tube, a first end of the first resistor is connected to a source of the first PMOS tube, a second end of the first resistor is connected to a first end of the first capacitor, a second end of the first capacitor is connected to ground, the second end of the first resistor is also connected to a gate of the first PMOS tube, the gate of the first PMOS tube is connected to a gate of the first NMOS tube, a drain of the first PMOS tube is connected to a drain of the first NMOS tube, a source of the first NMOS tube is connected to ground, the drain of the first PMOS tube is also connected to a gate of the second NMOS tube, a drain of the second NMOS tube is connected to a source of the first PMOS tube, and a source of the second NMOS tube is connected to ground.

[0010] In an embodiment of the present application, a cathode of the first Schottky diode is connected to the first node, and an anode of the first Schottky diode is connected to the power supply port.

[0011] In one embodiment of this application, the discharge protection module includes a second resistor, a third resistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a second Schottky diode. The first terminal of the second resistor is connected to the cathode of the second Schottky diode, the anode of the second Schottky diode is connected to the drain of the third NMOS transistor, the drain of the third NMOS transistor is also connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to the first terminal of the third resistor, the second terminal of the third resistor is connected to the drain of the fifth NMOS transistor, and the gate of the fifth NMOS transistor is connected to the first terminal of the third resistor. The first terminal of the second resistor is the input terminal of the discharge protection module, the drain of the fifth NMOS transistor is connected to the first node, and the source of the fifth NMOS transistor is the output terminal of the discharge protection module.

[0012] In one embodiment of this application, the breakdown voltage of the first Schottky diode and the second Schottky diode is greater than the maximum chip control voltage at the chip input / output port, and the breakdown voltage of the first Schottky diode and the second Schottky diode is less than the breakdown voltage inside the chip.

[0013] Secondly, this application provides a protection method applied to the chip electrostatic discharge protection circuit as described above, comprising: Monitor the real-time voltage of the chip's input / output ports and power supply ports; When electrostatic discharge occurs at the chip's input / output port or the power port, the electrostatic energy is discharged based on the electrostatic transmission module and the clamping module.

[0014] In one embodiment of this application, the electrostatic energy includes positive electrostatic energy and negative electrostatic energy. When an electrostatic effect occurs at the chip input / output port or the power port, the electrostatic energy is discharged based on the electrostatic transmission module and the clamping module, including: when the power port has positive electrostatic energy, discharging the positive electrostatic energy through one clamping unit of the clamping module; when the chip input / output port has positive electrostatic energy, discharging the positive electrostatic energy through the first clamping unit of the clamping module; when the power port has negative electrostatic energy, discharging the negative electrostatic energy through the second clamping unit of the clamping module; and when the chip input / output port has negative electrostatic energy, discharging the negative electrostatic energy through the electrostatic transmission module.

[0015] In one embodiment of this application, the method further includes: when the chip input / output port receives a chip control voltage, controlling the first clamping unit to not operate based on the discharge protection module.

[0016] The beneficial effects of this application are as follows: This application provides a chip electrostatic discharge (ESD) protection circuit and its protection method. The chip ESD protection circuit includes an ESD transmission module, a clamping module, and a discharge protection module. The ESD transmission module transmits the ESD energy at the chip's input / output ports. The clamping module is connected to the ESD transmission module and the power supply port, dissipating the ESD energy. When the chip's control voltage is input at the chip's input / output ports, the discharge protection module prevents the clamping module from being mis-energized. Based on the reverse series structure formed by the diodes in the ESD transmission module and the Schottky diodes in the clamping module, DC isolation between the chip's input / output ports and the power supply port is achieved. The chip ESD protection circuit provided by this application achieves DC isolation between the chip's input / output ports and the power supply port through the Schottky diodes in the clamping module. There are no power-on timing requirements for the two ports, and the voltage input range is expanded. The circuit has strong ESD discharge capability. By designing the discharge protection module, the control voltage of the ESD discharge path in the clamping module is precisely controlled, preventing the ESD discharge path from being mis-energized during normal chip operation. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] In the attached diagram: Figure 1 This is a schematic diagram of an electrostatic discharge (ESD) protection circuit for chips in the prior art; Figure 2 This is a block diagram of the chip electrostatic discharge protection circuit provided in the embodiments of this application; Figure 3 This is a schematic diagram of the specific structure of the chip electrostatic protection circuit provided in the embodiments of this application.

[0019] Figure reference numerals: 110 - Electrostatic transfer module; 120 - Clamping module; 121 - First clamping unit; 122 - Second clamping unit; 130 - Discharge protection module; VC C - Power supply voltage. Detailed Implementation

[0020] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0021] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present application. However, it will be apparent to those skilled in the art that embodiments of the present application may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present application.

[0023] With the rapid development of integrated circuits, chips are the "brain" and "heart" of the electronics field and the cornerstone of the modern digital world. Static electricity is one of the key factors that can damage chip functions; therefore, electrostatic protection must be implemented for chips, otherwise their internal components are highly susceptible to electrostatic damage.

[0024] In existing technologies, such as Figure 1 As shown, the electrostatic discharge (ESD) protection circuit of a conventional chip uses a combination of diodes and power clamping circuits. This structure is widely used in various chips due to its small size and strong ESD discharge capability. When using a conventional ESD discharge circuit, the control voltage of the chip must not exceed the power supply voltage, and there must be a power-on sequence requirement. For example... Figure 1 As shown, when the control voltage at the chip's input / output port (I / O terminal) is higher than the power supply voltage VCC at the power supply port and exceeds the forward voltage of diode D1, diode D1 will burn out due to excessive current. Similarly, if a high-level control voltage is applied to the input / output port (I / O terminal) before the power supply voltage VCC is powered on, diode D1 will also conduct fully in the forward direction and burn out due to excessive current. Therefore, chips with conventional electrostatic discharge (ESD) protection structures require the power supply voltage VCC to stabilize before applying a control voltage, and the magnitude of the control voltage is limited by the magnitude of the power supply voltage VCC. Chips with conventional ESD protection structures can no longer meet the application requirements of modern electronic systems involving multiple voltage domains and complex timing.

[0025] To solve the above problems, such as Figure 2 As shown, this application provides a chip electrostatic discharge (ESD) protection circuit, including: The electrostatic transmission module 110 is connected to the chip's input / output port and transmits the electrostatic energy of the chip's input / output port. The clamping module 120 is connected to the electrostatic transmission module 110 and the power port. When an electrostatic effect occurs at the power port or the chip input / output port, it discharges the electrostatic energy of the corresponding port. The discharge protection module 130 is connected to the chip input / output port and the clamping module 120. It is used to prevent the clamping module 120 from being mis-connected when the chip control voltage is input to the chip input / output port. The reverse series structure formed by the diode in the electrostatic transmission module 110 and the Schottky diode in the clamping module 120 enables DC isolation between the chip's input / output ports and power supply ports.

[0026] In detail, such as Figure 3 As shown, the electrostatic transmission module 110 includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the cathode of the second diode D2, and the anode of the second diode D2 is grounded. The anode of the first diode D1 is connected to the chip input / output port, which is connected to the internal circuit of the chip. The cathode of the first diode D1 is the first node a.

[0027] In detail, the clamping module 120 includes two clamping units and a first Schottky diode D3. The first clamping unit 121 is connected to the first node a and the cathode of the first diode D1, discharging the positive electrostatic energy at the chip's input / output port or the positive electrostatic energy at the power supply port. The cathode of the first Schottky diode D3 is connected to the first clamping unit 121, and the anode of the first Schottky diode D3 is connected to the second clamping unit 122. The second clamping unit 122 is connected to the power supply port, which receives the power supply voltage VCC. The second clamping unit 122 discharges the positive or negative electrostatic energy at the power supply port, where the electrostatic energy includes both positive and negative electrostatic energy.

[0028] In detail, the clamping unit includes a first resistor, a first capacitor, a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first end of the first resistor is connected to the source of the first PMOS transistor, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, the second end of the first resistor is also connected to the gate of the first PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, the drain of the first PMOS transistor is also connected to the gate of the second NMOS transistor, the drain of the second NMOS transistor is connected to the source of the first PMOS transistor, and the source of the second NMOS transistor is grounded.

[0029] Specifically, such as Figure 3 As shown, the first clamping unit 121 includes a first resistor R11, a first capacitor C11, a first PMOS transistor PM11, a first NMOS transistor NM11, and a second NMOS transistor NM21. The first terminal of the first resistor R11 is connected to the source of the first PMOS transistor PM11, and the second terminal of the first resistor R11 is connected to the first terminal of the first capacitor C11. The second terminal of the first capacitor C11 is grounded. The second terminal of the first resistor R11 is also connected to the gate of the first PMOS transistor PM11. The first NMOS transistor NM11's drain is connected to the gate of the first PMOS transistor PM11, the first PMOS transistor PM11's drain is connected to the drain of the first NMOS transistor NM11, the first NMOS transistor NM11's source is grounded, the first PMOS transistor PM11's drain is also connected to the gate of the second NMOS transistor NM21, the second NMOS transistor NM21's drain is connected to the source of the first PMOS transistor PM11, and the second NMOS transistor NM21's source is grounded. The first PMOS transistor PM11's source is connected to the cathode of the first Schottky diode D3.

[0030] Specifically, such as Figure 3As shown, the second clamping unit 122 includes a first resistor R12, a first capacitor C12, a first PMOS transistor PM12, a first NMOS transistor NM12, and a second NMOS transistor NM22. The first terminal of the first resistor R12 is connected to the source of the first PMOS transistor PM12, and the second terminal of the first resistor R12 is connected to the first terminal of the first capacitor C12. The second terminal of the first capacitor C12 is grounded. The second terminal of the first resistor R12 is also connected to the gate of the first PMOS transistor PM12. The first PMOS transistor PM12 is connected to the gate of the first NMOS transistor NM12, the drain of the first PMOS transistor PM12 is connected to the drain of the first NMOS transistor NM12, the source of the first NMOS transistor NM12 is grounded, the drain of the first PMOS transistor PM12 is also connected to the gate of the second NMOS transistor NM22, the drain of the second NMOS transistor NM22 is connected to the source of the first PMOS transistor PM12, and the source of the second NMOS transistor NM22 is grounded. The source of the first PMOS transistor PM12 is connected to the anode of the first Schottky diode D3.

[0031] In detail, such as Figure 3 As shown, the cathode of the first Schottky diode D3 is connected to the first node, and the anode of the first Schottky diode D3 is connected to the power supply port, which receives the power supply voltage VCC.

[0032] In detail, such as Figure 3 As shown, the discharge protection module 130 includes a second resistor R2, a third resistor R3, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, and a second Schottky diode D4. The first end of the second resistor R2 is connected to the cathode of the second Schottky diode D4. The anode of the second Schottky diode D4 is connected to the drain of the third NMOS transistor NM3. The drain of the third NMOS transistor NM3 is also connected to its gate. The source of the third NMOS transistor NM3 is grounded. The gate of the third NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is grounded. The drain of the fourth NMOS transistor NM5 is connected to the third... The first end of resistor R3 and the second end of the third resistor R3 are connected to the drain of the fifth NMOS transistor NM5. The gate of the fifth NMOS transistor NM5 is connected to the first end of the third resistor R3. The first end of the second resistor R2 is the input terminal of the discharge protection module 130. The input terminal of the discharge protection module 130 is connected to the chip's input / output port and is also connected to the chip's internal circuitry. The drain of the fifth NMOS transistor NM5 is connected to the first node a and the cathode of the first diode D1. The source of the fifth NMOS transistor NM5 is the output terminal of the discharge protection module 130, and the output terminal of the discharge protection module 130 is connected to the second end of the first resistor R11.

[0033] More specifically, the breakdown voltages of the first Schottky diode D3 and the second Schottky diode D4 are greater than the maximum chip control voltage at the chip's input / output ports, while the breakdown voltages of the first Schottky diode D3 and the second Schottky diode D4 are less than the breakdown voltages of the internal components of the chip. Specifically, the breakdown voltages of the first Schottky diode D3 and the second Schottky diode D4 are greater than the maximum chip control voltage at the chip's input / output ports, and the breakdown voltages of the two Schottky diodes (D3 and D4) are less than the breakdown voltages of the internal components of the chip.

[0034] Please refer to Figures 2 to 3 As shown, the working principle of the chip electrostatic discharge protection circuit provided in this application is as follows: like Figure 2 As shown, the electrostatic discharge module 110 is connected to the chip's input / output port to transmit the electrostatic energy present at the chip's input / output port. The clamping module 120 is connected to the electrostatic discharge module 110 and the power port to discharge electrostatic energy when an electrostatic effect occurs at the power port or the chip's input / output port. The discharge protection module 130 is connected to the chip's input / output port and the clamping module 120. When the chip control voltage is input at the chip's input / output port (I / O port), it controls the first clamping unit 121 in the clamping module 120 to not work, thereby preventing the chip control voltage from being discharged to ground from the first clamping unit 121.

[0035] like Figure 3 As shown, when the chip is working normally, because there is a first diode D1 and a first Schottky diode D3 between the chip input / output port (I / O port) and the power supply port, even if the chip input / output port (I / O port) is powered on before the power supply port, there is no current path between the chip input / output port (I / O port) and the power supply port; at the same time, the chip control voltage input to the chip input / output port (I / O port) can be greater than the power supply voltage VCC provided by the power supply port.

[0036] like Figure 3 As shown, when the voltage input to the chip input / output port is the chip control voltage, for example, when the chip control voltage is 3V, the second Schottky diode D4 in the discharge protection module 130 is cut off, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 in the discharge protection module 130 are cut off, the level of node b is high voltage, the fifth NMOS transistor NM5 is on, the level of node c is high level, and the first NMOS transistor NM11 is on. Therefore, when the chip control voltage is input to the chip input / output port, due to the presence of the discharge protection module 130, the first clamping unit 121 will not generate an energy transmission path.

[0037] When a positive electrostatic discharge (ESD) effect occurs at the power port, on one hand, the positive ESD energy at the power port is transferred to the first clamping unit 121 through the first Schottky diode D3. Because the voltage at the first node a is greater than the gate voltage of the first PMOS transistor PM11 in the first clamping unit 121, the first PMOS transistor PM11 is turned on, the gate of the second NMOS transistor NM21 is at a high level, and the second NMOS transistor NM21 is turned on, discharging the positive ESD energy to ground through the second NMOS transistor NM21. On the other hand, the positive ESD energy at the power port is greater than the gate voltage of the first PMOS transistor PM12 in the second clamping unit 122, so the first PMOS transistor PM12 is turned on, the gate voltage of the second NMOS transistor NM22 in the second clamping unit 122 is at a high level, and the second NMOS transistor NM22 is turned on, discharging the positive ESD energy at the power port to ground through the second NMOS transistor NM22. Therefore, the positive ESD energy at the power port is discharged through one of the clamping units of the clamping module 120.

[0038] When a negative voltage electrostatic effect occurs at the power port, because the voltage at the power port is less than the gate voltage of the second NMOS transistor NM22 in the second clamping unit 122, the second NMOS transistor NM22 in the second clamping unit 122 is turned on, thereby dissipating the negative voltage electrostatic energy through the second clamping unit 122.

[0039] When a positive electrostatic discharge (ESD) effect occurs at the chip's input / output ports, the second Schottky diode D4 breaks down and conducts, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 conduct, the level at node b is low, and the fifth NMOS transistor NM5 is off. The positive ESD energy present at the chip's input / output ports is discharged to ground through the second NMOS transistor NM21 because the voltage at the first node a is greater than the gate voltage of the first PMOS transistor PM11 in the first clamping unit 121. The gate voltage of the second NMOS transistor NM21 is high, so NM21 conducts. When a negative ESD effect occurs at the chip's input / output ports, the negative ESD energy is discharged to ground through the second diode D2 in the electrostatic discharge module 110 because the voltage at the chip's input / output ports is less than the voltage at ground.

[0040] This application also provides a protection method applied to the chip electrostatic discharge protection circuit as described above, the method comprising: Monitor the real-time voltage of the chip's input / output ports and power supply ports; When electrostatic discharge occurs at the chip's input / output ports or power ports, the electrostatic energy is discharged based on the electrostatic discharge module 110 and the clamping module 120.

[0041] Specifically, the voltage of the chip's input / output ports and power ports is monitored; when electrostatic discharge occurs at the chip's input / output ports or power ports, the positive electrostatic energy of the chip's input / output ports and power ports is discharged based on the clamping module 120, the negative electrostatic energy of the power port is discharged through the second clamping unit 122 in the clamping module 120, and the negative electrostatic energy of the chip's input / output ports is discharged through the second diode D2 in the electrostatic transmission module 110.

[0042] In detail, the electrostatic energy includes positive electrostatic energy and negative electrostatic energy. When an electrostatic effect occurs at the chip's input / output port or power port, the electrostatic energy is discharged based on the electrostatic transmission module 110 and the clamping module 120, including: when there is positive electrostatic energy at the power port, the positive electrostatic energy is discharged through one of the clamping units in the clamping module 120; when there is positive electrostatic energy at the chip's input / output port, the positive electrostatic energy is discharged through the first clamping unit 121 in the clamping module 120; when there is negative electrostatic energy at the power port, the negative electrostatic energy is discharged through the second clamping unit 122 in the clamping module 120; and when there is negative electrostatic energy at the chip's input / output port, the negative electrostatic energy is discharged through the second diode D2 in the electrostatic transmission module 110.

[0043] More specifically, the method further includes: when the chip control voltage is input to the chip input / output port, the first clamping unit 121 is deactivated based on the discharge protection module 130 to prevent the formation of an energy transfer path. Specifically, when the voltage at the chip input / output port is the chip control voltage, the second Schottky diode D4 in the discharge protection module 130 is cut off, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 in the discharge protection module 130 are cut off, the level at node b is high, the fifth NMOS transistor NM5 is on, the level at node c in the first clamping unit 121 is high, the first NMOS transistor NM11 is on, the chip control voltage input to the chip input / output port is not transmitted through the first clamping unit 121, and the chip operates normally.

[0044] This application provides a chip electrostatic discharge (ESD) protection circuit and method thereof. The chip ESD protection circuit includes an ESD transmission module, a clamping module, and a discharge protection module. The ESD transmission module transmits ESD energy from the chip's input / output ports. The clamping module is connected to the ESD transmission module and the power supply port, discharging the ESD energy. When the chip's control voltage is input to the chip's input / output ports, the discharge protection module prevents the clamping module from being mis-energized. Based on the reverse series structure formed by the diodes in the ESD transmission module and the Schottky diodes in the clamping module, DC isolation between the chip's input / output ports and the power supply port is achieved. The chip ESD protection circuit provided in this application achieves DC isolation between the chip's input / output ports and the power supply port through the Schottky diodes in the clamping module. There are no power-on timing requirements for the two ports, and the voltage input range is expanded. The circuit has strong ESD discharge capability. By designing the discharge protection module, the control voltage of the ESD discharge path in the clamping module is precisely controlled, preventing the ESD discharge path from being mis-energized during normal chip operation.

[0045] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A chip electrostatic discharge (ESD) protection circuit, characterized in that, include: An electrostatic transmission module is connected to the chip's input / output ports to transmit the electrostatic energy from the chip's input / output ports. The clamping module is connected to the electrostatic transmission module and the power port. When an electrostatic effect occurs at the power port or the chip input / output port, it discharges the electrostatic energy of the corresponding port. A discharge protection module, which is connected to the chip input / output port and the clamping module, is used to prevent the clamping module from misleading the circuit when the chip control voltage is input to the chip input / output port. The DC isolation between the chip's input / output ports and the power supply port is achieved by using a reverse series structure formed by the diodes in the electrostatic transmission module and the Schottky diodes in the clamping module.

2. The chip electrostatic discharge protection circuit according to claim 1, characterized in that, The electrostatic transmission module includes a first diode and a second diode. The anode of the first diode is connected to the cathode of the second diode, and the anode of the second diode is grounded. The anode of the first diode is connected to the input / output port of the chip, and the cathode of the first diode is the first node.

3. The chip electrostatic discharge protection circuit according to claim 2, characterized in that, The clamping module includes two clamping units and a first Schottky diode. The first clamping unit is connected to the first node and discharges the positive electrostatic energy at the chip's input / output port or the power supply port. The cathode of the first Schottky diode is connected to the first clamping unit, and the anode of the first Schottky diode is connected to the second clamping unit. The second clamping unit is connected to the power supply port and discharges the positive or negative electrostatic energy at the power supply port, wherein the electrostatic energy includes both the positive and negative electrostatic energy.

4. The chip electrostatic discharge protection circuit according to claim 3, characterized in that, The clamping unit includes a first resistor, a first capacitor, a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first end of the first resistor is connected to the source of the first PMOS transistor, the second end of the first resistor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, the second end of the first resistor is also connected to the gate of the first PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, the drain of the first PMOS transistor is also connected to the gate of the second NMOS transistor, the drain of the second NMOS transistor is connected to the source of the first PMOS transistor, and the source of the second NMOS transistor is grounded.

5. The chip electrostatic discharge protection circuit according to claim 3, characterized in that, The cathode of the first Schottky diode is connected to the first node, and the anode of the first Schottky diode is connected to the power supply port.

6. The chip electrostatic discharge protection circuit according to claim 3, characterized in that, The discharge protection module includes a second resistor, a third resistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a second Schottky diode. The first terminal of the second resistor is connected to the cathode of the second Schottky diode. The anode of the second Schottky diode is connected to the drain of the third NMOS transistor. The drain of the third NMOS transistor is also connected to its gate. The source of the third NMOS transistor is grounded. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The drain of the fourth NMOS transistor is connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the first terminal of the third resistor. The first terminal of the second resistor is the input terminal of the discharge protection module. The drain of the fifth NMOS transistor is connected to the first node. The source of the fifth NMOS transistor is the output terminal of the discharge protection module.

7. The chip electrostatic discharge protection circuit according to claim 6, characterized in that, The breakdown voltages of the first Schottky diode and the second Schottky diode are greater than the maximum chip control voltage at the chip's input / output ports, while the breakdown voltages of the first Schottky diode and the second Schottky diode are less than the internal breakdown voltage of the chip.

8. A protection method applied to a chip electrostatic discharge (ESD) protection circuit as described in any one of claims 1-7, characterized in that, include: Monitor the real-time voltage of the chip's input / output ports and power supply ports; When electrostatic discharge occurs at the chip's input / output port or the power port, the electrostatic energy is discharged based on the electrostatic transmission module and the clamping module.

9. The protection method for the chip electrostatic discharge protection circuit according to claim 8, characterized in that, The electrostatic energy includes positive voltage electrostatic energy and negative voltage electrostatic energy. When an electrostatic effect occurs at the chip input / output port or the power port, the electrostatic energy is discharged based on the electrostatic transmission module and the clamping module, including: When the positive electrostatic energy is present at the power port, the positive electrostatic energy is discharged through one of the clamping units of the clamping module. When the positive electrostatic energy exists at the chip's input / output port, the positive electrostatic energy is discharged through the first clamping unit in the clamping module. When the negative voltage electrostatic energy exists at the power port, the negative voltage electrostatic energy is discharged through the second clamping unit in the clamping module. When the negative voltage electrostatic energy exists at the chip's input / output port, the negative voltage electrostatic energy is discharged through the electrostatic transmission module.

10. The protection method for the chip electrostatic discharge protection circuit according to claim 9, characterized in that, The method further includes: When the chip control voltage is input to the chip input / output port, the first clamping unit is controlled to not work based on the discharge protection module.

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