Wiring structure, wiring method and circuit board

Abstract

The invention relates to a wiring structure, a wiring method and a circuit board, the wiring structure comprises a plurality of wiring layers, the plurality of wiring layers comprise at least one first wiring layer with a first circuit, the first circuit comprises a first circuit segment and at least one second circuit segment, the width of the second circuit section is configured to be determined by taking a second wiring layer as a reference plane, and the second wiring layer is the closest wiring layer of the first wiring layer; the width of the first circuit section is configured to be determined by taking the third wiring layer as a reference plane, and the third wiring layer is a wiring layer adjacent to the first wiring layer, so that the PCB wiring space can be effectively saved, the influence of shadows on non-ground circuit arrangement can be reduced, and the wiring loss of the PCB can also be reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of printed circuit board, in particular, to a wiring structure, a wiring method and a circuit board. BACKGROUND

[0002] With the increasing rate of SERDES (serializer / deserializer), the requirement for PCB (Printed Circuit Board) wiring loss is also increasing. In the case of PCB material, trace length, layering, and impedance being determined, the existing solution to reduce PCB wiring loss is generally to set a layer reference. However, such a setting occupies more PCB wiring layers and squeezes the wiring space of non-ground traces, affecting the arrangement of non-ground traces. SUMMARY

[0003] The purpose of the present disclosure is to provide a wiring structure, a wiring method and a circuit board, which can save wiring space and reduce the arrangement of non-ground traces to at least partially solve the above technical problems.

[0004] To achieve the above purpose, the first aspect of the present disclosure provides a wiring structure, comprising: a plurality of wiring layers, wherein at least one first wiring layer having a first trace is included in the plurality of wiring layers; the first trace comprises a first trace segment and at least one second trace segment; the width of the second trace segment is configured to be determined with the second wiring layer as a reference plane, wherein the second wiring layer is the wiring layer most adjacent to the first wiring layer; the width of the first trace segment is configured to be determined with the third wiring layer as a reference plane, wherein the third wiring layer is the wiring layer next adjacent to the first wiring layer.

[0005] Optionally, the width of the first trace segment is greater than the width of the second trace segment.

[0006] Optionally, the second wiring layer and the third wiring layer are connected through a reflow ground hole.

[0007] Optionally, the reflow ground hole is arranged at the joint of the first trace segment and the second trace segment and located on opposite sides of the first trace.

[0008] Optionally, the first trace comprises a single-ended impedance trace or a differential trace.

[0009] Optionally, an insulating layer is arranged between two adjacent wiring layers.

[0010] The second aspect of the present disclosure provides a wiring method, comprising: arranging a plurality of wiring layers, the plurality of wiring layers including at least a first wiring layer having a first line; arranging the first wiring layer, including: determining a width of a second line segment of the first line with a second wiring layer as a reference plane; wherein the second wiring layer is a wiring layer most adjacent to the first wiring layer; determining a width of a first line segment of the first line with a third wiring layer as a reference plane, wherein the third wiring layer is a wiring layer next adjacent to the first wiring layer.

[0011] Optionally, the width of the first line segment is greater than the width of the second line segment.

[0012] Optionally, the method further includes: arranging a reflow via between the second wiring layer and the third wiring layer; connecting the second wiring layer and the third wiring layer through the reflow via.

[0013] Optionally, the reflow via is arranged at a joint of the first line segment and the second line segment and located on opposite sides of the first line.

[0014] Optionally, the first line includes a single-ended impedance line or a differential line.

[0015] Optionally, the method further includes: arranging an insulating layer between two adjacent wiring layers.

[0016] A third aspect of the present disclosure provides a circuit board, including a wiring structure, the wiring structure including the wiring structure according to the first aspect of the present disclosure; or formed by the wiring method according to the second aspect of the present disclosure.

[0017] According to the above technical solution, the wiring structure includes a plurality of wiring layers, the plurality of wiring layers including at least a first wiring layer having a first line, the first line including a first line segment and at least a second line segment, the width of the second line segment being configured to be determined with a second wiring layer as a reference plane, and the width of the first line segment being configured to be determined with a third wiring layer as a reference plane, wherein the second wiring layer is a wiring layer most adjacent to the first wiring layer, and the third wiring layer is a wiring layer next adjacent to the first wiring layer. In this way, for the first line arranged in the first wiring layer, the most adjacent wiring layer and the next adjacent wiring layer of the first wiring layer can be flexibly taken as reference layers in the case of unchanged impedance, and when a part of the area in the next adjacent reference layer of the first wiring layer needs to be arranged with a non-ground line, the most adjacent wiring layer of the first wiring layer can be taken as a reference layer, thereby effectively saving the PCB wiring space and reducing the impact on the arrangement of the non-ground line.

[0018] Other features and advantages of the present disclosure will be described in detail in the following detailed description of some exemplary embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the following detailed description, serve to explain the present disclosure. In the drawings: Figure 1 is a side view schematic diagram of a partial wiring structure provided in some exemplary embodiments of the present disclosure; Figure 2 is a side view schematic diagram of a partial wiring structure provided in some exemplary embodiments of the present disclosure; Figure 3 is a top view schematic diagram of a partial wiring structure provided in some exemplary embodiments of the present disclosure, in which only the first wiring layer, the first line and the reflow via hole are shown in the diagram.

[0020] BRIEF DESCRIPTION OF DRAWINGS 10 - wiring layer; 11 - first wiring layer; 12 - second wiring layer; 13 - third wiring layer; 20 - first line; 21 - first line segment; 22 - second line segment; 30 - reflow via hole; 40 - insulating layer; 50 - first region; 60 - non-ground line; 100 - wiring structure. DETAILED DESCRIPTION

[0021] The detailed description of the present disclosure is described below in conjunction with the accompanying drawings. It should be understood that the detailed description described herein is only used to explain and illustrate the present disclosure, and is not used to limit the present disclosure.

[0022] The orientation words such as "inner, outer" used without the opposite description refer to the inner and outer relative to the outline of the component or structure itself. In addition, it should be noted that the terms such as "first, second" are used to distinguish one element from another element, and do not have sequential and important nature. In addition, in the description with reference to the drawings, the same reference signs in different drawings represent the same elements.

[0023] As SERDES (serializers / deserializers) speeds increase, the requirements for PCB (printed circuit board) routing loss also become more stringent. Given a fixed PCB material, trace length, layer stack-up, and impedance, existing solutions for reducing PCB routing loss generally involve interlayer referencing. This involves increasing the dielectric thickness between the trace and the reference layer to increase the trace width, thereby reducing routing loss. Taking a trace on layer L3 as an example, layers L2 and L4 can generally be referenced, with the impedance line width being K1. Interlayer referencing can be used with an upper interlayer reference of L1 and / or a lower interlayer reference of L5, in which case the impedance line width is K2, where K2 > K1. This thickening of the impedance line width reduces PCB routing loss. The disadvantage of this solution is that there cannot be any traces in the projection area of ​​the PCB routing on layers L2 and / or L4. Furthermore, ground planes are required in the projection areas of layers L1 and / or L5, occupying more PCB layers and reducing the routing space for non-ground traces.

[0024] Therefore, when the entire routing layer is a reference layer that serves as a reference for placing signal traces, non-ground lines cannot be placed on the routing layer between the routing layer where signal traces are placed and the reference layer. This encroaches on the routing space of non-ground lines and occupies more routing layers on the PCB.

[0025] Based on this, such as Figures 1 to 3 As shown, a first aspect of this disclosure provides a wiring structure 100, including a plurality of wiring layers 10, with an insulating layer 40 disposed between the plurality of wiring layers 10. For example, the insulating layer 40 may be made of FR-4 (Flame Retardant 4) material or other dielectric material. The plurality of wiring layers 10 includes at least one first wiring layer 11 having a first line 20, the first line 20 including a first line segment 21 and at least one second line segment 22.

[0026] It should be noted that the first line 20 is a signal trace, for example, it can be a trace for radio frequency / high-speed signal transmission.

[0027] In the above embodiments, the width of the second line segment 22 is configured to be determined with reference to the second wiring layer 12, which is the most adjacent wiring layer 10 to the first wiring layer 11; and the width of the first line segment 21 is configured to be determined with reference to the third wiring layer 13, which is the second most adjacent wiring layer 10 to the first wiring layer 11. In this way, for the first line 20 arranged in the first wiring layer 11, the most adjacent wiring layer 10 and the second most adjacent wiring layer 10 of the first wiring layer 11 can be flexibly taken as the reference layer in the case of constant impedance, and when the non-ground line 60 needs to be arranged in the partial area in the second most adjacent wiring layer 10 of the first wiring layer 11, the most adjacent wiring layer 10 of the first wiring layer 11 can be taken as the reference layer, thereby effectively saving the PCB wiring space, reducing the influence on the arrangement of the non-ground line 60, making the line arrangement more flexible, and reducing the number of occupied PCB wiring layers.

[0028] It should be understood that the most adjacent wiring layer 10 of the first wiring layer 11 mentioned above is the wiring layer 10 most adjacent to the first wiring layer 11 in the stacking direction of the plurality of wiring layers 10, which can be the wiring layer 10 most adjacent to the first wiring layer 11 on one side (above) in the stacking direction, or the wiring layer 10 most adjacent to the first wiring layer 11 on the opposite side (below) in the stacking direction.

[0029] For example, when the L layer is taken as the first wiring layer 11, the L+1 layer and / or the L-1 layer is the most adjacent wiring layer 10 of the first wiring layer 11, i.e., the second wiring layer 12, and the L+2 layer and / or the L-2 layer is the second most adjacent wiring layer 10 of the first wiring layer 11, i.e., the third wiring layer 13.

[0030] In some embodiments, as shown in FIGS. 1A and 1B, the first line segment 21 is taken as the reference layer of the second most adjacent wiring layer 10 of the first wiring layer 11, and the second line segment 22 is taken as the reference layer of the most adjacent wiring layer 10 of the first wiring layer 11, i.e., the distance between the first line segment 21 and the corresponding reference layer is greater than the distance between the second line segment 22 and the corresponding reference layer, and the width of the first line segment 21 is greater than the width of the second line segment 22, so that the impedance of the first line segment 21 and the second line segment 22 of the first line 20 is constant. Figure 1 and Figure 2 In addition, the width of the first line segment 21 in the first line 20 is determined with reference to the second most adjacent wiring layer 10 of the first wiring layer 11, so that the width of the first line segment 21 is large, thereby reducing the wiring loss.

[0031] In addition, the width of the first line segment 21 in the first line 20 is determined with reference to the second most adjacent wiring layer 10 of the first wiring layer 11, so that the width of the first line segment 21 is large, thereby reducing the wiring loss.

[0032] In some embodiments, the area of the third wiring layer 13 corresponding to the first line segment 21 needs to be paved, which is the local ground area (forming the reference plane) in the third wiring layer 13. For details, please refer to the part with cross-section lines in the first area 50 of the third wiring layer 13 in Figure 1 and Figure 2 . Similarly, the area of the second wiring layer 12 corresponding to the second line segment 22 also needs to be paved, which is the local ground area (forming the reference plane) in the second wiring layer 12. For details, please refer to the part with cross-section lines in the first area of the second wiring layer 12 in Figure 1 and Figure 2 .

[0033] It should be understood that when the first line segment 21 of the first wiring layer 11 is arranged with the third wiring layer 13 as the reference layer of the determined width, there should be an insulating medium layer between the first line segment 21 and the third wiring layer 13, and no line can be arranged.

[0034] In some embodiments, the second wiring layer 12 and the third wiring layer 13 can be connected through the reflow ground hole 30, which can connect the local ground area in the third wiring layer 13 corresponding to the first line segment 21 and the local ground area in the second wiring layer 12 corresponding to the second line segment 22. In this way, the local ground areas in the different reference layers corresponding to the first line 20 can be connected, that is, the local ground areas (ground planes) of the second wiring layer 12 and the third wiring layer 13 corresponding to the first line 20 are connected, forming a low-impedance reflow path and reducing the risk of signal resonance.

[0035] At the same time, since the reference layer corresponding to the second line segment 22 is arranged in the second wiring layer 12, the space area at the third wiring layer 13 on the same side can be used to arrange the non-ground line 60, improving the flexibility of wiring and saving the number of layers and thickness of the PCB.

[0036] It should be understood that the number of the above-mentioned reflow ground hole 30 can be multiple, which can connect the local ground areas of the different reference layers corresponding to the first line 20, which is not limited here.

[0037] In some embodiments, the position of the reflow ground hole 30 can be set arbitrarily according to actual needs. For example, as shown in Figure 1 and Figure 2 , the reflow ground hole 30 can be arranged at the joint of the first line segment 21 and the second line segment 22 and located on the opposite sides of the first line 20. In this way, a complete and low-impedance path can be constructed for the return current of the first line 20, thereby minimizing the current loop area and ensuring signal integrity and controlling electromagnetic interference.

[0038] In some embodiments, the first line 20 comprises a single-ended impedance line or a differential line. A single-ended impedance line is a line that transmits a signal only through one conductor with a reference plane (GND or Power layer) as "ground", and the signal voltage is referenced to the reference plane (i.e. signal voltage = potential difference between the line and the reference plane). A differential line is composed of two parallel, equal-length, equal-width, and equal-interval conductors, and the signal is transmitted in the form of "differential voltage" (i.e. signal voltage = line 1 voltage - line 2 voltage), without explicit dependence on a single layer reference plane (but usually still needs the reference plane to assist backflow).

[0039] In addition, it should be understood that an insulating layer 40 is provided between two adjacent wiring layers 10, wherein the insulating layer 40 can be made of an insulating dielectric material commonly used in PCBs (printed circuit boards). For example, FR-4 (Flame Retardant 4, flame-retardant epoxy glass cloth substrate, flame-retardant grade 4) can be used, and other materials disclosed in related technologies can also be used, which will not be described here.

[0040] In some embodiments, the number of first line segments 21 and second line segments 22 of the first line 20 can be multiple, according to the different number of regions in which the non-ground line 60 needs to be arranged in the next adjacent wiring layer 10 (i.e. the third wiring layer 13) of the first wiring layer 11. For example, the first line 20 can include one first line segment 21 and one second line segment 22, or the first line 20 can include one first line segment 21 and two or more second line segments 22, or the first line 20 can include one second line segment 22 and two or more first line segments 21, or the first line 20 can include multiple first line segments 21 and multiple second line segments 22. Therefore, the number of first line segments 21 and second line segments 22 of the first line 20 can be determined according to the overall design of the wiring structure, which is within the protection scope of the present disclosure.

[0041] When the first line 20 arranged in the first wiring layer 11 includes multiple first line segments 21 and multiple second line segments 22, the multiple first line segments 21 all take the third wiring layer 13 (next adjacent to the first wiring layer 11) as the reference layer, and the multiple second line segments 22 all take the second wiring layer 12 (most adjacent to the first wiring layer 11) as the reference layer, wherein the third wiring layer 13 includes multiple local grounding regions (forming a reference plane) corresponding to the first line segments 21, and the second wiring layer 12 includes multiple local grounding regions (forming a reference plane) corresponding to the second line segments 22, and the multiple local grounding regions in the third wiring layer 13 and the multiple local grounding regions in the second wiring layer 12 can be connected through the backflow via holes 30, which will not be described here.

[0042] In addition, it should be understood that the first line 20 can be a high-frequency signal line for transmitting a high-frequency signal, such as a radio frequency signal, a video signal, or a high-speed digital signal, and the like, which will not be described herein.

[0043] The second aspect of the present disclosure also provides a wiring method, which comprises: arranging a plurality of wiring layers, wherein the plurality of wiring layers comprises at least one first wiring layer having a first line.

[0044] The arrangement of the first wiring layer comprises the following steps.

[0045] The width of the second line segment of the first line is determined with reference to a second wiring layer, wherein the second wiring layer is the most adjacent wiring layer to the first wiring layer.

[0046] The width of the first line segment of the first line is determined with reference to a third wiring layer, wherein the third wiring layer is the second adjacent wiring layer to the first wiring layer.

[0047] In the method, the first line 20 can be arranged in the first wiring layer 11, and when the first line 20 is arranged in the first wiring layer 11, the width of the second line segment 22 of the first line 20 can be determined with reference to the second wiring layer 12, which is the most adjacent wiring layer to the first wiring layer 11, and the width of the first line segment 21 of the first line 20 can be determined with reference to the third wiring layer 13, which is the second adjacent wiring layer to the first wiring layer 11. In this way, the wiring method can more flexibly adjust the reference layer of the first line 20 arranged in the first wiring layer 11, and when a part of the second adjacent wiring layer 10 of the first wiring layer 11 needs to be provided with a non-ground line 60 and cannot be used as a reference plane, the most adjacent wiring layer 10 of the first wiring layer 11 can be used as the reference layer of the first line 20, thereby saving the space occupied by the PCB wiring, reducing the influence on the arrangement of the non-ground line 60, improving the flexibility of the wiring, and saving the number of wiring layers of the PCB.

[0048] In some embodiments, the first line segment 21 is determined with reference to the third wiring layer 13, the second line segment 22 is determined with reference to the second wiring layer 12, and in the stacking direction of the wiring structure 100, the distance between the third wiring layer 13 and the first wiring layer 11 is greater than the distance between the second wiring layer 12 and the first wiring layer 11. Therefore, the width of the first line segment 21 is set to be greater than the width of the second line segment 22, so that the impedance of the first line segment 21 and the second line segment 22 can be kept unchanged.

[0049] In addition, the width of the first line segment 21 in the first line 20 is determined with reference to the next adjacent wiring layer 10 of the first wiring layer 11, so that the width of the first line segment 21 is higher to adapt to the same target impedance and reduce the wiring loss.

[0050] In some embodiments, the wiring method further comprises: arranging a reflow via hole 30 between the second wiring layer 12 and the third wiring layer 13; and connecting the second wiring layer 12 and the third wiring layer 13 through the reflow via hole 30.

[0051] In the method, the third wiring layer 13 is the reference layer for determining the first line segment 21 of the first line 20, and the second wiring layer 12 is the reference layer for determining the second line segment 22 of the first line 20. Therefore, the area (reference plane) corresponding to the first line segment 21 in the third wiring layer 13 needs to be paved, which is a local ground area in the third wiring layer 13. The area corresponding to the second line segment 22 in the second wiring layer 12 also needs to be paved, which is a local ground area in the second wiring layer 12. By arranging the reflow via hole 30 between the third wiring layer 13 and the second wiring layer 12, the local ground area (ground plane) in the third wiring layer 13 and the local ground area (ground plane) in the second wiring layer 12 can be electrically connected to form a low-impedance reflow path, thereby reducing the risk of signal resonance.

[0052] In some embodiments, the reflow via hole 30 is arranged at the joint of the first line segment 21 and the second line segment 22 and located on opposite sides of the first line. In this way, a complete and low-impedance path can be formed for the return current of the first line 20, thereby minimizing the current loop area and ensuring signal integrity and controlling electromagnetic interference.

[0053] In some embodiments, the first line 20 comprises a single-ended impedance line or a differential line, which can be specifically referred to the embodiments of the wiring structure described above and is not limited herein.

[0054] In some embodiments, the method further comprises arranging an insulating layer 40 between two adjacent wiring layers 10. As described in the embodiments of the wiring structure 100 of the present disclosure, the insulating layer 40 can be made of an insulating dielectric material commonly used in PCBs (printed circuit boards). For example, FR-4 (Flame Retardant 4) material can be used, which is not described herein again.

[0055] In order to more clearly describe the wiring method, examples will be given below.

[0056] For example, reference can be made to Figures 1 to 3As shown, the first line 20 is arranged at the Lth layer counted from the top layer of the wiring structure 100, that is, the Lth layer is the first wiring layer 11, and the first line 20 is preferably referenced by a layer above or below the Lth layer. When L = 1 or 2, the reference layer is the L+2th layer, that is, the L+2th layer is the third wiring layer 13. When L > 2, the reference layer can be the L-2th layer, that is, the L-2th layer is the third wiring layer 13. The reference layer can also be the L+2th layer, that is, the L+2th layer is the third wiring layer 13. Alternatively, the reference layer can be both the L+2th layer and the L-2th layer, that is, the L+2th layer and the L-2th layer are both the third wiring layer 13. The line width of the first line 20 determined by the reference layer is W2, and the part of the first line 20 determined by the reference layer can be the first line segment 21. The L+2th layer and / or the L-2th layer corresponding to the first line segment 21 needs to be grounded to form a local ground area (a reference plane).

[0057] Reference is made to Figures 1 to 3 As shown, the wiring layers 10 of the wiring structure 100 are stacked together, and an insulating layer 40 is arranged between adjacent wiring layers 10, wherein, Figure 3 The first area 50 shown in the middle is arranged along the stacking direction of the wiring layers 10 in the wiring structure 100. When the first line 20 passes through the first area 50, the L+2th layer and / or the L-2th layer needs to handle the non-ground line 60 (for example, Figure 1 and Figure 2 In the third wiring layer 13, the first area 50 is arranged with the non-ground line 60), the first line 20 in the first area 50 can be referenced by the L+1th layer and / or the L-1th layer to determine the line width, the line width of the part of the first line 20 corresponding to the first area 50 can be W1 to ensure that the impedance of the first line 20 does not change (W1 < W2), and the part of the first line 20 in the first area 50 can be the second line segment 22 of the first line 20. Meanwhile, the L+1th layer and / or the L-1th layer of the first area 50 needs to be grounded to form a local ground area.

[0058] At the junction of the change of the reference plane of the first line 20, a backflow ground hole 30 is added to connect the local ground areas of the corresponding different reference layers of the first line 20 to reduce the wiring loss of the PCB. For example, when the reference layers of the first line segment 21 are L+2 and L-2, and the reference layers of the second line segment 22 are L+1 and L-1, at least one backflow ground hole 30 is added to connect the local ground area of the L+2th layer and the local ground area of the L+1th layer, and another backflow ground hole 30 is added to connect the local ground area of the L-1th layer and the local ground area of the L-1th layer.

[0059] In addition, as can be seen from the above, the second wiring layer 12 and the third wiring layer 13 are located on the same side or different sides of the first wiring layer 11 in the stacking direction of the wiring structure, which is not limited here.

[0060] In some embodiments, the first wiring layer 11 is arranged on the first line 20, and the reference layer for determining the width of the first line segment 21 is a next-nearest reference layer, i.e., the third wiring layer 13, that is, the first line segment 21 uses a barrier reference, so that the medium thickness between the first line segment 21 and the corresponding reference layer is thicker, thereby making the width of the first line segment 21 wider to reduce the loss, and the reference layer for determining the width of the second line segment 22 is the nearest reference layer, i.e., the second wiring layer 12, which can leave the area of the corresponding third wiring layer 13 of the second line segment 22 to arrange the non-ground line 60 in the area, avoiding the area being occupied when the first line 20 is arranged and needing to select another reference layer, thereby saving wiring space.

[0061] The third aspect of the present disclosure provides a circuit board, which can include the wiring structure 100 described above, wherein the wiring structure 100 can include the wiring structure 100 provided by the first aspect of the present disclosure, or the wiring structure formed by the wiring method provided by the second aspect of the present disclosure. It should be noted that the circuit board further includes an insulating layer 40 between each wiring layer of the wiring structure, which can be referred to in related technologies and will not be described here. The circuit board can reduce wiring loss and save wiring space, which will not be described here.

[0062] In some embodiments, the wiring structure 100 has a first area 50, and the third wiring layer 13 is provided with a non-ground line 60 at a position corresponding to the first area 50 to make full use of the wiring space of the circuit board.

[0063] The preferred embodiments of the present disclosure are described in detail above with reference to the drawings, but the present disclosure is not limited to the specific details in the above-described embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

[0064] In addition, it should be noted that each specific technical feature described in the above-described specific embodiments can be combined in any appropriate manner without contradiction, and in order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0065] In addition, various different embodiments of the present disclosure can also be combined in any appropriate manner, as long as they do not deviate from the idea of the present disclosure, and they should also be considered as disclosed by the present disclosure.

Claims

1. A wiring structure, characterized in that, include: Multiple wiring layers, wherein the multiple wiring layers include at least one first wiring layer having a first line; The first line includes a first line segment and at least one second line segment; The width of the second line segment is configured to be determined with the second wiring layer as a reference plane, wherein the second wiring layer is the wiring layer that is closest to the first wiring layer; The width of the first line segment is configured to be determined with reference to the third wiring layer, wherein the third wiring layer is the wiring layer adjacent to the first wiring layer.

2. The wiring structure according to claim 1, characterized in that, The width of the first line segment is greater than the width of the second line segment.

3. The wiring structure according to claim 1, characterized in that, The second wiring layer and the third wiring layer are connected through a return ground via.

4. The wiring structure according to claim 3, characterized in that, The return ground hole is arranged at the junction of the first line segment and the second line segment, and is located on opposite sides of the first line.

5. The wiring structure according to claim 1, characterized in that, The first line includes a single-ended impedance line or a differential line.

6. The wiring structure according to any one of claims 1-5, characterized in that, An insulating layer is provided between two adjacent wiring layers.

7. A wiring method, characterized in that, The method includes: Multiple wiring layers are arranged, wherein at least one of the multiple wiring layers includes a first wiring layer having a first line; Arranging the first wiring layer includes: The width of the second line segment of the first line is determined with the second wiring layer as a reference plane; wherein, the second wiring layer is the wiring layer that is closest to the first wiring layer; The width of the first line segment of the first line is determined with the third wiring layer as a reference plane, wherein the third wiring layer is a wiring layer adjacent to the first wiring layer.

8. The wiring method according to claim 7, characterized in that, The width of the first line segment is greater than the width of the second line segment.

9. The wiring method according to claim 7, characterized in that, The method further includes: A return ground via is disposed between the second wiring layer and the third wiring layer; The second wiring layer and the third wiring layer are connected through the return ground via.

10. The wiring method according to claim 9, characterized in that, The return ground hole is arranged at the junction of the first line segment and the second line segment, and is located on opposite sides of the first line.

11. The wiring method according to claim 7, characterized in that, The first line includes a single-ended impedance line or a differential line.

12. The wiring method according to claim 7, characterized in that, The method further includes: An insulating layer is arranged between two adjacent wiring layers.

13. A circuit board, comprising a wiring structure, characterized in that, The wiring structure includes the wiring structure described in any one of claims 1-6; or is formed using the wiring method described in any one of claims 7-12.

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