Forming method of hybrid bonding structure and hybrid bonding structure

Abstract

The invention provides a forming method of a hybrid bonding structure and the hybrid bonding structure. The forming method of the hybrid bonding structure comprises the step of forming a rewiring wafer. The rewiring wafer comprises a substrate, a first dielectric layer and a rewiring layer which are stacked in sequence. Wherein a prefabricated through hole structure is formed in the first dielectric layer; the prefabricated through hole structure penetrates through part of the first dielectric layer from the upper surface of the first dielectric layer. And bonding the rewiring layer of the rewiring wafer with the first wafer. And removing the substrate of the rewiring wafer. And etching the lower surface of the first dielectric layer, and depositing to form a first contact bonding pad. Wherein the first contact bonding pad is in contact with the prefabricated through hole structure to form a first hybrid bonding structure; the first contact pad and the prefabricated through hole structure are aligned in the vertical direction. And bonding the first wafer and the second wafer through the first hybrid bonding structure. When the rewiring wafer is formed, the prefabricated through hole structure is formed in advance, and alignment deviation caused by wafer deformation or process fluctuation after bonding is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor packaging technology, and in particular to a forming method of a hybrid bonding structure and the hybrid bonding structure. BACKGROUND

[0002] With the development of integrated circuit technology towards three-dimensional integration, hybrid bonding technology has become an important means to realize high-density interconnection between chips. Through accurate alignment and connection at wafer level, this technology can effectively improve the signal transmission efficiency and wiring flexibility in chip stacking structure, and is widely used in high-performance computing, storage expansion and other scenarios.

[0003] In the prior art, a redistribution layer (RDL) is usually used to provide additional wiring resources for a three-dimensional stacking structure, and a via structure is used to realize electrical connection between upper and lower layers. However, in actual process, the alignment accuracy of the via structure and the redistribution layer is strict, and the traditional "via preparation after bonding" process is prone to alignment deviation caused by wafer deformation due to bonding, which makes it difficult to realize accurate alignment in the vertical direction, and further causes poor interconnection stability and low process yield. SUMMARY

[0004] The embodiments of the present application provide a forming method of a hybrid bonding structure and the hybrid bonding structure. In the forming of a redistribution wafer, a pre-via structure is formed in advance to avoid alignment deviation caused by wafer deformation or process fluctuation after bonding.

[0005] The technical solutions of the embodiments of the present application are implemented as follows: The embodiments of the present application provide a forming method of a hybrid bonding structure, which comprises: forming a redistribution wafer; the redistribution wafer comprises: a substrate, a first dielectric layer and a redistribution layer stacked in sequence; wherein a pre-via structure is formed in the first dielectric layer; the pre-via structure penetrates the first dielectric layer from the upper surface of the first dielectric layer; bonding the redistribution layer of the redistribution wafer with a first wafer; removing the substrate of the redistribution wafer; etching the lower surface of the first dielectric layer and depositing to form a first contact pad; wherein the first contact pad is in contact with the pre-via structure to form a first hybrid bonding structure; the first contact pad and the pre-via structure are aligned in the vertical direction; and bonding the first wafer with a second wafer through the first hybrid bonding structure.

[0006] In some embodiments of the present disclosure, the method of forming the re-wiring wafer comprises: depositing the first dielectric layer on the substrate; etching an upper surface of the first dielectric layer to form a first via; filling a metal material in the first via to form the pre-fabricated via structure; depositing a second dielectric layer on the first dielectric layer; etching an upper surface of the second dielectric layer and filling to form the re-wiring layer, thereby forming the re-wiring wafer.

[0007] In some embodiments of the present disclosure, a cross-section of the first via is T-shaped; the first via comprises a straight hole and a trench which are in communication with each other along the vertical direction; wherein a width of the trench along a first direction is greater than a hole diameter of the straight hole; the first direction is perpendicular to the vertical direction.

[0008] In some embodiments of the present disclosure, the pre-fabricated via structure is formed by filling in the first via through a double damascene process.

[0009] In some embodiments of the present disclosure, the re-wiring wafer further comprises: a release modification layer and a third dielectric layer stacked in sequence; the release modification layer and the third dielectric layer are located between the substrate and the first dielectric layer; the removing the substrate of the re-wiring wafer comprises: removing the release modification layer by a pyrolytic bonding process to separate the substrate and the third dielectric layer; removing the third dielectric layer remaining on the first dielectric layer by etching.

[0010] In some embodiments of the present disclosure, the re-wiring wafer further comprises: a buffer layer and a thin film layer stacked in sequence; the buffer layer and the thin film layer are located between the substrate and the first dielectric layer.

[0011] In some embodiments of the present disclosure, the removing the substrate of the re-wiring wafer further comprises: thinning the substrate by a grinding process; removing the substrate by a chemical mechanical polishing process.

[0012] In some embodiments of the present disclosure, before the bonding the first wafer and the second wafer, the method of forming the hybrid bonding structure further comprises: etching a lower surface of the first dielectric layer and depositing to form a virtual pad; wherein the virtual pad is located between two first contact pads adjacent along a first direction; the first direction is perpendicular to the vertical direction.

[0013] In some embodiments of the present disclosure, the bonding the redistribution layer of the redistribution wafer to the first wafer comprises: etching an upper surface of the second dielectric layer to form a second via; the second via exposes part of the redistribution layer; filling the second via to form a second contact pad, thereby forming a second hybrid bonding structure; the second hybrid bonding structure is in contact with the redistribution layer; and the redistribution layer of the redistribution wafer is bonded to the first wafer through the second hybrid bonding structure.

[0014] The present disclosure also provides a hybrid bonding structure, comprising: a first wafer and a redistribution wafer; the redistribution wafer comprises: a first dielectric layer and a redistribution layer stacked in sequence; wherein a preformed via structure is formed in the first dielectric layer; the preformed via structure is formed before the redistribution layer of the redistribution wafer is bonded to the first wafer; the preformed via structure penetrates part of the first dielectric layer from an upper surface of the first dielectric layer; a first contact pad is also formed in the first dielectric layer; the first contact pad penetrates part of the first dielectric layer from a lower surface of the first dielectric layer; the first contact pad is in contact with the preformed via structure, constituting a first hybrid bonding structure; the first contact pad and the preformed via structure are aligned in a vertical direction; the redistribution layer of the redistribution wafer is bonded to the first wafer; and the first dielectric layer of the redistribution wafer is bonded to a second wafer.

[0015] The present disclosure has the following beneficial effects: when forming the redistribution wafer, the first dielectric layer is prepared in advance, and the preformed via structure is formed in the first dielectric layer. Compared with forming the first dielectric layer after the redistribution wafer is bonded to the first wafer, the surface structure of the redistribution wafer before bonding is simple without complex functional layers, and a first dielectric layer film with good thickness consistency can be obtained through a deposition process. Meanwhile, the preformed via structure is formed in advance on the first dielectric layer with good thickness consistency, which can avoid alignment deviation caused by wafer deformation or process fluctuation after multiple bonding, thereby improving the alignment accuracy.

[0016] In addition, after forming the redistribution wafer, the redistribution layer of the redistribution wafer is bonded to the first wafer, and then the substrate of the redistribution wafer is removed, so that only the redistribution layer is bonded to the surface of the first wafer. The redistribution layer provides high-density signal redistribution and I / O (input / output) port expansion functions for the first wafer, while avoiding the thickness redundancy, thermal resistance and cost problems caused by the substrate. Finally, the first hybrid bonding structure is prepared on the exposed surface of the redistribution layer, and the first hybrid bonding structure is used to realize high-precision bonding with the second wafer, thereby improving the signal transmission efficiency and interconnection reliability in packaging. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort. Figure 1 is a flow diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 1 ; Figure 2 is a flow diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 2 ; Figure 3 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 1 ; Figure 4 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 2 ; Figure 5 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 3 ; Figure 6 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 4 ; Figure 7 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 5 ; Figure 8 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 6 ; Figure 9 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 7 ; Figure 10 is a structural diagram of the method for forming the hybrid bonding structure provided by the embodiments of the present application Figure 8 . DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will further describe the specific technical solutions of the present application with reference to the drawings in the embodiments of the present application. The following embodiments are used to illustrate the embodiments of the present application, but not to limit the scope of the embodiments of the present application.

[0019] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets as each other and as all possible embodiments, and that "some embodiments" can be combined with each other, without conflict, unless otherwise indicated.

[0020] In the following description, the terms "first\second\third" are merely used to distinguish similar objects, and do not represent a specific order or sequence of the objects. It is to be understood that the "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0021] In this document, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element, or there can be intervening layers / elements between them. Also, in one orientation, a layer / element is "on" another layer / element, when reversed, it can be "under" the other layer / element.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. The terminology used in this document is for the purpose of describing embodiments only and is not intended to be limiting of the embodiments.

[0023] In a conventional process, when a redistribution layer 131 needs to be bonded to the surface of a wafer to be bonded (i.e. the first wafer 20 described herein), the following steps need to be performed in sequence: first, bond the redistribution wafer 10 to the wafer to be bonded (i.e. the first wafer 20 described herein), and remove the substrate 11 of the redistribution wafer 10; then, deposit a dielectric layer on the exposed surface of the redistribution layer 131; and finally, prepare a hybrid bonding structure comprising a via and a pad on the dielectric layer.

[0024] In the present application, when the redistribution wafer 10 is prepared, that is, before the redistribution wafer 10 is bonded to the first wafer 20, a first dielectric layer 12 is prepared in advance, and a pre-prepared via structure 121 is prepared in the first dielectric layer 12.

[0025] The embodiments of the present application provide a method for forming a hybrid bonding structure, referring to Figure 1 The method for forming a hybrid bonding structure comprises Figure 1 The steps S101-S105 shown will be described in combination.

[0026] S101: Form a redistribution wafer.

[0027] In the embodiments of the present disclosure, referring to Figure 6As shown, the redistribution wafer 10 is formed. The redistribution wafer 10 comprises: a substrate 11, a first dielectric layer 12 and a redistribution layer 131 stacked in sequence. Among them, the first dielectric layer 12 is formed with a pre-prepared via structure 121; the pre-prepared via structure 121 penetrates the first dielectric layer 12 from the upper surface of the first dielectric layer 12. When the first dielectric layer 12 is formed on the surface of the substrate 11, because there is no complex functional layer (such as the redistribution layer) on the surface of the redistribution wafer 10 at this time, the structure is simple and has high flatness, and the first dielectric layer 12 film with good thickness consistency can be prepared by deposition process. The first dielectric layer 12 has good consistency, so that it can accurately control the depth, aperture and sidewall morphology of the pre-prepared via structure 121 in the process of forming the pre-prepared via structure 121, avoiding defects such as etching residue and sidewall tilt, and further ensuring the accurate alignment of the pre-prepared via structure 121 and the redistribution layer 131.

[0028] It should be noted that the redistribution wafer 10 is an advanced chip packaging technology, which "reproduces" one or more new metal line layers on the surface of the silicon wafer through semiconductor process, so as to redistribute the pads with small spacing on the wafer to positions with larger spacing and more reasonable layout, thereby facilitating electrical connection with the outside.

[0029] S102: Bonding the redistribution layer of the redistribution wafer with the first wafer.

[0030] In the embodiments of the present disclosure, referring to Figure 8 As shown, the redistribution wafer 10 is bonded with the first wafer 20 by a hybrid bonding process. The hybrid bonding process can realize high-density, low-resistance and low-delay interconnection, and is suitable for advanced packaging applications such as high-performance computing chips and storage chips.

[0031] S103: Removing the substrate of the redistribution wafer.

[0032] In the embodiments of the present disclosure, referring to Figure 8 and Figure 9 As shown, the removal method can select different processes according to the composite film structure (film between the substrate 11 and the redistribution layer 131), such as using grinding, chemical mechanical polishing, wet etching or pyrolytic bonding.

[0033] S104: Etching the lower surface of the first dielectric layer and depositing to form a first contact pad. The first contact pad is in contact with the pre-prepared via structure and constitutes a first hybrid bonding structure; the first contact pad and the pre-prepared via structure are aligned in the vertical direction.

[0034] In the embodiments of the present disclosure, referring to Figure 10As shown, the first contact pad 122 is formed by etching the lower surface of the first dielectric layer 12 and depositing a metal material (such as copper, aluminum, etc.). The structure of the first contact pad 122 improves the bonding accuracy and enhances the electrical conductivity and mechanical strength of the interface.

[0035] S105: Bond the first wafer to the second wafer through the first hybrid bonding structure.

[0036] In the embodiments of the present disclosure, the first hybrid bonding structure 30 is used to bond the first wafer 20 to the second wafer, and the bonding process can be performed in a high-vacuum environment to reduce the influence of impurities and oxides. Figure 10 As shown, the first hybrid bonding structure 30 makes the hybrid bonding between the first wafer 20 and the second wafer more stable and reliable, and the hybrid bonding process can be performed in a high-vacuum environment to reduce the influence of impurities and oxides.

[0037] It can be understood that, when the re-distribution wafer 10 is formed, the first dielectric layer 12 is prepared in advance, and the pre-formed via structure 121 is formed in the first dielectric layer 12. Compared with forming the first dielectric layer 12 after the re-distribution wafer 10 is bonded to the first wafer 20, the surface structure of the re-distribution wafer 10 before bonding is simple and does not have complex functional layers, and the first dielectric layer 12 film with good thickness consistency can be obtained through a deposition process. At the same time, the pre-formed via structure 121 is formed on the first dielectric layer 12 with good thickness consistency, which can avoid the alignment deviation caused by the deformation of the wafer after multiple bonding or process fluctuations, and improve the alignment accuracy.

[0038] In addition, after the re-distribution wafer 10 is formed, the re-distribution layer 131 of the re-distribution wafer 10 is bonded to the first wafer 20, and then the substrate 11 of the re-distribution wafer 10 is removed, so that only the re-distribution layer 131 is bonded to the surface of the first wafer 20. The re-distribution layer 131 provides the first wafer 20 with high-density signal redistribution and I / O (input / output) port expansion functions, while avoiding the thickness redundancy, thermal resistance, and cost problems caused by the substrate 11. Finally, the first hybrid bonding structure 30 is prepared on the exposed surface of the re-distribution layer 131, and the first hybrid bonding structure 30 is used to bond the second wafer with high accuracy, thereby improving the signal transmission efficiency and interconnection reliability in packaging.

[0039] In some embodiments of the present disclosure, the method for forming the re-distribution wafer 10 includes Figure 2 The steps S201-S205 are shown. Each step will be described.

[0040] S201: Deposit a first dielectric layer on a substrate.

[0041] In the embodiments of the present disclosure, the first hybrid bonding structure 30 is used to bond the first wafer 20 to the second wafer, and the bonding process can be performed in a high-vacuum environment to reduce the influence of impurities and oxides. Figure 3As shown, a first dielectric layer 12 is deposited on the substrate 11. The first dielectric layer 12 is usually made of silicon oxide or other semiconductor insulating materials, and is used for preparing the pre-punch structure 121 later.

[0042] S202: etching the upper surface of the first dielectric layer to form a first via.

[0043] In the embodiments of the present disclosure, refer to Figure 4 As shown, the first via for subsequent metal filling is formed on the upper surface of the first dielectric layer 12 by selective etching of the first dielectric layer 12. The size and depth of the first via are determined according to design requirements, and usually need to be accurately controlled to ensure the alignment accuracy of subsequent wiring.

[0044] S203: filling a metal material in the first via to form a pre-punch structure.

[0045] In the embodiments of the present disclosure, refer to Figure 5 As shown, the pre-punch structure 121 is formed by filling a metal material in the first via. The filling material is usually a metal material with excellent conductivity such as copper (Cu) or aluminum (Al), which is coated to the corresponding position by an electroplating process. The pre-punch structure 121 can be used as a positioning reference during hybrid bonding, improving the alignment accuracy and thus enhancing the overall performance after stacking.

[0046] S204: depositing a second dielectric layer on the first dielectric layer.

[0047] In the embodiments of the present disclosure, refer to Figure 6 As shown, a second dielectric layer 13 is deposited on the first dielectric layer 12. The second dielectric layer 13 is also made of insulating materials, which is used for preparing a redistribution layer 131 electrically connected to the pre-punch structure 121 and as a support layer for the subsequent redistribution layer 131.

[0048] S205: etching the upper surface of the second dielectric layer and filling to form a redistribution layer, thereby forming a redistribution wafer.

[0049] In the embodiments of the present disclosure, refer to Figure 6 As shown, the wiring groove is formed on the second dielectric layer 13 by etching, and then the redistribution layer 131 is formed by metal filling. The patterning design of the redistribution layer 131 can be flexibly adjusted according to the actual wiring requirements to optimize the signal path, reduce the delay and improve the wiring density. The formation process of the redistribution layer 131 can adopt a dual damascene process to simplify the process flow, reduce the cost and yield loss.

[0050] In some embodiments of the present disclosure, refer to Figure 7As shown, the first via has a T-shaped cross section. The first via includes a straight hole and a trench that are in communication with each other along the vertical direction Z. The trench has a width along the first direction X that is greater than the diameter of the straight hole; the first direction X is perpendicular to the vertical direction Z.

[0051] It should be noted that, referring to Figure 7 As shown, the first via is composed of two parts that are in communication with each other: one part is a straight hole that extends along the vertical direction Z through the first dielectric layer 12, and the other part is a trench that extends laterally above the straight hole. The diameter of the straight hole is usually small, and if it is directly aligned with the redistribution layer 131, alignment errors are likely to occur. By designing a wider trench at the end of the straight hole, the lateral dimension of the upper end of the straight hole is expanded, forming a "surface contact" rather than a "point contact". When subsequently aligned with the redistribution layer, as long as the alignment mark can be ensured to fall within the wider trench, electrical connection with the underlying straight hole can be ensured. The wider trench above the straight hole can effectively improve the alignment accuracy and increase the process design window.

[0052] In some embodiments of the present disclosure, the first via is filled by a double damascene process to form a pre-prepared via structure 121.

[0053] It should be noted that, referring to Figure 7 As shown, the straight hole and the trench are formed simultaneously in the same process flow by a double damascene process, simplifying the process flow and reducing costs and yield loss.

[0054] In some embodiments of the present disclosure, referring to Figure 7 As shown, the redistribution wafer 10 further includes a separation modification layer 15 and a third dielectric layer 16 that are stacked in sequence. The separation modification layer 15 and the third dielectric layer 16 are located between the substrate 11 and the first dielectric layer 12. Removing the substrate 11 of the redistribution wafer 10 includes steps S301-S302, which will be described in combination.

[0055] S301: The separation modification layer is removed by a pyrolytic bonding process to separate the substrate and the third dielectric layer.

[0056] In embodiments of the present disclosure, referring to Figure 8 and Figure 9 As shown, the separation modification layer 15 is used to achieve controlled separation of the substrate 11, avoiding damage to the wafer caused by mechanical grinding or chemical etching. The separation modification layer 15 is usually made of silicon oxide, silicon nitride or other composite materials with low bonding force. By heating, the separation modification layer 15 undergoes thermal decomposition, thereby destroying the adhesion between the separation modification layer 15 and the substrate 11, and achieving physical separation of the separation modification layer 15 and the substrate 11. The separated silicon substrate 11 can be reused for the preparation of the redistribution wafer 10, reducing costs.

[0057] S302: Remove the remaining third dielectric layer on the first dielectric layer by etching.

[0058] In the embodiments of the present disclosure, as shown in Figure 8 and Figure 9 As shown in the embodiments of the present disclosure, after the removal of the modified layer 15, part of the third dielectric layer 16 may remain on the first dielectric layer 12, and the remaining third dielectric layer 16 on the first dielectric layer 12 needs to be removed by etching.

[0059] In some embodiments of the present disclosure, as shown in Figure 7 As shown in the embodiments of the present disclosure, the redistribution wafer 10 further comprises a buffer layer 14 and a thin film layer 17 stacked in sequence. The buffer layer 14 and the thin film layer 17 are located between the substrate 11 and the first dielectric layer 12. The buffer layer 14 is usually made of insulating materials such as silicon oxide (SiO2), which has good dielectric properties and thermal stability. The buffer layer 14 is used to absorb and disperse interlayer stress, and balance the overall structural stress. The thin film layer 17 is deposited on the surface of the buffer layer 14, which can be made of silicon nitride (SiN) or silicon carbon nitride (SiCN) thin film. The thin film layer 17 has excellent chemical stability and mechanical strength, which can improve the alignment accuracy and bonding strength in the hybrid bonding process.

[0060] In some embodiments of the present disclosure, the removal of the substrate 11 of the redistribution wafer 10 further comprises steps S401-S402. Each step will be described in detail.

[0061] S401: Thin the substrate by grinding process.

[0062] In the embodiments of the present disclosure, as shown in Figure 8 and Figure 9 The grinding process is a physical processing method, which usually uses a grinding wheel or a grinding belt to process the surface of the wafer. By thinning through the grinding process, a large amount of substrate 11 material is quickly removed to improve process efficiency.

[0063] S402: Remove the substrate by chemical mechanical polishing process.

[0064] In the embodiments of the present disclosure, as shown in Figure 8 and Figure 9 After the grinding process, the substrate 11 is accurately removed by the chemical mechanical polishing process without damaging the underlying first dielectric layer 12.

[0065] In some embodiments of the present disclosure, before the first wafer 20 is bonded with the second wafer, the method for forming the hybrid bonding structure further comprises step S501.

[0066] S501: etching a lower surface of the first dielectric layer and depositing a dummy pad. The dummy pad is located between two first contact pads adjacent in a first direction. The first direction is perpendicular to a vertical direction.

[0067] In the embodiments of the present disclosure, referring to Figure 10 As shown in FIG. 12, the lower surface of the first dielectric layer 12 is etched, and a dummy pad 123 is formed by deposition. The dummy pad 123 is used to improve the interface uniformity in the subsequent bonding process. The dummy pad 123 does not directly participate in electrical connection, but is used for process compensation, stress release, or as auxiliary support for the subsequent bonding structure. The dummy pad 123 is arranged between the adjacent first contact pads 122, which can physically balance the thermal stress distribution of the wafer and prevent wafer warping or deformation caused by stress concentration during the bonding process.

[0068] In some embodiments of the present disclosure, bonding the redistribution layer 131 of the redistribution wafer 10 to the first wafer 20 includes steps S601-S603. Each step will be described in detail.

[0069] S601: etching an upper surface of the second dielectric layer to form a second via. The second via exposes part of the redistribution layer.

[0070] In the embodiments of the present disclosure, referring to Figure 6 and Figure 7 As shown in FIG. 13, a second via is formed on the second dielectric layer 13 by etching process, so that part of the underlying redistribution layer 131 is exposed, providing a connection channel for the subsequent filling of the metal to form a contact pad. The second dielectric layer 13 acts as an electrical isolation layer to prevent short circuit between different metal layers. The size and position of the second via need to be accurately controlled to ensure the alignment accuracy with the underlying redistribution layer 131.

[0071] S602: filling the second via to form a second contact pad, thereby forming a second hybrid bonding structure. The second hybrid bonding structure is in contact with the redistribution layer.

[0072] In the embodiments of the present disclosure, referring to Figure 6 and Figure 7 As shown in FIG. 14, the second contact pad 132 is formed by electroplating a metal material in the second via, thereby forming a second hybrid bonding structure. The second contact pad 132 is usually made of copper, aluminum or other metal materials with good electrical conductivity, and the second contact pad 132 is used for electrical connection.

[0073] S603: bonding the redistribution layer of the redistribution wafer to the first wafer through the second hybrid bonding structure.

[0074] In the embodiments of the present disclosure, referring to Figure 8As shown, the redistribution wafer 10 is bonded to the first wafer 20 through the second hybrid bonding structure, which improves the alignment accuracy and connection reliability.

[0075] The embodiments of the present disclosure further provide a hybrid bonding structure, referring to Figure 7 and Figure 10 As shown, the hybrid bonding structure includes the first wafer 20 and the redistribution wafer 10. The redistribution wafer 10 includes the first dielectric layer 12 and the redistribution layer 131 stacked in sequence. The first dielectric layer 12 has a preformed via structure 121 formed therein. The preformed via structure 121 is formed before the redistribution layer 131 of the redistribution wafer 10 is bonded to the first wafer 20. The preformed via structure 121 penetrates the first dielectric layer 12 from the upper surface of the first dielectric layer 12.

[0076] In the embodiments of the present disclosure, referring to Figure 10 As shown, the first dielectric layer 12 further has a first contact pad 122 formed therein. The first contact pad 122 penetrates the first dielectric layer 12 from the lower surface of the first dielectric layer 12. The first contact pad 122 is in contact with the preformed via structure 121 and constitutes the first hybrid bonding structure 30. The first contact pad 122 is aligned with the preformed via structure 121 in the vertical direction Z.

[0077] It should be noted that, referring to Figure 10 As shown, the first contact pad 122 is a conductive structure formed on the lower surface of the first dielectric layer 12 and used for physical and electrical connection with a target wafer. The first contact pad 122 is accurately aligned with the preformed via structure 121 in the vertical direction Z, thereby achieving a low-resistance and high-reliability bonding effect.

[0078] In the embodiments of the present disclosure, referring to Figure 7 and Figure 10 As shown, the redistribution layer 131 of the redistribution wafer 10 is bonded to the first wafer 20, and the first dielectric layer of the redistribution wafer is bonded to the first wafer.

[0079] It should be noted that, referring to Figure 7 and Figure 10 As shown, the redistribution layer 131 of the redistribution wafer 10 is bonded to the first wafer 20 through the second hybrid bonding structure, which improves the alignment accuracy and connection reliability. The first wafer 20 is bonded to the second wafer through the first hybrid bonding structure 30, and the hybrid bonding process can be performed in a high-vacuum environment to reduce the influence of impurities and oxides.

[0080] It can be understood that, referring to Figure 7 and Figure 10As shown, when forming the redistribution wafer 10, a first dielectric layer 12 is prepared in advance, and a pre-fabricated via structure 121 is formed in the first dielectric layer 12. Compared to the formation of the first dielectric layer 12 after the redistribution wafer 10 is bonded to the first wafer 20, the surface structure of the redistribution wafer 10 before bonding is simple and has no complex functional layers. A thin film of the first dielectric layer 12 with good thickness uniformity can be obtained through the deposition process. At the same time, the pre-fabricated via structure 121 formed in advance on the first dielectric layer 12 with good thickness uniformity can avoid alignment deviations caused by wafer deformation or process fluctuations after multiple bonding, thereby improving alignment accuracy.

[0081] Furthermore, after forming the redistribution wafer 10, the redistribution layer 131 of the redistribution wafer 10 is bonded to the first wafer 20. Subsequently, the substrate 11 of the redistribution wafer 10 is removed, leaving only the redistribution layer 131 bonded to the surface of the first wafer 20. The redistribution layer 131 provides the first wafer 20 with high-density signal redistribution and I / O (input / output) port expansion capabilities, while avoiding the thickness redundancy, thermal resistance, and cost issues associated with the substrate 11. Finally, a first hybrid bonding structure 30 is fabricated on the exposed surface of the redistribution layer 131. The first hybrid bonding structure 30 is used to achieve high-precision bonding with the second wafer, thereby improving signal transmission efficiency and interconnect reliability in the package.

[0082] It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments of this application are merely for description and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0083] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0084] The above merely provides the specific implementation of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the embodiments of the present application, which should be covered in the protection scope of the embodiments of the present application.

Claims

1. A method for forming a hybrid bonding structure, characterized in that, The method for forming the hybrid bonding structure includes: A redistribution wafer is formed; the redistribution wafer includes: a substrate, a first dielectric layer and a redistribution layer stacked sequentially; wherein, a pre-fabricated via structure is formed in the first dielectric layer; the pre-fabricated via structure penetrates a portion of the first dielectric layer through the upper surface of the first dielectric layer; The redistribution layer of the redistribution wafer is bonded to the first wafer; Remove the substrate from the redistribution wafer; The lower surface of the first dielectric layer is etched, and a first contact pad is deposited to form it; wherein the first contact pad contacts the pre-fabricated via structure to form a first hybrid bonding structure; the first contact pad and the pre-fabricated via structure are aligned in the vertical direction. The first wafer and the second wafer are bonded together using the first hybrid bonding structure.

2. The method for forming a hybrid bonding structure according to claim 1, characterized in that, The method for forming the redistribution wafer includes: The first dielectric layer is deposited on the substrate; The upper surface of the first dielectric layer is etched to form the first through-hole; The first through hole is filled with metal material to form the prefabricated through hole structure; Deposit a second dielectric layer on the first dielectric layer; The upper surface of the second dielectric layer is etched and filled to form the redistribution layer, thereby forming the redistribution wafer.

3. The method for forming a hybrid bonding structure according to claim 2, characterized in that, The first through hole has a T-shaped cross-section; the first through hole includes a straight hole and a groove that are interconnected along the vertical direction; wherein the width of the groove along the first direction is greater than the diameter of the straight hole; the first direction is perpendicular to the vertical direction.

4. The method for forming a hybrid bonding structure according to claim 3, characterized in that, The first through hole is filled using a double damask process to form a prefabricated through hole structure.

5. The method for forming a hybrid bonding structure according to claim 1, characterized in that, The redistribution wafer further includes: a stripping modification layer and a third dielectric layer stacked sequentially; the stripping modification layer and the third dielectric layer are located between the substrate and the first dielectric layer; The substrate from which the redistribution wafer is removed includes: The stripping modification layer is removed by a pyrolysis bonding process, thereby separating the substrate and the third dielectric layer; The remaining third dielectric layer on the first dielectric layer is removed by etching.

6. The method for forming a hybrid bonding structure according to claim 1, characterized in that, The redistribution wafer further includes: a buffer layer and a thin film layer stacked sequentially; the buffer layer and the thin film layer are located between the substrate and the first dielectric layer.

7. The method for forming a hybrid bonding structure according to claim 1, characterized in that, The substrate from which the redistribution wafer is removed further includes: The substrate is thinned using a grinding process; The substrate is removed by a chemical mechanical polishing process.

8. The method for forming a hybrid bonding structure according to claim 1, characterized in that, Before bonding the first wafer to the second wafer, the method for forming the hybrid bonding structure further includes: The lower surface of the first dielectric layer is etched and a virtual pad is deposited to form a virtual pad; wherein the virtual pad is located between two adjacent first contact pads along a first direction; the first direction is perpendicular to the vertical direction.

9. The method for forming a hybrid bonding structure according to claim 3, characterized in that, The step of bonding the redistribution layer of the redistribution wafer to the first wafer includes: The upper surface of the second dielectric layer is etched to form a second via; the second via exposes a portion of the redistribution layer. The second through-hole is filled to form a second contact pad, thereby forming a second hybrid bonding structure; the second hybrid bonding structure is in contact with the redistribution layer; The redistribution layer of the redistribution wafer is bonded to the first wafer via a second hybrid bonding structure.

10. A hybrid bonding structure, characterized in that, The hybrid bonding structure includes: a first wafer and a redistribution wafer; The redistribution wafer includes: a first dielectric layer and a redistribution layer stacked sequentially; wherein, a pre-fabricated via structure is formed in the first dielectric layer; the pre-fabricated via structure is formed before the redistribution layer of the redistribution wafer is bonded to the first wafer; the pre-fabricated via structure penetrates a portion of the first dielectric layer through the upper surface of the first dielectric layer; A first contact pad is also formed in the first dielectric layer; The first contact pad penetrates a portion of the first dielectric layer through the lower surface of the first dielectric layer; the first contact pad contacts the pre-fabricated via structure to form a first hybrid bonding structure; the first contact pad and the pre-fabricated via structure are aligned in the vertical direction. The redistribution layer of the redistribution wafer is bonded to the first wafer; The first dielectric layer of the redistribution wafer is bonded to the second wafer.

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