Multilayer ceramic capacitor

Abstract

According to the present invention, it is possible to provide a multilayer ceramic capacitor that achieves high capacitance and has high reliability. In a laminated ceramic capacitor (1), a laminated body (2) has an inner layer section (10) in which a plurality of first internal electrode layers (6a) and a plurality of second internal electrode layers (6b) face each other, and an outer layer section made of a dielectric material, the length of the inner layer section (10) in the direction parallel to the lamination direction (T) at the center of the inner layer section (10) in the width direction (W) is set as a first length, and the length of the inner layer section (10) in the direction parallel to the lamination direction (T) is set as a second length. The length of the inner layer section (10) in the direction parallel to the stacking direction (T) at a position where the length of the inner layer section (10) in the direction parallel to the end of the inner layer section (10) in the width direction (W) from the end of the inner layer section (10) in the width direction (W) is 0.3% to 8.0% of the length of the inner layer section (10) in the width direction (W). The second length is longer than the first length.

Description

TECHNICAL FIELD

[0001] The present application relates to a multilayer ceramic capacitor. BACKGROUND

[0002] In manufacturing a multilayer ceramic capacitor, a plurality of dielectric sheets are prepared, and the dielectric sheets are stacked. In recent years, in order to achieve miniaturization and high capacitance of the multilayer ceramic capacitor, thinning and multilayering of the dielectric sheets are being promoted. In addition, in order to improve the durability and the like of the multilayer ceramic capacitor which is multilayered, in Patent Literature 1, a technique of containing a glass component in an external electrode is disclosed.

[0003] PRIOR ART LITERATURE

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 2001-267173 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, the more the thinning and multilayering of the dielectric sheets are promoted, the more the durability decreases, particularly at the end portion of the internal electrode layer. As an example of the decrease in the durability, there is the following case. In manufacturing a multilayer ceramic capacitor, the stacked dielectric sheets are pressed. By this pressing, the dielectric layer is sometimes thinned at the end portion of the internal electrode layer. On the other hand, at the end portion of the internal electrode layer, due to the edge effect, the strength of the electric field becomes large compared with other portions of the internal electrode layer. Therefore, electric field concentration occurs at the end portion of the internal electrode layer where the dielectric layer is thin, and insulation breakdown occurs.

[0008] This decrease in the durability becomes more of a problem in a case where a larger capacitance is desired. This is because, in order to increase the capacitance, the thickness of the dielectric layer is made thinner.

[0009] Therefore, the present application has an object to provide a multilayer ceramic capacitor which achieves a high capacitance and has high reliability.

[0010] TECHNICAL SOLUTION FOR SOLVING THE PROBLEMS

[0011] The laminated ceramic capacitor of the present application has: a laminate having a plurality of laminated dielectric layers, and a plurality of first internal electrode layers and a plurality of second internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposing in a laminating direction, a first end surface and a second end surface opposing in a length direction orthogonal to the laminating direction, and a first side surface and a second side surface opposing in a width direction orthogonal to the laminating direction and the length direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the laminate has: an inner layer portion in which the plurality of first internal electrode layers and the plurality of second internal electrode layers oppose each other; and an outer layer portion composed of a dielectric material, when a length of the inner layer portion in a direction parallel to the laminating direction at a central position in the width direction of the inner layer portion is set as a first length, and a length of the inner layer portion in the direction parallel to the laminating direction at a position where a length of the inner layer portion in a direction parallel to the other end in the width direction of the inner layer portion from an end in the width direction of the inner layer portion is 0.3% or more and 8.0% or less of a length of the inner layer portion in the width direction is set as a second length, the second length is longer than the first length.

[0012] Effects of the Invention

[0013] According to the present application, it is possible to provide a laminated ceramic capacitor in which capacitance is easily increased and reliability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a perspective view of the laminated ceramic capacitor of the present embodiment.

[0015] Figure 2 is a cross-sectional view of line I-I of Figure 1

[0016] Figure 3 is a cross-sectional view of line II-II of Figure 1

[0017] Figure 4 is a cross-sectional view of line III-III of Figure 1

[0018] Figure 5A is a view showing a state in which a conductive paste and a paste for step reduction are printed on a dielectric sheet.

[0019] Figure 5B is a view showing two laminated dielectric sheets 40.

[0020] Figure 6 is a cross-sectional view of line W-W' of Figure 5A DETAILED DESCRIPTION​​​​

[0021] Based on Figure 1 to describe the specific embodiments. Figure 1 is a perspective view of a multilayer ceramic capacitor 1 which is an embodiment of the present application.

[0022] (laminate)

[0023] The laminate 2 includes a plurality of dielectric layers and a plurality of internal electrode layers which are laminated. The shape of the laminate 2 is substantially a rectangular parallelepiped. In the laminate 2, the direction in which the dielectric layers and the internal electrode layers are laminated is set as a laminating direction T. The direction orthogonal to the laminating direction T is set as a width direction W. The direction orthogonal to the laminating direction T and the width direction W is set as a length direction L.

[0024] In the laminate 2, one of the two faces opposite in the laminating direction T is set as a first main face Ml. The other one is set as a second main face M2. In the laminate 2, one of the two faces opposite in the width direction W is set as a first side face SI. The other one is set as a second side face S2. In the laminate 2, one of the two faces opposite in the length direction L is set as a first end face El. The other one is set as a second end face E2. The mounting face of the multilayer ceramic capacitor 1 is the second main face M2. The so-called mounting face means the face facing a wiring substrate or the like when the multilayer ceramic capacitor 1 is mounted to the wiring substrate or the like.

[0025] As to the cross section of the laminate 2, the I-I line cross section of Figure 1 is set as an LT cross section. As to the cross section of the laminate 2, the II-II line cross section of Figure 1 is set as a WT cross section. As to the cross section of the laminate 2, the III-III line cross section of Figure 1 is set as a LW cross section.

[0026] The corner portions of the laminate 2 and the edge line portions of the laminate 2 preferably have rounded corners. The corner portion is a portion where three faces of the laminate 2 intersect. The edge line portion is a portion where two faces of the laminate 2 intersect. The concave-convex or the like can be formed in a part or all of the main faces, the side faces, and the end faces.

[0027] (dielectric layer)

[0028] The total number of the dielectric layers laminated in the laminate 2 is preferably 15 or more and 2000 or less. The main material of the dielectric layer is a ceramic material. Among the examples of the ceramic material, there are dielectric ceramics in which BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like is the main component. The ceramic material can also be a dielectric ceramic in which a Mn compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, or the like is added as a subcomponent to these main components.

[0029] The thickness of one layer of the dielectric layer is preferably 0.5 μm or more and 10 μm or less.

[0030] (Sectioning of the laminate)

[0031] The sectioning in the length direction L of the laminate 2 will be described based on Figure 2 Figure 2 is a cross-sectional view taken along the line I-I of Figure 1 The laminate 2 can be sectioned into a first main surface side outer layer portion OLl, an inner layer range IL, and a second main surface side outer layer portion OL2 in the stacking direction T. The first main surface side outer layer portion OLl, the inner layer range IL, and the second main surface side outer layer portion OL2 are arranged in order from the first main surface Ml toward the second main surface M2 in the stacking direction T.

[0032] The first main surface side outer layer portion OLl is a portion between the inner electrode layer closest to the first main surface Ml and the first main surface Ml. The inner layer range IL is a range in which the inner electrode layers are opposed to each other. The second main surface side outer layer portion OL2 is a portion between the inner electrode layer closest to the second main surface M2 and the second main surface M2.

[0033] The first main surface side outer layer portion OLl is located on the first main surface Ml side of the laminate 2. The first main surface side outer layer portion OLl is formed of a collection of a plurality of dielectric layers located between the first main surface Ml and the inner electrode layer closest to the first main surface Ml. The first main surface side outer layer portion OLl is formed of a plurality of dielectric layers located between the first main surface Ml and the outermost surface of the inner layer range IL on the first main surface Ml side and an extension line of the outermost surface.

[0034] The second main surface side outer layer portion OL2 is located on the second main surface M2 side of the laminate 2. The second main surface side outer layer portion OL2 is formed of a collection of a plurality of dielectric layers located between the second main surface M2 and the inner electrode layer closest to the second main surface M2. The second main surface side outer layer portion OL2 is formed of a plurality of dielectric layers located between the second main surface M2 and the outermost surface of the inner layer range IL on the second main surface M2 side and an extension line of the outermost surface.

[0035] The inner layer range IL is a range sandwiched by the first main surface side outer layer portion OLl and the second main surface side outer layer portion OL2.

[0036] The dielectric layers disposed in the first main surface side outer layer portion OLl and the second main surface side outer layer portion OL2 among the dielectric layers are set as outer layer dielectric layers 3. The dielectric layers disposed in the inner layer range IL among the dielectric layers are set as inner layer dielectric layers 4.

[0037] ​In the description of the length and the position, the following terms are used. The length in the length direction L is set as the length direction length. The length in the width direction W is set as the width direction length. The length in the stacking direction T is set as the stacking direction length. The position of the length that is half of the length direction length is set as the central position in the length direction L. The central position in the length direction L is set as the length direction central position. The position of the length that is half of the width direction length is set as the central position in the width direction W. The central position in the width direction W is set as the width direction central position. The position of the length that is half of the stacking direction length is set as the central position in the stacking direction T. The central position in the stacking direction T is set as the stacking direction central position. The end portion in the length direction L is set as the length direction end portion. The end portion in the width direction W is set as the width direction end portion. The end portion in the stacking direction T is set as the stacking direction end portion.

[0038] The size of the laminate 2 is not particularly limited. The length direction length of the laminate is preferably 0.2 mm or more and 10 mm or less. The width direction length of the laminate 2 is preferably 0.1 mm or more and 5 mm or less. The stacking direction length of the laminate 2 is preferably 0.1 mm or more and 5 mm or less.

[0039] (L gap)

[0040] The division in the length direction L of the laminate 2 is described. The laminate 2 can be divided into the 1st end surface side outer layer portion LG1, the length direction opposing portion LF, and the 2nd end surface side outer layer portion LG2 in the length direction L. The 1st end surface side outer layer portion LG1, the length direction opposing portion LF, and the 2nd end surface side outer layer portion LG2 are arranged in order from the 1st end surface E1 toward the 2nd end surface E2 in the length direction L.

[0041] The length direction opposing portion LF is a portion in which the 1st internal electrode layer 6a and the 2nd internal electrode layer 6b oppose each other in the stacking direction T. The 1st end surface side outer layer portion LG1 is a portion between the length direction opposing portion LF and the 1st end surface E1. The 2nd end surface side outer layer portion LG2 is a portion between the length direction opposing portion LF and the 2nd end surface E2. The length direction opposing portion LF is a portion corresponding to the opposing electrode portion of the internal electrode layer. The 1st end surface side outer layer portion LG1 and the 2nd end surface side outer layer portion LG2 are portions corresponding to the lead electrode portion of the internal electrode layer. The 1st end surface side outer layer portion LG1 and the 2nd end surface side outer layer portion LG2 are also referred to as L gaps.

[0042] The 1st end surface side outer layer portion LG1 is located on the 1st end surface E1 side. The 1st end surface side outer layer portion LG1 is located between the 1st end surface E1 and the outermost surface of the end portion of the 1st end surface E1 side of the 2nd internal electrode layer 6b.

[0043] The 2nd end surface side outer layer portion LG2 is located on the 2nd end surface E2 side. The 2nd end surface side outer layer portion LG2 is located between the 2nd end surface E2 and the most surface of the end portion on the 2nd end surface E2 side of the 1st inner electrode layer 6a.

[0044] (W gap)

[0045] The division in the width direction W of the laminate 2 will be described based on Figure 3 Figure 3 is Figure 1 II-II line sectional view of the laminate 2. The laminate 2 can be divided into a 1st side surface side outer layer portion WG1, a width direction opposing portion WF, and a 2nd side surface side outer layer portion WG2 in the width direction W. The 1st side surface side outer layer portion WG1, the width direction opposing portion WF, and the 2nd side surface side outer layer portion WG2 are arranged in order from the 1st side surface S1 toward the 2nd side surface S2 in the width direction W.

[0046] The width direction opposing portion WF is a portion in which the inner electrode layers oppose each other in the stacking direction T. The 1st side surface side outer layer portion WG1 is a portion between the width direction opposing portion WF and the 1st side surface S1. The 2nd side surface side outer layer portion WG2 is a portion between the width direction opposing portion WF and the 2nd side surface S2. The 1st side surface side outer layer portion WG1 and the 2nd side surface side outer layer portion WG2 are also referred to as W gaps.

[0047] The 1st side surface side outer layer portion WG1 and the 2nd side surface side outer layer portion WG2 are portions in which the inner electrode layers are not present in the stacking direction T. The 1st side surface side outer layer portion WG1 is located on the 1st side surface S1 side. The 1st side surface side outer layer portion WG1 is formed by a plurality of dielectric layers located between the 1st side surface S1 and the most surface of the width direction opposing portion WF on the 1st side surface S1 side.

[0048] The 2nd side surface side outer layer portion WG2 is located on the 2nd side surface S2 side. The 2nd side surface side outer layer portion WG2 is formed by a plurality of dielectric layers located between the 2nd side surface S2 and the most surface of the width direction opposing portion WF on the 2nd side surface S2 side.

[0049] (inner electrode layer)

[0050] The inner electrode layer includes a plurality of 1st inner electrode layers 6a and a plurality of 2nd inner electrode layers 6b. The 1st inner electrode layer 6a is an inner electrode layer exposed at the 1st end surface E1. The 2nd inner electrode layer 6b is an inner electrode layer exposed at the 2nd end surface E2.

[0051] The 1st inner electrode layer 6a can be divided into a 1st opposing electrode portion 7a and a 1st lead electrode portion 8a. The 1st opposing electrode portion 7a is a portion opposing the 2nd inner electrode layer 6b. The 1st lead electrode portion 8a is a portion leading out from the 1st opposing electrode portion 7a to the 1st end surface E1 of the laminate 2. ​

[0052] The end portion of the first lead-out electrode portion 8a on the first end surface E1 side is led out to the surface of the first end surface E1 of the laminate 2. The end portion of the first lead-out electrode portion 8a led out to the first end surface E1 forms an exposed portion on the first end surface E1.

[0053] The second internal electrode layer 6b can be divided into a second opposing electrode portion 7b and a second lead-out electrode portion 8b. The second opposing electrode portion 7b is a portion opposing the first internal electrode layer 6a. The second lead-out electrode portion 8b is a portion led out from the second opposing electrode portion 7b to the second end surface E2 of the laminate 2.

[0054] The end portion of the second lead-out electrode portion 8b on the second end surface E2 side is led out to the surface of the second end surface E2 of the laminate 2. The end portion of the second lead-out electrode portion 8b led out to the second end surface E2 forms an exposed portion on the second end surface E2.

[0055] The shape of the first opposing electrode portion 7a and the shape of the second opposing electrode portion 7b are not particularly limited. The shape of the first opposing electrode portion 7a and the shape of the second opposing electrode portion 7b are preferably rectangular. The corner portions of the first opposing electrode portion 7a and the corner portions of the second opposing electrode portion 7b can also have rounded corners. The corner portions of the first opposing electrode portion 7a and the corner portions of the second opposing electrode portion 7b can also be formed obliquely. By obliquely formed, it means formed in a tapered shape.

[0056] The shape of the first lead-out electrode portion 8a and the shape of the second lead-out electrode portion 8b are not particularly limited. The shape of the first lead-out electrode portion 8a and the shape of the second lead-out electrode portion 8b are preferably rectangular. The corner portions of the first lead-out electrode portion 8a and the corner portions of the second lead-out electrode portion 8b can also have rounded corners. The corner portions of the first lead-out electrode portion 8a and the corner portions of the second lead-out electrode portion 8b can also be formed obliquely. By obliquely formed, it means formed in a tapered shape.

[0057] The width of the first opposing electrode portion 7a and the width of the first lead-out electrode portion 8a can be the same. It can also be that the width of either one of the first opposing electrode portion 7a and the first lead-out electrode portion 8a is narrower than the width of the other one.

[0058] The width of the second opposing electrode portion 7b and the width of the second lead-out electrode portion 8b can be the same. It can also be that the width of either one of the second opposing electrode portion 7b and the second lead-out electrode portion 8b is narrower than the width of the other one.

[0059] The material of the first internal electrode layer 6a and the second internal electrode layer 6b can be, for example, a metal such as Ni, Cu, Ag, Pd, Au, an alloy containing at least one of these metals such as an Ag-Pd alloy, or the like appropriate conductive material.

[0060] In the multilayer ceramic capacitor 1, a capacitance is formed by the first opposing electrode portion 7a and the second opposing electrode portion 7b opposing each other with the inner layer dielectric layer 4 interposed therebetween. Thus, the multilayer ceramic capacitor 1 exhibits the characteristics of a capacitor.

[0061] The thickness of the first internal electrode layer 6a and the thickness of the second internal electrode layer 6b are, for example, preferably in the range of 0.2 μm or more and 2.0 μm or less. The total number of pieces, which is the sum of the number of pieces of the first internal electrode layer 6a and the number of pieces of the second internal electrode layer 6b, is preferably 15 pieces or more and 2000 pieces or less.

[0062] (Step reduction near end surface)

[0063] In the multilayer ceramic capacitor 1, the second dielectric layer 5b is provided. The second dielectric layer 5b is a dielectric layer provided to make the length in the stacking direction of the stack 2 approximately uniform.

[0064] The step reduction in the stack 2 is described with reference to Figure 2 It is preferable that the difference between the length in the stacking direction of the stack 2 in the lengthwise facing portion LF and the length in the stacking direction of the stack 2 in the first end surface side outer layer portion LG1 be small. It is preferable that the difference between the length in the stacking direction of the stack 2 in the lengthwise facing portion LF and the length in the stacking direction of the stack 2 in the second end surface side outer layer portion LG2 be small.

[0065] However, in the inner layer range IL, the difference between the length in the stacking direction of the stack 2 in the lengthwise facing portion LF and the length in the stacking direction of the stack 2 in the first end surface side outer layer portion LG1 tends to be large. In the inner layer range IL, the difference between the length in the stacking direction of the stack 2 in the lengthwise facing portion LF and the length in the stacking direction of the stack 2 in the second end surface side outer layer portion LG2 tends to be small.

[0066] In the inner layer range IL, in the lengthwise facing portion LF, the inner layer dielectric layer 4 and the first internal electrode layer 6a and the second internal electrode layer 6b are stacked.

[0067] In the first end surface side outer layer portion LG1, only the inner layer dielectric layer 4 and the first internal electrode layer 6a are stacked. In the first end surface side outer layer portion LG1, the second internal electrode layer 6b is not stacked.

[0068] In the second end surface side outer layer portion LG2, only the inner layer dielectric layer 4 and the second internal electrode layer 6b are stacked. In the second end surface side outer layer portion LG2, the first internal electrode layer 6a is not stacked.

[0069] In the length direction opposite portion LF and the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2, the layers stacked are different. Therefore, in the length direction opposite portion LF and the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2, the stacked direction length is easily different.

[0070] In order to reduce the difference in the stacked direction length in the length direction opposite portion LF and the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2, an additional inner dielectric layer 4 is provided in the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. This additional inner dielectric layer 4 is provided as a second dielectric layer 5b. In order to distinguish from the second dielectric layer 5b, the dielectric layer included in the laminate 2 other than the second dielectric layer 5b is provided as a first dielectric layer 5a.

[0071] The second dielectric layer 5b is provided between the length direction end portion of the first internal electrode layer 6a and the second end surface E2. The second dielectric layer 5b is provided between the length direction end portion of the second internal electrode layer 6b and the first end surface E1.

[0072] The main component of the second dielectric layer 5b is preferably the same as the main component of the first dielectric layer 5a. The component of the second dielectric layer 5b is not limited thereto.

[0073] (Step reduction near side surface)

[0074] In the laminate ceramic capacitor 1, the second dielectric layer 5b is also provided near the side surface. This will be explained based on Figure 3 The stacked direction length of the laminate 2 is preferably uniform not only in the length direction L but also in the width direction W. In the inner layer range IL, in the width direction opposite portion WF and the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2, the stacked direction length is easily different in the width direction W as well as in the length direction L.

[0075] In the inner layer range IL, in the width direction opposite portion WF, the inner dielectric layer 4 and the first internal electrode layer 6a and the second internal electrode layer 6b are stacked.

[0076] In the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2, the first internal electrode layer 6a and the second internal electrode layer 6b are not stacked. In the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2, only the inner dielectric layer 4 is stacked.

[0077] In the width direction opposite portion WF and the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2, the layers stacked are different. Therefore, in the width direction opposite portion WF and the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2, the stacked direction length is easily different.

[0078] In order to reduce the difference in the stacking direction length between the width direction opposite portion WF and the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2, an additional inner layer dielectric layer 4 is provided in the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2. This additional inner layer dielectric layer 4 is the second dielectric layer 5b.

[0079] The second dielectric layer 5b is provided between the end portion on the first side surface S1 side in the width direction W of the first internal electrode layer 6a and the second internal electrode layer 6b and the first side surface S1. The second dielectric layer 5b is provided between the end portion on the second side surface S2 side in the width direction W of the first internal electrode layer 6a and the second internal electrode layer 6b and the second side surface S2.

[0080] (Inner layer portion)

[0081] The portion in which the first internal electrode layer 6a and the second internal electrode layer 6b are opposite to each other is set as an inner layer portion 10. The inner layer portion 10 is Figure 2 the length direction opposite portion LF and Figure 3 the width direction opposite portion WF and the inner layer range IL intersect. The shape of the inner layer portion 10 is substantially a rectangular parallelepiped. In Figure 2 , the portion in which the length direction opposite portion LF and the inner layer range IL intersect is shown as the inner layer portion 10. Further, in Figure 3 , the portion in which the width direction opposite portion WF and the inner layer range IL intersect is shown as the inner layer portion 10.

[0082] (External electrode)

[0083] The external electrode is described. The external electrode includes a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is connected to the first internal electrode layer 6a. The first external electrode 20a is further provided from the first end surface E1 to a portion of the first major surface M1 and a portion of the second major surface M2, and a portion of the first side surface S1 and a portion of the second side surface S2.

[0084] The second external electrode 20b is connected to the second internal electrode layer 6b. The second external electrode 20b is further provided from the second end surface E2 to a portion of the first major surface M1 and a portion of the second major surface M2, and a portion of the first side surface S1 and a portion of the second side surface S2.

[0085] The first external electrode 20a and the second external electrode 20b preferably have a base electrode layer and a plating layer. The base electrode layer can include at least one layer selected from a fired layer, a conductive resin layer, a thin film layer, and the like. The conductive resin layer can be provided independently of the base electrode layer. The structure in which the fired layer is provided as the base electrode layer and the conductive resin layer is provided independently of the base electrode layer will be described as an example.

[0086] The first external electrode 20a includes a first base electrode layer 21a, a first conductive resin layer 22a, a first lower plating layer 23a, and a first upper plating layer 24a. The second external electrode 20b includes a second base electrode layer 21b, a second conductive resin layer 22b, a second lower plating layer 23b, and a second upper plating layer 24b.

[0087] The first base electrode layer 21a and the second base electrode layer 21b are layers including a conductive metal and a glass component. The first conductive resin layer 22a and the second conductive resin layer 22b do not include a metal component. The first conductive resin layer 22a and the second conductive resin layer 22b are formed of a thermosetting resin. The first lower plating layer 23a and the second lower plating layer 23b can be provided as Ni plating layers, for example. The first upper plating layer 24a and the second upper plating layer 24b can be provided as Sn plating layers, for example.

[0088] (Base electrode layer)

[0089] The base electrode layer includes the first base electrode layer 21a and the second base electrode layer 21b. The first base electrode layer 21a is disposed from the first end surface E1 to a portion of the first major surface M1 and a portion of the second major surface M2, and a portion of the first side surface S1 and a portion of the second side surface S2. The second base electrode layer 21b is disposed from the second end surface E2 to a portion of the first major surface M1 and a portion of the second major surface M2, and a portion of the first side surface S1 and a portion of the second side surface S2.

[0090] The first base electrode layer 21a and the second base electrode layer 21b include a conductive metal and a glass component. The conductive metal is at least one of Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like, for example. The glass component is at least one of B, Si, Ba, Mg, Al, Li, and the like.

[0091] The first base electrode layer 21a and the second base electrode layer 21b can also be formed in multiple layers. The first base electrode layer 21a and the second base electrode layer 21b can also be formed by applying a conductive paste including a glass component and a metal to a laminate, and then performing firing. The firing can be performed simultaneously with the firing of the internal electrode layer. The firing can also be performed after the internal electrode layer is fired.

[0092] In the case where the conductive paste is fired at the same time as the internal electrode layer and the dielectric layer, a dielectric material is preferably added in place of the glass component. The first base electrode layer 21a and the second base electrode layer 21b are fired layers formed by firing.

[0093] The thickness of the first base electrode layer 21a at the central position in the stacking direction of the first base electrode layer 21a located at the first end surface E1 is, for example, preferably in the range of 10 μm or more and 150 μm or less. The thickness of the second base electrode layer 21b at the central position in the stacking direction of the second base electrode layer 21b located at the second end surface E2 is, for example, preferably in the range of 10 μm or more and 150 μm or less.

[0094] In the case where the first base electrode layer 21a and the second base electrode layer 21b are provided on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2, the thickness of the first base electrode layer 21a or the second base electrode layer 21b at the central position in the longitudinal direction of the first base electrode layer 21a or the second base electrode layer 21b located on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2 is, for example, preferably in the range of 5 μm or more and 50 μm or less.

[0095] In the case where the base electrode layer is provided as a thin film layer, the thin film layer can be formed by a thin film formation method such as a sputtering method or an evaporation method. The formed thin film layer is a layer in which metal particles are stacked. The thickness of the formed thin film layer is 1 μm or less.

[0096] (Electrically conductive resin layer)

[0097] An electrically conductive resin layer is provided on the base electrode layer. The electrically conductive resin layer contains a resin component and a metal component. The electrically conductive resin layer has a first electrically conductive resin layer 22a and a second electrically conductive resin layer 22b. The first electrically conductive resin layer 22a and the second electrically conductive resin layer 22b contain a thermosetting resin as the resin component. By containing the resin component, the first electrically conductive resin layer 22a and the second electrically conductive resin layer 22b are softer than the base electrode layer. The base electrode layer does not contain the resin component. The base electrode layer contains a plating film, a metal component, a glass component, and the like. The base electrode layer is a fired product. For these reasons, the base electrode layer is not soft.

[0098] The electrically conductive resin layer functions as a buffer layer. Therefore, in the case where a flexural stress is applied to the mounting substrate, and a physical impact is applied to the multilayer ceramic capacitor 1 due to the stress, cracks are less likely to occur in the multilayer ceramic capacitor 1. In the case where an impact due to thermal cycles is applied to the multilayer ceramic capacitor 1, cracks are less likely to occur in the multilayer ceramic capacitor 1.

[0099] The thermosetting resin included in the conductive resin layer is, for example, various thermosetting resins such as an epoxy resin, a phenol resin, a polyurethane resin, a silicone resin, a polyimide resin, and the like. Among these resins, the epoxy resin is one of the most suitable resins. This is because the epoxy resin is excellent in heat resistance, moisture resistance, adhesion, and the like.

[0100] The first conductive resin layer 22a is arranged on the first base electrode layer 21a. The first conductive resin layer 22a covers the first base electrode layer 21a. The end portion of the first conductive resin layer 22a is preferably in contact with the laminate 2.

[0101] The second conductive resin layer 22b is arranged on the second base electrode layer 21b. The second conductive resin layer 22b covers the second base electrode layer 21b. The end portion of the second conductive resin layer 22b is preferably in contact with the laminate 2.

[0102] The metal component included in the first conductive resin layer 22a and the second conductive resin layer 22b can be Ag, Cu, Ni, Sn, Bi, or an alloy including them. The shape of the metal component is preferably a filler shape. In the case where the metal component is a metal powder, a metal powder on which Sn, Ni, or Cu is coated on the surface can be used. In the case where a metal powder on which Sn, Ni, or Cu is coated on the surface is used, the metal powder is preferably a powder of Ag, Cu, Ni, Sn, Bi, or an alloy thereof. The metal component particularly preferably includes Ag. The Ag can be Ag alone. The Ag can also be an alloy including Ag or a metal powder on which Ag is coated on the surface.

[0103] In the case where a metal powder on which Ag coating is performed on the surface is used, a powder of Cu, Ni, Sn, Bi, or an alloy thereof is preferably used as the metal powder. In the case where Ag is used as the metal filler, the following advantages are obtained. Ag has the lowest electrical resistance among metals. Ag can form an electrode having low electrical resistance. Ag is a noble metal. Ag is not easily oxidized. Ag can make the resistance of the conductive resin layer high. The use of Ag as the metal filler can make the metal of the base material inexpensive while maintaining the properties of Ag.

[0104] The shape of the metal filler included in the first conductive resin layer 22a and the second conductive resin layer 22b is not particularly limited. The shape of the metal filler can be spherical or flat, or the like. The metal filler can also be a material in which a spherical metal powder and a flat metal powder are mixed.

[0105] The average particle diameter of the metal filler contained in the first conductive resin layer 22a and the second conductive resin layer 22b is not particularly limited. The average particle diameter of the metal filler can be, for example, 0.3 μm or more and 10 μm or less. The average particle diameter of the metal filler contained in the conductive resin layer can be found by calculation based on the laser diffraction particle size measurement method (based on IOS 13320). The method of finding the average particle diameter can be applied regardless of the shape of the filler.

[0106] The metal filler contained in the first conductive resin layer 22a and the second conductive resin layer 22b enables the conductive resin layer to be electrified. The contact of the metal filler with the metal filler forms an electrification path inside the conductive resin layer.

[0107] The resin contained in the first conductive resin layer 22a and the second conductive resin layer 22b is, for example, various well-known thermosetting resins such as an epoxy resin, a phenoxy resin, a phenol resin, a polyurethane resin, a silicone resin, a polyimide resin, and the like. The epoxy resin is excellent in heat resistance, moisture resistance, and adhesion, and the like. The epoxy resin is one of the most suitable resins.

[0108] The first conductive resin layer 22a and the second conductive resin layer 22b preferably contain a curing agent in addition to the thermosetting resin. In the case where an epoxy resin is used as the base resin, the curing agent can be various well-known compounds such as a phenol-based, an amine-based, an acid anhydride-based, an imidazole-based, an active ester-based, an amide imide-based, and the like.

[0109] The amount of the metal contained in the first conductive resin layer 22a is preferably 35 vmol% or more and 75 vmol% or less with respect to the entire volume of the first conductive resin layer 22a. The amount of the metal contained in the second conductive resin layer 22b is preferably 35 vmol% or more and 75 vmol% or less with respect to the entire volume of the second conductive resin layer 22b.

[0110] The amount of the resin contained in the first conductive resin layer 22a is preferably 25 vmol% or more and 65 vmol% or less with respect to the entire volume of the first conductive resin layer 22a. The amount of the resin contained in the second conductive resin layer 22b is preferably 25 vmol% or more and 65 vmol% or less with respect to the entire volume of the second conductive resin layer 22b.

[0111] The thickness of the first conductive resin layer 22a or the second conductive resin layer 22b at the central position in the stacking direction of the first conductive resin layer 22a or the second conductive resin layer 22b located at the first end surface El or the second end surface E2 is, for example, preferably 10 μm or more and 200 μm or less.

[0112] In the case where the first conductive resin layer 22a and the second conductive resin layer 22b are provided on the first main surface Ml and the second main surface M2, and the first side surface Sl and the second side surface S2, the thickness of the conductive resin layer at the central position in the length direction of the first conductive resin layer 22a or the second conductive resin layer 22b located on the first main surface Ml and the second main surface M2, and the first side surface Sl and the second side surface S2 is, for example, preferably in the order of 10 μm or more and 200 μm or less.

[0113] (plating layer)

[0114] The plating layer will be described. The plating layer includes a lower plating layer and an upper plating layer. The plating layer includes two layers. The plating layer can be one layer or a plurality of layers.

[0115] (lower plating layer)

[0116] The lower plating layer is disposed on the conductive resin layer. The lower plating layer covers at least a portion of the conductive resin layer. The lower plating layer includes a first lower plating layer 23a and a second lower plating layer 23b. The first lower plating layer 23a is disposed on the first conductive resin layer 22a. The second lower plating layer 23b is disposed on the second conductive resin layer 22b.

[0117] The first lower plating layer 23a and the second lower plating layer 23b can be Ni plating layers. By providing the lower plating layer as a Ni plating layer, solder corrosion of the base electrode layer and the like at the time of mounting the multilayer ceramic capacitor 1 is suppressed.

[0118] (upper plating layer)

[0119] The upper plating layer is disposed on the lower plating layer. The upper plating layer covers at least a portion of the lower plating layer. The upper plating layer includes a first upper plating layer 24a and a second upper plating layer 24b. The first upper plating layer 24a is disposed on the first lower plating layer 23a. The second upper plating layer 24b is disposed on the second lower plating layer 23b.

[0120] The first upper plating layer 24a and the second upper plating layer 24b can be Sn plating layers. The wettability of solder with respect to Sn plating layers is good. Therefore, by providing the upper plating layer as a Sn plating layer, mounting of the multilayer ceramic capacitor 1 to a substrate and the like becomes easy.

[0121] The metal of the material of the lower plating layer and the surface plating layer is not particularly limited. The plating layer can be, for example, at least one of Cu, Ni, Ag, Pd, Au, Sn, and the like, and an alloy such as an Ag-Pd alloy, including the lower plating layer and the surface plating layer.

[0122] The thickness of each layer of the plating layer is preferably 2 μm or more and 15 μm or less.

[0123] It is also possible to not provide the base electrode layer. It is also possible to form the external electrode only by the plating layer. A case where the base electrode layer is not provided and only the plating layer is provided is described.

[0124] The first external electrode 20a and the second external electrode 20b are formed directly on the surface of the laminate 2. The first external electrode 20a and the second external electrode 20b are plating layers. The laminate ceramic capacitor 1 includes the plating layer electrically connected to the first internal electrode layer 6a or the second internal electrode layer 6b. A pretreatment can be performed before the plating layer is formed. The pretreatment is, for example, disposing a catalyst on the surface of the laminate 2.

[0125] The plating layer preferably includes a lower plating electrode and an upper plating electrode. The lower plating electrode is a plating electrode formed on the surface of the laminate 2. The upper plating electrode is a plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode preferably include, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy including the metal.

[0126] The lower plating electrode is preferably formed using Ni. Ni has good solder barrier properties. The upper plating electrode is preferably formed using Sn or Au, or the like. Sn and Au have good solder wettability.

[0127] In a case where the first internal electrode layer and the second internal electrode layer are formed using Ni, the lower plating electrode is preferably formed using Cu. Cu has good adhesion to Ni. The upper plating electrode can be formed as needed. The first external electrode 20a and the second external electrode 20b can also be formed only by the lower plating electrode.

[0128] The outermost layer of the plating layer can also be the upper plating electrode. A further plating electrode can be further formed on the surface of the upper plating electrode. In a case where the plating layer is disposed without providing the base electrode layer, the preferred thickness of each layer of the plating layer is 1 μm or more and 15 μm or less. The plating layer preferably does not include glass. The preferred proportion of metal per unit volume of the plating layer is 99 vol% or more.

[0129] The size of the laminate ceramic capacitor 1 is not particularly limited. The preferred lengthwise length of the laminate ceramic capacitor 1 including the laminate 2 and the external electrode is 0.2 mm or more and 10 mm or less. The preferred laminating direction length of the laminate ceramic capacitor 1 including the laminate 2 and the external electrode is 0.1 mm or more and 5 mm or less. The preferred widthwise length of the laminate ceramic capacitor 1 including the laminate 2 and the external electrode is 0.1 mm or more and 10 mm or less.

[0130] (Method for manufacturing a laminate ceramic capacitor)

[0131] A manufacturing method of the laminated ceramic capacitor 1 will be described.

[0132] (1) A conductive paste for a dielectric sheet and an internal electrode layer is prepared. The conductive paste for a dielectric sheet and an internal electrode layer contains a binder and a solvent. The binder and the solvent can be a publicly known organic binder and an organic solvent, etc.

[0133] (2) The conductive paste for an internal electrode layer is printed on a dielectric sheet in a given pattern. By the printing of the conductive paste, an internal electrode layer pattern is formed. The printing can be performed by, for example, screen printing or gravure printing, etc.

[0134] (3) Dielectric sheets for an outer layer portion are laminated in a given number of sheets. The dielectric sheets for an outer layer portion are not printed with an internal electrode layer pattern. On the laminated dielectric sheets, dielectric sheets printed with an internal electrode layer pattern are sequentially laminated. Further, the dielectric sheets for an outer layer portion in a given number of sheets are laminated thereon. By the lamination thereof, a laminated sheet is produced.

[0135] The second dielectric layer 5b will be described. The second dielectric layer 5b is provided in order to reduce a step of the laminated body 2. A dielectric paste to be the second dielectric layer 5b is called a step-reducing paste.

[0136] The step-reducing paste is coated on a region around the internal electrode layer pattern on the dielectric sheet printed with the internal electrode layer pattern. The step-reducing paste is coated on a portion where the internal electrode layer pattern is not formed. This is because the step-reducing paste is a paste used in order to eliminate a step between the internal electrode layer pattern and the surrounding region. The step-reducing paste can be coated so as to overlap with an end portion of the internal electrode layer pattern. The overlapping width can be set to, for example, a degree of 50 μm. The step-reducing paste can be coated so as to form a gap between the internal electrode layer pattern. The width of the gap can be set to, for example, 50 μm.

[0137] The step-reducing paste can be the same as a ceramic paste used when the dielectric sheet is produced. The step-reducing paste can be different from the ceramic paste used when the dielectric sheet is produced.

[0138] (4) A laminated block is produced by pressing the laminated sheet in a lamination direction. As a method of pressing, isostatic pressing can be adopted.

[0139] (5) The laminated block is cut to a given size. By the cutting, a laminated chip is cut out. At the time of cutting, the corner portions and the edge portions of the laminated chip can also be rounded. As a method of rounding, barrel polishing can be adopted.

[0140] (6) Firing the laminated chip. By this firing, the laminate is produced. The preferable firing temperature is 900°C or higher and 1200°C or lower. The firing temperature can be changed depending on the material of the dielectric and the internal electrode layer.

[0141] An external electrode is provided to the laminate.

[0142] (7) A conductive paste that becomes a base electrode is applied to both end surfaces of the laminate. The conductive paste contains a glass component and a metal. The method of application can employ, for example, a dipping method. After the application, a sintering process is performed. By this sintering process, a base electrode layer is formed. The preferable temperature of the sintering process is 700°C or higher and 900°C or lower. The base electrode layer is a sintered layer.

[0143] (8) A conductive resin layer is formed on the base electrode layer. A conductive resin paste is prepared. The conductive resin paste contains a resin component and a metal component. The conductive resin paste is applied to the base electrode layer. The method of application can employ a dipping method. After the application, a heat treatment is performed. The temperature of the heat treatment is set to 200°C or higher and 550°C or lower. By this heat treatment, the resin is thermally cured. By this thermal curing, a conductive electrode layer is formed. The atmosphere at the time of the heat treatment is preferably a nitrogen atmosphere. The preferable oxygen concentration is 100 ppm or lower. This oxygen concentration makes it difficult for the resin to scatter. This oxygen concentration makes it difficult for the various metal components to be oxidized.

[0144] (9) After the conductive resin layer is formed, a Ni plating layer is formed on the surface of the conductive resin layer. This Ni plating layer becomes the first lower layer plating layer and the second lower layer plating layer. The method of forming the Ni plating layer can employ an electrolytic plating method. The preferable plating method is barrel plating.

[0145] (10) A Sn plating layer is formed on the Ni plating layer. On the first Ni plating layer, a first Sn plating layer is formed. On the second Ni plating layer, a second Sn plating layer is formed. By forming the Sn plating layer, the wettability of the solder used when the laminated ceramic capacitor 1 is mounted to a substrate or the like can be improved. The mounting of the laminated ceramic capacitor 1 to a substrate or the like becomes easy. The method of forming the Sn plating layer can employ an electrolytic plating method. The preferable plating method is barrel plating.

[0146] (Laminating direction length and width direction length)

[0147] The length of each part of the internal layer portion 10 of the laminated ceramic capacitor 1 is explained based on Figure 4 Figure 4 Fig. 101 is a III-III line sectional view of the laminated ceramic capacitor 1 of Figure 1 Figure 4 Fig. 101 is a WT sectional view of the laminated body 2 at the length direction central position of the laminated body 2 of

[0148] ​​(laminate direction length)

[0149] The laminate direction length of the inner layer portion 10 is described. The width direction length of the inner layer portion 10 is shown as length D7. The width direction end portion of the inner layer portion 10 is shown as line W3. The length of half of the length D7 is set as length D8. The position, which is apart from the length D8 in the direction from the width direction end portion W3 to the other width direction end portion of the inner layer portion 10 in the width direction W, is shown as line Wl. The position of the line Wl is the width direction central position.

[0150] The length, which is equal to or more than 0.3% and equal to or less than 8.0% of the length D7, is set as length D9. In other words, the position, which is equal to or more than 0.3% and equal to or less than 8.0% of the length of the inner layer portion 10 in the direction from the end portion of the width direction W to the end portion of the width direction W of the inner layer portion 10, is the position included in the range of the length D9. The position, which is apart from the length D9 in the direction from the width direction end portion W3 to the other width direction end portion of the inner layer portion 10 in the width direction W, is shown as line W2. The position of the line W2 is set as the end portion vicinity position W2 in the width direction W of the inner layer portion 10. The end portion vicinity position W2 in the width direction W is set as the width direction end portion vicinity position W2.

[0151] The laminate direction length of the inner layer portion 10 at the width direction central position Wl is set as the first length Dl. The laminate direction length of the inner layer portion 10 at the width direction end portion vicinity position W2 is set as the second length D2. The laminate direction length of the inner layer portion 10 at the width direction end portion W3 is set as the third length D3.

[0152] (laminate direction length at width direction end portion vicinity position)

[0153] The second length D2 is longer than the first length Dl. The laminate direction length of the inner layer portion 10 is longer at the width direction end portion vicinity position W2 than at the width direction central position Wl.

[0154] The second length D2 is equal to or less than 102.6% of the first length Dl. Alternatively, the second length D2 is longer than the first length Dl, and the difference between the second length D2 and the first length Dl is equal to or less than 30 μm.

[0155] (laminate direction length at width direction end portion)

[0156] The third length D3 is shorter than the first length Dl. The laminate direction length of the inner layer portion 10 is shorter at the width direction end portion W3 than at the width direction central position Wl.

[0157] To summarize the above, the stacking length of the inner layer 10 is as follows: near the end in the width direction W2 > central position in the width direction W1 > end in the width direction W3.

[0158] The width direction length of the inner layer 10 is explained. The stacking direction length of the inner layer 10 is shown as D10. The stacking direction end of the inner layer 10 is shown as line T6. Half the length D10 is defined as length D11. The position of the inner layer 10 moving from the stacking direction end T6 to the other stacking direction end in the stacking direction T, away from length D11, is shown as line T4. The position of line T4 is the center position in the stacking direction.

[0159] The length D12 is defined as being 10% to 40% of the length D10. A line T5 is used to indicate a position away from the length D12, extending from the end T6 in the stacking direction towards the end of the inner layer 10 in another stacking direction T. The position of line T5 is defined as a position T5 near the end of the inner layer 10 in the stacking direction.

[0160] The width length of the inner layer 10 at the center position T4 in the stacking direction is set as the fourth length D4. The width length of the inner layer 10 at the near end position T5 in the stacking direction is set as the fifth length D5. The width length of the inner layer 10 at the end position T6 in the stacking direction is set as the sixth length D6.

[0161] The fifth length D5 is shorter than the fourth length D4. The width length of the inner layer 10 is shorter at position T5 near the end in the stacking direction than at position T4 in the length direction center.

[0162] The fifth length D5 is more than 97.5% but less than 100% of the fourth length D4. Alternatively, the fifth length D5 is longer than the fourth length D4, and the difference between the fifth length D5 and the fourth length D4 is less than 30 μm.

[0163] The sixth length D6 is shorter than the fifth length D5. The width length of the inner layer 10 is shorter at the end T6 in the stacking direction than at the position near the end T5 in the stacking direction.

[0164] To summarize the above, the width length of the inner layer 10 is: center position T4 in the stacking direction > near the end position in the stacking direction T5 > end position in the stacking direction T6.

[0165] (Raised area)

[0166] Figure 4 Figure 102 is an enlarged view of a portion of the inner layer 10. (See figure 102.) Figure 4The first internal electrode layer 6a and the second internal electrode layer 6b protrude in the stacking direction T from the second main surface M2 side toward the first main surface Ml side at the width direction end portion vicinity position W2 shown by the dashed-line enclosing frame Rl of the 102. For one internal electrode layer, the portion of the internal electrode layer at the width direction end portion vicinity position W2 that is located more on the first main surface Ml side than the position on the first main surface Ml side in the stacking direction T at the width direction central position Wl is provided as a protruding portion 30. The protruding portion 30 is formed by the internal electrode layer overlapping the second dielectric layer 5b or the like. By the presence of the protruding portion 30, the stacking direction length at the width direction end portion vicinity position W2 of the inner layer portion 10 becomes longer than the stacking direction length at the width direction central position Wl.

[0167] (Dielectric layer)

[0168] Based on Figure 4 The stacking direction lengths of the layers are explained with reference to the 102. The stacking direction lengths of the layers show the thicknesses of the layers. The stacking direction lengths of the dielectric layers are explained. The stacking direction length of the first dielectric layer 5a at the width direction central position Wl is provided as a length D21. The stacking direction length of the second dielectric layer 5b at the width direction end portion vicinity position W2 is provided as a length D22. The stacking direction length of the second dielectric layer 5b at the width direction end portion W3 is provided as a length D23.

[0169] The stacking direction length of the dielectric layer is longer at the width direction end portion vicinity position W2 than at the width direction central position Wl. The length D22 is longer than the length D21.

[0170] The stacking direction length of the dielectric layer is longer at the width direction end portion W3 than at the width direction end portion vicinity position W2. The length D23 is longer than the length D22.

[0171] (Internal electrode layer)

[0172] The stacking direction lengths of the internal electrode layers are explained. The internal electrode layers are explained with the first internal electrode layer 6a as an example. The contents explained with the first internal electrode layer 6a as an example are also the same in the second internal electrode layer 6b. The stacking direction length of the first internal electrode layer 6a at the width direction central position Wl is provided as a length D24. The stacking direction length of the first internal electrode layer 6a at the width direction end portion vicinity position W2 is provided as a length D25. The stacking direction length of the first internal electrode layer 6a at the width direction end portion W3 is provided as a length D26.

[0173] The stacking direction length of the first internal electrode layer 6a is shorter at the width direction end portion vicinity position W2 than at the width direction central position Wl. The length D25 is shorter than the length D24.

[0174] The layer-stacking direction length of the first internal electrode layer 6a is shorter at the width direction end portion W3 than at the position near the width direction end portion W2. The length D26 is shorter than the length D25.

[0175] (Layer-stacking direction length of element)

[0176] One element is formed by combining one dielectric layer and one internal electrode layer that is in contact with the dielectric layer. The sum of the layer-stacking direction length of the dielectric layer included in one element and the layer-stacking direction length of the internal electrode layer included in one element is set as the layer-stacking direction length of the element. The layer-stacking direction length of the element at the width direction central position Wl is the sum of the length D21 and the length D24. The layer-stacking direction length of the element at the position near the width direction end portion W2 is the sum of the length D22 and the length D25. The layer-stacking direction length of the element at the width direction end portion W3 is the sum of the length D23 and the length D26.

[0177] (Position near width direction end portion)

[0178] The increase in the length D22 in the dielectric layer from the length D21 is greater than the decrease in the length D25 in the internal electrode layer from the length D24. Therefore, the layer-stacking direction length of the element becomes longer at the position near the width direction end portion W2 than at the width direction central position Wl. As a result, the layer-stacking direction length of the inner layer portion 10 becomes longer at the position near the width direction end portion W2 than at the width direction central position Wl.

[0179] (Width direction end portion)

[0180] The increase in the length D23 in the dielectric layer from the length D21 is smaller than the decrease in the length D26 in the internal electrode layer from the length D24. Therefore, the layer-stacking direction length of the element becomes shorter at the width direction end portion W3 than at the width direction central position Wl. As a result, the layer-stacking direction length of the inner layer portion 10 becomes shorter at the width direction end portion W3 than at the width direction central position Wl.

[0181] (Electrostatic capacitance)

[0182] In the multilayer ceramic capacitor 1, the static capacitance of the multilayer ceramic capacitor 1 can be increased by the second length D2 being longer than the first length Dl. By increasing the length in the stacking direction of the inner layer portion 10 at the position W2 near the width direction end portion, the length in the stacking direction of the internal electrode layer at the position W2 near the width direction end portion included in the position can be increased. If the length in the stacking direction of the internal electrode layer is increased, the static capacitance is increased. In the multilayer ceramic capacitor 1, the length in the stacking direction of the internal electrode layer does not sharply decrease from the length D24 at the position Wl in the width direction center to the length D26 at the position W3 in the width direction end portion in two stages as the position Wl in the width direction center is approached toward the position W3 in the width direction end portion. The length in the stacking direction of the internal electrode layer at the position W2 near the width direction end portion between the position Wl in the width direction center and the position W3 in the width direction end portion becomes the length D25 which is longer than the length D26 at the position W3 in the width direction end portion. This is because the length in the stacking direction of the internal electrode layer at the position W2 near the width direction end portion is increased by the presence of the protrusion portion 30.

[0183] The length in the stacking direction of the internal electrode layer at the position W2 near the width direction end portion is longer than that at the position W3 in the width direction end portion. Therefore, a large static capacitance can be generated by the inner layer portion 10.

[0184] By forming the portion in which the length in the stacking direction of the internal electrode layer is longer at the position W2 near the width direction end portion, the static capacitance can be generated with high precision. Thus, the precision of the static capacitance generated by the multilayer ceramic capacitor 1 can be improved.

[0185] In the process of manufacturing the multilayer ceramic capacitor 1, the laminated sheet is sometimes pressed in the stacking direction T. By the pressing, the length in the stacking direction of the inner layer portion 10 sometimes becomes shorter at the position W3 in the width direction end portion than at the position Wl in the width direction center. If the length in the stacking direction of the inner layer portion 10 at the position W3 in the width direction end portion is shortened, the reliability of the multilayer ceramic capacitor 1 is sometimes decreased. The length in the stacking direction of the inner layer portion 10 at the position Wl in the width direction center is sometimes increased so that the length in the stacking direction of the inner layer portion 10 at the position W3 in the width direction end portion is not shortened. In order to increase the length in the stacking direction of the inner layer portion 10 at the position Wl in the width direction center, for example, the length in the stacking direction of the dielectric layer is considered to be increased. The increase of the length in the stacking direction of the dielectric layer becomes a main cause of the decrease of the static capacitance of the multilayer ceramic capacitor 1.

[0186] In the multilayer ceramic capacitor 1, at the position W2 near the width direction end portion, a portion of the inner layer portion 10 is formed, which has a longer length in the stacking direction than the width direction end portion W3. Therefore, it is possible to suppress the reduction in the length in the length direction of the inner layer portion 10 at the width direction end portion W3. Therefore, it is not necessary to increase the length in the stacking direction of the inner layer portion 10 at the width direction central position W1. This means that it is not necessary to increase the length in the stacking direction of the dielectric layer. Therefore, in the multilayer ceramic capacitor 1, it is possible to increase the electrostatic capacitance.

[0187] (Strength)

[0188] In the multilayer ceramic capacitor 1, by making the second length D2 longer than the first length D1, it is possible to improve the strength against electric field of the multilayer ceramic capacitor 1. The multilayer ceramic capacitor 1 is sometimes exposed to a strong electric field at the end portion. If the multilayer ceramic capacitor 1 is exposed to a strong electric field, sometimes, dielectric breakdown occurs in the multilayer ceramic capacitor 1. In the multilayer ceramic capacitor 1, the length in the stacking direction of the dielectric layer is longer at the position W2 near the width direction end portion than at the width direction central position W1. Further, at the width direction end portion W3, the length in the stacking direction of the dielectric layer is longer than at the position W2 near the width direction end portion.

[0189] Therefore, the multilayer ceramic capacitor 1 of the present disclosure can improve the strength against electric field at the end portion.

[0190] Based on Figure 5A , Figure 5B and Figure 6 , the manufacturing method of the multilayer ceramic capacitor 1 is explained in more detail. The process of printing the conductive paste for the internal electrode layer and the like on the dielectric sheet in a given pattern is explained. Figure 5A is a view showing the state in which the conductive paste 42 for the internal electrode layer and the paste 44 for the step reduction are printed on the dielectric sheet. Figure 5A is a plan view of a face parallel to the length direction L and the width direction W. Figure 5B is a view showing two stacked dielectric sheets 40. Figure 6 is Figure 5A a W-W' cross-sectional view of

[0191] As shown in Figure 5A , the conductive paste 42 for the internal electrode layer is printed on the dielectric sheet in a given pattern. The dielectric sheet is not shown in Figure 5A . The dielectric sheet 40 is shown in Figure 5B and Figure 6 . In Figure 5AThe internal electrode layer pattern shown has recesses 50 provided at both widthwise ends in the vicinity of the central position in the lengthwise direction. The so-called recess 50 refers to a portion in which a part of the external shape of the internal electrode layer pattern is cut away. The configuration of the internal electrode layer pattern provided with the recess 50 is also referred to as a racket configuration. Note that the internal electrode layer pattern is not limited to this racket configuration. Further, the internal electrode layer pattern can also be configured as a pattern provided with no recess 50.

[0192] A step-reducing paste 44 is disposed around the pattern of the conductive paste 42 for the internal electrode layer. The step-reducing paste 44 is printed on the dielectric sheet 40 before the conductive paste 42 for the internal electrode layer is printed on the dielectric sheet 40.

[0193] The conductive paste 42 for the internal electrode layer is printed so that a portion thereof overlaps the step-reducing paste 44. This will be described based on Figure 6 The widthwise length of the portion of the conductive paste 42 for the internal electrode layer that overlaps the conductive paste 42 is shown as length D31. The length D31 is referred to as the overlap length. The length of the overlap length D31 can be appropriately decided. The length of the overlap length D31 can be set to 50 μm, for example.

[0194] Figure 6 The structure in which the conductive paste 42 overlaps the step-reducing paste 44 means that the conductive paste 42 is formed after the step-reducing paste 44 is formed. In the case where the conductive paste 42 is formed after the step-reducing paste 44 is formed, the positions of the ends in the lengthwise direction L of the internal electrode layer are easily aligned in the later multilayer body 2. This is because the step-reducing paste 44 functions as a dam for the conductive paste 42 at the time of formation of the conductive paste 42.

[0195] Note that the order of formation of the step-reducing paste 44 and the conductive paste 42 can also be the order in which the step-reducing paste 44 is formed after the conductive paste 42 is formed. Even with such an order of formation, a multilayer ceramic capacitor 1 having the preferable first length D1 and second length D2 can be obtained.

[0196] The portion of the conductive paste 42 for the internal electrode layer that overlaps the step-reducing paste 44 is provided as an overlap portion 46. This overlap portion 46 becomes the Figure 4 raised portion 30 in the inner layer portion 10 shown as 102.

[0197] The printing thicknesses of the step-reducing paste 44 and the conductive paste 42 for the internal electrode layer will be described. Figure 6 The length D32 shows the printing thickness of the step-reducing paste 44. Figure 6The length D33 shows the printing thickness of the conductive paste 42 for the internal electrode layer. The length D32 and the length D33 can be appropriately set. The ratio of the length D32 to the length D33, i.e., D32 / D33, can be set to 0.5, for example.

[0198] By appropriately setting the overlapping length D31 and the value of D32 / D33, it is possible to form the internal layer portion 10 having the configuration as shown in FIG. 1. Figure 4

[0199] As for the length in the width direction W of the internal layer portion 10, at the time of lamination, it is slowly stacked in a state without a step countermeasure, and in pressing, the portion of the outer layer is locally pressed into the gap portion using rubber, whereby it is possible to manufacture D6 < D5 < D4.

[0200] Based on the above, Figure 5B The lamination of the dielectric sheets 40 on which the conductive paste 42 for the internal electrode layer is printed will be described. In the present embodiment, two dielectric sheets 40 are shown for the purpose of describing the method of lamination. The dielectric sheets 40 are sequentially laminated in a given number of sheets by the method of lamination shown in FIG. 2. Figure 5B Figure 5B The dielectric sheets 40 are laminated with the positions in the length direction L being shifted by one sheet. The two dielectric sheets 40 laminated continuously are provided as a first dielectric sheet 40A and a second dielectric sheet 40B. The second dielectric sheet 40B is laminated to the first dielectric sheet 40A in a state in which the length in the length direction L is shifted by about half the length in the length direction L of the dielectric sheet 40 with respect to the first dielectric sheet 40A.

[0201] The laminate of the dielectric sheets 40 laminated in a given number of sheets is cut at a given site. In the present embodiment, the position of the cut is shown by a line L1 and a line L2. After the cut, the cut product is subjected to firing, whereby the laminate 2 is obtained.

[0202] The laminate of the dielectric sheets 40 laminated in a given number of sheets is cut at a given site. In the present embodiment, the position of the cut is shown by a line L1 and a line L2. After the cut, the cut product is subjected to firing, whereby the laminate 2 is obtained. Figure 5B In the state of the laminate 2, the conductive paste 42 printed on the internal electrode layer of the first dielectric sheet 40A becomes the first internal electrode layer 6a. On the other hand, the conductive paste 42 printed on the internal electrode layer of the second dielectric sheet 40B becomes the second internal electrode layer 6b.

[0203] In the conductive paste 42 for the internal electrode layer, in order to form the recess 50, the start point of the length in the width direction W is shortened to a first recess end portion 51 and a second recess end portion 52. The first recess end portion 51 and the second recess end portion 52 are in positions opposed in the width direction W. The line connecting the first recess end portion 51 and the second recess end portion 52 is shown by a line L3.

[0204]

[0205] ​​​In the conductive paste 42 used in the inner electrode layer, the ends in the length direction L are designated as the first quadrangular end 53 and the second quadrangular end 54. The first quadrangular end 53 and the second quadrangular end 54 are positioned opposite each other in the width direction W. The line connecting the first quadrangular end 53 and the second quadrangular end 54 is shown as line L4.

[0206] In the stacked ceramic capacitor 1 of this embodiment, when the first dielectric sheet 40A and the second dielectric sheet 40B are stacked, the lines L3 and L4 do not overlap. The direction in which line L3 deviates from line L4 is the direction in which line L3 does not overlap with the conductive paste 42 printed on the inner electrode layer of the stacked dielectric sheet 40. Figure 5B In the example shown, line L3 in the first dielectric sheet 40A does not deviate from the direction of overlap with the conductive paste 42 printed on the internal electrode layer of the second dielectric sheet 40B. Figure 5B In the diagram, the length by which lines L3 and L4 deviate is shown as length D50.

[0207] In the multilayer ceramic capacitor 1 of this embodiment, the dielectric sheets 40 are stacked such that lines L3 and L4 do not overlap. Therefore, in the fired multilayer 2, the internal electrode layer is as follows. Hereinafter, it is assumed that by... Figure 5B The internal electrode layer shown is formed by firing the conductive paste 42. (Refer to...) Figure 5B Let's now explain the internal electrode layer. Figure 5B In the figure, brackets are added to the reference numerals for the internal electrode layer.

[0208] In the multilayer ceramic capacitor 1 of this embodiment, although a recess 50 is formed, the first lead electrode portion 8a of the outer layer portion LG1 on the first end face side has a portion whose length in the width direction W is the same as that of the first counter electrode portion 7a of the opposing portion LF in the length direction. The portion shown by the length D50 is the portion where the length in the width direction W of the first lead electrode portion 8a is the same as the length in the width direction W of the first counter electrode portion 7a.

[0209] exist Figure 5B In the diagram, the length of the width direction W of the first opposing electrode portion 7a of the longitudinally opposed portion LF is shown as length D51. Furthermore, the length of the width direction W of the first lead-out electrode portion 8a of the first end-face side outer layer portion LG1 is shown as length D52 within the range indicated by D50. The length of the width direction W of the first lead-out electrode portion 8a of the first end-face side outer layer portion LG1 is shown as length on line L1 as D53. Line L1 is a line corresponding to the end face of the laminate 2. D52 is equal to D51. Furthermore, D53 is shorter than both D51 and D52. This is because a recess 50 is formed.

[0210] By being configured as described above, the reliability of the vicinity of the boundary of the first end surface side outer layer portion LG1 and the length direction opposing portion LF can be improved. In addition, the above description is made taking the first end surface side outer layer portion LG1 as an example, but the same applies to the second end surface side outer layer portion LG2.

[0211] (Measurement method)

[0212] The length of each portion in the laminated ceramic capacitor 1, the laminate 2, the inner layer portion 10, and the like can be measured with a micrometer or an optical microscope. For example, the laminated ceramic capacitor 1 is ground to a desired position such as the length direction central position. Then, the cross section exposed by the grinding is observed with an optical microscope or the like, whereby the length can be measured.

[0213] The embodiments of the present application have been described above, but the present application is not limited to the foregoing embodiments, and various modifications and alterations can be made.

[0214] For example, the step lowering paste 44 can also be printed on the dielectric sheet 40 after the conductive paste 42 for the internal electrode layer is printed on the dielectric sheet 40.

[0215] The conductive paste 42 for the internal electrode layer and the step lowering paste 44 can also be disposed on the edges along the width direction W in addition to the edges along the length direction L in the outer shape of the internal electrode layer pattern.

[0216] <1>

[0217] A laminated ceramic capacitor has:

[0218] A laminate has a plurality of laminated dielectric layers, and a plurality of first internal electrode layers and a plurality of second internal electrode layers laminated on the dielectric layers, and has a first main surface and a second main surface opposing in a laminating direction, a first end surface and a second end surface opposing in a length direction orthogonal to the laminating direction, and a first side surface and a second side surface opposing in a width direction orthogonal to the laminating direction and the length direction;

[0219] A first external electrode is disposed on the first end surface; and

[0220] A second external electrode is disposed on the second end surface,

[0221] wherein

[0222] The laminate has:

[0223] An inner layer portion in which the plurality of first internal electrode layers and the plurality of second internal electrode layers oppose; and

[0224] An outer layer portion composed of a dielectric material,

[0225] a length of the inner layer portion in a direction parallel to the stacking direction at a position where a length of the inner layer portion in a direction parallel to the stacking direction at the central position in the width direction of the inner layer portion is set to a first length, and

[0226] a length of the inner layer portion in a direction parallel to the stacking direction at a position where a length of the inner layer portion in a direction parallel to the stacking direction at the central position in the width direction of the inner layer portion is set to a first length, and

[0227] the second length is longer than the first length.

[0228] <2>

[0229] The multilayer ceramic capacitor according to <1>, in which

[0230] the second length is 102.6% or less of the first length.

[0231] <3>

[0232] The multilayer ceramic capacitor according to <1>, in which

[0233] the second length is longer than the first length,

[0234] a difference between the second length and the first length is 30 pm or less.

[0235] <4>

[0236] The multilayer ceramic capacitor according to any one of <1> to <3>, in which

[0237] a length of the inner layer portion in a direction parallel to the stacking direction at the central position in the stacking direction of the inner layer portion is set to a fourth length, and

[0238] the fourth length is shorter than the first length.

[0239] <5>

[0240] The multilayer ceramic capacitor according to any one of <1> to <4>, in which

[0241] a length of the inner layer portion in a direction parallel to the stacking direction at the central position in the stacking direction of the inner layer portion is set to a fourth length, and

[0242] When a length of the inner layer portion in a direction parallel to the width direction at a position of the inner layer portion at which a length in a direction from an end portion of the stacking direction of the inner layer portion to the central position of the inner layer portion in the stacking direction is 10% or more and 40% or less of a length of the inner layer portion in the stacking direction is set as a fifth length,

[0243] The fifth length is shorter than the fourth length.

[0244] <6>

[0245] The laminated ceramic capacitor according to <5>, wherein

[0246] When a length of the inner layer portion in a direction parallel to the width direction at the end portion of the inner layer portion in the stacking direction is set as a sixth length,

[0247] The sixth length is shorter than the fifth length.

[0248] <7>

[0249] The laminated ceramic capacitor according to any one of <1> to <6>, wherein

[0250] a portion of the first internal electrode layer and the second internal electrode layer disposed in the inner layer portion is set as an opposing electrode portion, and

[0251] When a portion of the first internal electrode layer disposed between the inner layer portion and the first end surface and a portion of the second internal electrode layer disposed between the inner layer portion and the second end surface are set as lead-out electrode portions,

[0252] The lead-out electrode portions have a length in the width direction that is the same as a length in the width direction of the opposing electrode portion.

[0253] Explanation of Reference Numerals

[0254] 1 Laminated ceramic capacitor

[0255] 2 Laminated body

[0256] 3 Outer dielectric layer

[0257] 4 Inner dielectric layer

[0258] 5a First dielectric layer

[0259] 5b Second dielectric layer

[0260] 6a First internal electrode layer

[0261] 6b Second internal electrode layer

[0262] 10 inner layer portion

[0263] 20a first external electrode

[0264] 20b second external electrode

[0265] 30 raised portion

[0266] 40 dielectric sheet

[0267] 42 conductive paste for internal electrode layer

[0268] 44 paste for step reduction

[0269] 46 overlapping portion

[0270] 50 recess

[0271] IL inner layer range

[0272] LF lengthwise opposite portion

[0273] WF widthwise opposite portion

Claims

1. A multilayer ceramic capacitor, comprising: A laminate has a plurality of stacked dielectric layers, a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked on the dielectric layers, and has a first main surface and a second main surface opposite to each other in the stacking direction, a first end surface and a second end surface opposite to each other in the length direction orthogonal to the stacking direction, and a first side surface and a second side surface opposite to each other in the width direction orthogonal to the stacking direction and the length direction. A first external electrode is disposed on the first end face; and The second external electrode is disposed on the second end face. in, The laminate has: The inner layer portions of the plurality of first inner electrode layers and the plurality of second inner electrode layers facing each other; and The outer layer is made of dielectric material. The length of the inner layer portion at the center position in the width direction, in the direction parallel to the stacking direction, is defined as the first length, and When the length of the inner layer portion in the direction parallel to the stacking direction, which is at least 0.3% and less than 8.0% of the length of the inner layer portion in the width direction, is defined as the second length, then... The second length is longer than the first length.

2. The multilayer ceramic capacitor according to claim 1, wherein, The second length is less than 102.6% of the first length.

3. The multilayer ceramic capacitor according to claim 1, wherein, The second length is longer than the first length. The difference between the second length and the first length is less than 30 μm.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, When the length of the inner layer portion at its end in the width direction, in the direction parallel to the stacking direction, is set as the third length, The third length is shorter than the first length.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, The length of the inner layer in the direction parallel to the width direction, located at the center of the stacking direction, is defined as the fourth length. When the length of the inner layer portion in the direction from its end in the stacking direction to its center in the stacking direction is 10% to 40% of the length of the inner layer portion in the stacking direction, and the length of the inner layer portion in the direction parallel to the width direction is defined as the fifth length, The fifth length is shorter than the fourth length.

6. The multilayer ceramic capacitor according to claim 5, wherein, When the length of the inner layer portion at its end in the stacking direction, in the direction parallel to the width direction, is set as the sixth length, The sixth length is shorter than the fifth length.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein, The portions disposed in the inner layer portion of the first inner electrode layer and the second inner electrode layer are designated as opposing electrode portions, and When the portion of the first inner electrode layer disposed between the inner layer and the first end face, and the portion of the second inner electrode layer disposed between the inner layer and the second end face are designated as lead-out electrode portions, The length in the width direction of the lead-out electrode portion at the first end face or the second end face is shorter than the length in the width direction of the opposing electrode portion. The lead-out electrode portion has a portion whose length in the width direction is the same as the length in the width direction of the opposing electrode portion.

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